JPH05260106A - Carrier reproducting circuit - Google Patents

Abstract

PURPOSE:To improve C/N to obtain a flat phase characteristic and to reproduce the carrier of a high-speed modulated signal by adding a moving average circuit and taking the moving average of carrier components to slowly limit the band of carrier components. CONSTITUTION:An input modulated signal (a) is distributed to an inverse modulator (carrier component extracting circuit) 12 through an orthogonal detector 10 and a delay line 11. The inverse modulator 12 extracts a carrier component (a) and inputs it to a moving average circuit 13 which is operated at the clock speed of a frequency (f) corresponding to a signal (a). The circuit 13 converts it to a carrier component c2 obtained by taking the moving average for n clocks, and this component c2 is inputted to a latch circuit 14. The circuit 14 thins this component at the clock speed of f/n to obtain a carrier component c3, and this component c3 is inputted to a digital filter 15 operated at the clock speed of f/nHz. Thus, the digital filter constituting a carrier reproducing filter is operated at the low-speed clock signal, and high C/N and the flat phase characteristic are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit for recovering a carrier in a synchronous detection circuit for digitally modulated signals.

[0002]

2. Description of the Related Art A demodulator for demodulating a digital phase-modulated signal represented by a PSK (Phase Shift Keying) signal is constructed by a digital circuit, and further downsizing, no adjustment and low power consumption are achieved by using an LSI. A circuit configuration method to be achieved is being studied. As one of the methods of constructing a carrier recovery circuit in such a digital demodulator, an inverse modulation tank having a feature that the carrier slip ratio is small in a line having a low C / N ratio (signal to noise power ratio) such as a satellite line. A limiter system is known (for example, the 1990 Autumn National Conference of the Institute of Electronics, Information and Communication Engineers B-170).

When the inverse modulation tank limiter system is used for a demodulator in time division multiple access communication, even if there is a frequency difference between burst signals that cannot be compensated by an automatic frequency control circuit that compensates for the average frequency deviation of burst signals. , It is necessary to keep the bit error rate and the carrier slip rate low. For that purpose, a high C / N ratio is used as a carrier recovery filter that filters the carrier component extracted by the inverse modulator.
The improvement ratio and small phase rotation between input and output are required even when the input frequency is far from the center frequency of the filter.

FIG. 4 is a block diagram showing a configuration example of a conventional phase modulation signal demodulator which employs an inverse modulation tank limiter system. In the figure, the input modulation signal a is the quadrature detector 10
Is distributed to the inverse modulator 12 via the delay line 11. The inverse modulator 12 phase-modulates the input modulation signal a with the demodulated signal b output from the quadrature detector 11 in an opposite phase to remove the modulation component and extracts the carrier component c. The carrier component c has a noise component removed by a digital filter 15, and a limiter circuit 16 reproduces a carrier wave d having a constant amplitude.
Becomes The reproduced carrier wave d is input to the quadrature detector 11 and used for detection processing. The quadrature detector 10, the inverse modulator 12, the digital filter 15 and the limiter circuit 16 are operated by a clock signal corresponding to the speed of the input modulation signal a.

In such an inverse modulation tank limiter type carrier recovery circuit, the inverse modulator 12 corresponds to a carrier component extraction circuit, and the digital filter 15 and the limiter circuit 16 correspond to a carrier recovery filter.

Here, the frequency spectrum of the carrier component c in the conventional phase modulation signal demodulator, the amplitude characteristic and the phase characteristic of the digital filter 15, and the frequency spectrum of the reproduced carrier wave d are shown in FIGS. 5 (1), (2) and (3). ). As shown in (1), the carrier wave component c output from the inverse modulator 12 contains a wideband noise component, and by passing through the digital filter 15 having the amplitude characteristic and the phase characteristic shown in (2), ( As shown in 3), the reproduced carrier wave d from which the noise component is removed is obtained.

By the way, the maximum operation speed of the conventional demodulator is the digital filter 1 having a multi-bit multiplication circuit.
It is almost determined by the operating speed of 5. Therefore, when operating the demodulator beyond the operating speed of the multiplication circuit in the digital filter 15, the digital filter 15
It was necessary to use the thinned clock pulse for.

FIG. 6 shows a conventional configuration of a phase modulation signal demodulator when the digital filter 15 is operated with a low speed clock signal. In FIG. 6, the inverse modulator 12 operates with the clock signal of f [Hz] corresponding to the input modulation signal a and extracts the carrier component c. On the other hand, the frequency divider 17 divides the clock signal of f [Hz] by n to generate f / n.
A clock signal of [Hz] is generated and given to the latch circuit 14, the digital filter 15, and the limiter circuit 16.
The carrier component c extracted by the inverse modulator 12 becomes the carrier component c1 decimated at the clock speed of f / n [Hz] by the latch circuit 14, and is a digital filter operating at the clock speed of f / n [Hz]. 15 is input. Similarly,
The carrier wave component c1 has a noise component removed by the digital filter 15, and becomes a reproduced carrier wave d1 having a constant amplitude by the limiter circuit 16.

Here, the frequency spectrum of the carrier component c, the frequency spectrum of the carrier component c1 when n = 2, the amplitude characteristic and the phase characteristic of the digital filter 15, and the frequency spectrum of the reproduced carrier d1 are shown in FIGS. 2),
Shown in (3) and (4). The decimated carrier component c1 causes a noise component to be folded due to the clock speed being converted to f / 2, and the noise power density is doubled as compared with the carrier component c as shown in (2). ..

[0010]

In the conventional configuration shown in FIG. 4, the digital filter 1 having a multi-bit multiplication circuit is used.
It was difficult to increase the speed of the demodulator because the upper limit of the operating speed was determined by the operating speed of 5. That is, it was not possible to deal with high-speed modulation signals.

On the other hand, in the conventional configuration shown in FIG. 6, if the pass band width of the digital filter 15 is made the same as that of the digital filter in the configuration of FIG. 4, the C / N ratio of the reproduced carrier wave d1 as shown in FIG. 7 (4). Deteriorate, and as a result, the bit error rate of the demodulator and the slip rate characteristic of the carrier deteriorate. Further, when the pass band width of the digital filter 15 is set to 1 / n times in order to prevent the deterioration of the C / N ratio of the reproduced carrier wave d1, the phase characteristic becomes steep and the phase rotation increases with respect to the frequency fluctuation of the input signal. Similarly, the bit error rate of the demodulator and the slip rate characteristic of the carrier are deteriorated.

The present invention is a carrier recovery filter having a high C /
An object of the present invention is to provide a carrier recovery circuit which can obtain an N improvement ratio and a flat phase characteristic and can perform carrier recovery of a high speed modulation signal.

[0013]

According to the present invention, a carrier component extraction circuit for removing a modulation component from an input modulation signal by a non-linear operation to extract a carrier component, and only a carrier component is passed from an output of the carrier component extraction circuit. In the carrier regeneration circuit having a carrier regeneration filter that removes noise and other unnecessary components and outputs a reproduced carrier, the carrier regeneration filter operates with a clock signal at a speed f corresponding to the input modulated signal, A moving average circuit for taking a moving average of the carrier component extracted by the carrier component extracting circuit over n clocks (n is an integer), and a clock signal of a speed f / n obtained by dividing the clock signal of the speed f by n. A latch circuit for latching the carrier wave component output from the moving average circuit, and an output from the latch circuit, which operates by the clock signal of the speed f / n Characterized by comprising a digital filter for outputting a reproduced carrier wave obtained by removing the unnecessary component from the carrier wave component.

[0014]

In the moving average circuit added in the present invention, the moving average circuit operates with the clock signal of speed f corresponding to the input modulation signal, and the moving average of the carrier components extracted by the carrier component extracting circuit is taken over n clocks. Therefore, the carrier component can be gently band-limited to increase the C / N ratio by n times. Therefore, even if the latch circuit performs the thinning-out process with the clock signal of the speed f / n, it is possible to prevent the noise power density from increasing due to the band limitation performed by the moving average circuit.

With such a configuration, the digital filter in the next stage can be operated with a clock signal of speed f / n, and a high C / N improvement ratio can be realized even with pass band characteristics similar to the conventional one. At the same time, since the phase rotation by the moving average circuit can be made extremely small, a flat phase characteristic can be obtained.

[0016]

1 is a block diagram showing the construction of an embodiment in which the carrier recovery circuit of the present invention is applied to an inverse modulation tank limiter system.

In the figure, an input modulation signal a is distributed to an inverse modulator 12 via a quadrature detector 10 and a delay line 11. The inverse modulator 12 phase-modulates the input modulation signal a with the demodulated signal b output from the quadrature detector 11 in an opposite phase to remove the modulation component and extracts the carrier component c. The carrier wave component c is input to the moving average circuit 13 which operates at a clock speed of f [Hz] corresponding to the input modulation signal, and is converted into a carrier wave component c2 which is a moving average over n clocks. This carrier wave component c2 is input to the latch circuit 14, becomes a carrier wave component c3 thinned out at the clock speed of f / n [Hz], and is input to the digital filter 15 operating at the clock speed of f / n [Hz]. .. Similarly, the carrier component c3 has a noise component removed by the digital filter 15, and becomes a reproduced carrier d2 having a constant amplitude by the limiter circuit 16. This reproduced carrier wave d2 is used by the quadrature detector 1
It is input to 0 and used for detection processing. In addition, frequency divider 1
7 divides the clock signal of f [Hz] by n to f / n [H
The clock signal of z] is generated and given to the latch circuit 14, the digital filter 15, and the limiter circuit 16.

In the carrier recovery circuit of this embodiment, the inverse modulator 12 corresponds to the carrier component extraction circuit, and the moving average circuit 1
3, the latch circuit 14, the digital filter 15, and the limiter circuit 16 correspond to a carrier wave reproduction filter.

The function of the carrier recovery filter in this embodiment will be described below with reference to FIG. In FIG. 3, (1) is the frequency spectrum of the carrier component c in the phase modulation signal demodulator of this embodiment, and (2) is the moving average circuit 13
Amplitude characteristic and phase characteristic, (3) is the frequency spectrum of the carrier component c2, and (4) is the carrier component c3 when n = 2.
, (5) shows the amplitude characteristic and phase characteristic of the digital filter 15, and (6) shows the frequency spectrum of the reproduced carrier d2.

The carrier component c output from the inverse modulator 12
Is a carrier component c2 whose band is gradually band-limited by the moving average circuit 13 to increase the C / N ratio by n times as shown in (3). Next, the latch circuit 14 causes f / n [H
When the carrier component c2 is thinned out at the clock speed of z], the noise component is folded back, but since the moving average circuit 13 limits the band, it is possible to prevent an increase in noise power density as shown in (4). ..

Therefore, as shown in (5), the pass band width of the digital filter 15 for processing the carrier wave component c3 is as shown in FIG. 5 (2).
, (7) (3)), but as shown in (6), C /
It is possible to avoid the deterioration of the N ratio. On the other hand, the phase rotation is the sum of the phase rotations of the moving average circuit 13 and the digital filter 15, but when n is as small as 2, the phase rotation by the moving average circuit 13 is extremely small, so its influence is almost ignored. can do.

FIG. 2 is a block diagram showing a configuration example of the moving average circuit 13. In the figure, when n = 2, the moving average circuit 13 outputs the delay circuit 20 for delaying the carrier wave component c by one clock, the 1-bit shift circuit 21 for inputting the carrier wave component c, and the carrier wave component c. A 1-bit shift circuit 22 input through the delay circuit 20 and an adder circuit 23 that adds the outputs of the 1-bit shift circuits 21 and 22. A carrier component obtained by taking a moving average from the adder circuit 23 over two clocks. Output c2.

As described above, the moving average circuit 13 can be realized with an extremely simple structure, and therefore can be sufficiently operated even at the clock speed of f [Hz] corresponding to the high speed input modulation signal a. The digital filter 15 can be operated with a low-speed clock signal of f / n [Hz] as in the conventional case.

[0024]

As described above, since the digital filter constituting the carrier wave reproducing filter can be operated by the low speed clock signal, the carrier wave reproducing circuit corresponding to the high speed modulated signal can be realized. Furthermore, in the carrier recovery filter, when the carrier component extracted by the clock signal corresponding to the input modulation signal is thinned out by the low-speed clock, it is possible to effectively suppress an increase in noise power density, which results in a high C / N improvement ratio. A flat phase characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment when a carrier recovery circuit of the present invention is applied to an inverse modulation tank limiter system.

FIG. 2 is a block diagram showing a configuration example of a moving average circuit 13.

FIG. 3 is a diagram illustrating a function of a carrier recovery filter according to an embodiment.

FIG. 4 is a block diagram showing a configuration example of a conventional phase modulation signal demodulator that employs an inverse modulation tank limiter system.

FIG. 5 is a diagram illustrating a function of a conventional carrier recovery filter.

FIG. 6 is a block diagram showing a conventional configuration example of a phase modulation signal demodulator when a digital filter is operated with a low-speed clock signal.

FIG. 7 is a diagram illustrating the function of a conventional carrier recovery filter that operates with a low-speed clock signal.

[Explanation of symbols]

 10 quadrature detector 11 delay line 12 inverse modulator 13 moving average circuit 14 latch circuit 15 digital filter 16 limiter circuit 17 frequency divider 20 delay circuit 21, 22 1-bit shift circuit 23 adder circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shuzo Kato 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. A carrier component extraction circuit for removing a modulation component from an input modulation signal by a non-linear operation to extract a carrier component, and only a carrier component is passed from an output of the carrier component extraction circuit to eliminate noise and other unnecessary components. In a carrier recovery circuit including a carrier recovery filter that removes and outputs a recovered carrier, the carrier recovery filter operates with a clock signal at a speed f corresponding to the input modulation signal, and is extracted by the carrier component extraction circuit. A moving average circuit for taking a moving average of the carrier component over n clocks (n is an integer), and a clock signal of a speed f / n obtained by dividing the clock signal of the speed f by n are output from the moving average circuit. A latch circuit for latching a carrier wave component; and a carrier wave component which is operated by the clock signal of the speed f / n and which is output from the latch circuit. Carrier recovery circuit, characterized in that a digital filter for outputting a reproducing carrier to remove unnecessary components.