JP2003188748A - Rds decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an RDS decoder which can reduce man-hour of processing related to the extraction of an RDS signal from an FM compounded audio signal and can be easily integrated into a digital signal processing system for performing main audio signal processing. <P>SOLUTION: The RDS decoder has synchronous demodulation means 1 for generating a baseband RDS signal by inputting the FM compounded audio signal obtained by multiplexing the RDS signal based on digital data on an FM audio signal and a data restoring means 2 for restoring the digital data from the baseband RDS signal. In the synchronous demodulation means 1, an input signal is converted to two baseband signals of orthogonal phases, unwanted component is removed from these signals, and the baseband RDS signal is generated by detecting and correcting a residual phase error. In the data restoring means 2, a phase error between the data of a conversion ratio adjusted by a sampling frequency converting means 6 and a transmission symbol timing is detected, and on the basis of the phase error, the conversion ratio is adjusted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an R used in a radio data system (RDS) for transmitting an RDS signal based on digital data on an FM voice signal.
It relates to a DS decoder.

[0002]

2. Description of the Related Art In RDS broadcasting, an FM audio signal having a pilot signal of 19 kHz and an RDS signal modulated in a frequency band (57 kHz) three times as high as that of the pilot signal are superimposed and transmitted (that is, multiplex transmission). Has been adopted. The transmitted RDS signal is obtained by subjecting differentially encoded binary time-series data to two-phase phase modulation (BPSK), and subjecting a 57 kHz subcarrier to double-sided modulation with this BPSK signal. An RDS radio receiver is used to receive the RDS broadcast. The RDS radio receiver has an RDS decoder for demodulating and decoding the RDS signal, in addition to a receiving circuit (FM tuner unit) for receiving the FM broadcast signal and a digital audio signal processing circuit for reproducing the voice. . FIG. 7 is a block diagram showing the configuration of a conventional RDS decoder disclosed in Japanese Patent No. 2593079.

In the RDS decoder shown in FIG. 7,
The band pass filter (BPF) 101 extracts only the RDS signal centered at 57 kHz from the FM composite audio signal obtained by detecting the FM broadcast signal. The subcarrier reproducing means 103 is an RD that is modulated on both sides and has no carrier.
The S signal is synchronously detected, and a reproduced carrier signal having the same phase and frequency as the RDS subcarrier is provided to the multiplier 102. The subcarrier reproducing means 103 is configured as, for example, a Costas loop type phase locked loop.

The output of the multiplier 102 is the baseband RD.
The S signal and the unnecessary component signal of 114 kHz are included. A low pass filter (LPF) 104 removes unnecessary component signals and outputs a baseband RDS signal. Also, LPF
The 104 also has a function of improving the performance of the RDS decoder by eliminating noise by passing only the spectrum required for decoding.

The symbol clock reproducing means 106 is an LP
From the baseband RDS signal output from F104,
A BPSK symbol break is detected. The symbol clock reproducing means 106 has a symbol clock cycle of 57 k.
Utilizing the fact that it is 48 times the Hz subcarrier period, the symbol clock period (symbol rate 1187.5H
z), and the phase of the BPSK signal is determined by utilizing the fact that the BPSK signal always has a zero cross point in the center of its waveform.

The inverting amplifier 105 is an inverting amplifier having a gain of one.
It is a vessel. The switch 107 is a symbol clock reproduction hand.
The symbol clock (waveform of FIG. 7) provided from the stage 106
SC). Switch 107 is a symbol
The first half cycle of one clock cycle (symbol period)
Baseband RDS signal (waveform in Fig. 7)
R ₁) Is given to the integrator 109, and the latter half of the symbol period
During the cycle period, the output from the inverting amplifier 105 (see FIG. 7)
Waveform R_Two) Is given to the integrator 109. As a result, BP
When the SK modulation phase is 0 degree, the product is obtained over the entire symbol period.
For example, a positive potential is applied to the divider 109 and BPSK
If the modulation phase is 180 degrees, the product will be
A negative potential is applied to the divider 109, for example.

The result of integration by the integrator 109 (waveform R _{3 in} FIG. 7) is determined by the slicer 110 at the end of the symbol period to be decoded as binary data. The processing performed in synchronization with this symbol period is called the integrated and dump processing. The switch 108 is once closed at the beginning of the symbol period to initialize the state of the integrator 109.

The flip-flop circuit 111 takes in the output of the slicer 110 at the last timing of the symbol period (also the first timing of the next symbol),
Hold that value at the output for the next symbol period. The flip-flop circuit 112 is the flip-flop circuit 1 of the previous stage.
The output of 11 is held with a delay of one symbol period. Therefore,
The exclusive OR circuit (XOR) 113 gives an output of "true" when the data carried in the BPSK symbol are different from each other in time series, and "false" when they are the same. Perform dynamic decoding.

[0009]

As described above,
The conventional RDS decoder is configured as a circuit dedicated to a decoding process, and first, a process for extracting an RDS signal from an FM composite audio signal is performed by a BPF 101 that allows a signal in a band centered on a subcarrier to pass through. Further, as the clock signal that determines the processing timing of the RDS signal extracted by the BPF 101, the master clock that is synchronized with the subcarrier frequency or the symbol rate is used. Therefore, as part of a digital signal processing system that performs reception processing for receiving FM audio broadcasting, digital audio signal processing for audio reproduction, etc.
There are two major problems with incorporating a decoder, as shown below.

The first problem relates to the BPF 101 which is a subcarrier extracting filter. The BPF 101 has the following functional requirements. It is necessary to have the pass band at the sub-carrier frequency which is a relatively high frequency. It is necessary to narrow the pass band even though the sub-carrier frequency is a relatively high frequency. It is necessary to sufficiently increase the amount of attenuation outside the pass band. Therefore, it is necessary to use a filter having a high sampling frequency and a large order for the BPF 101, and there is a problem that the number of processing steps increases.

The second problem relates to the sampling frequency of the decoding process. In the decoding process of the RDS signal, it is desired to process the data in synchronization with the timing of the transmission symbol. However, when the basic clock is determined by prioritizing other processing such as radio signal processing and digital audio signal processing, it is generally impossible to generate a sampling frequency that synchronizes with a transmission symbol from a simple integer ratio of the basic clock frequency. . In other words, there is a problem that adjusting the basic clock frequency so as to be synchronized with the frequency of the RDS transmission symbol is difficult in the operation of other systems.

Therefore, the present invention has been made in order to solve the above-mentioned problems of the prior art, and an object thereof is to reduce the number of man-hours for processing for extracting an RDS signal from an FM composite audio signal. It is to provide an RDS decoder capable.

Another object of the present invention is to eliminate the restriction that the clock (time reference) for RDS signal processing must be synchronized with the RDS symbol frequency, and to perform digital signal processing for main audio signal processing of FM broadcasting. It is to provide an RDS decoder that can be easily integrated into a system.

[0014]

An RDS decoder according to claim 1 is an RD based on digital data in an FM audio signal.
Synchronous demodulation means for inputting a multiplexed signal obtained by multiplexing S signals and generating a baseband RDS signal from the RDS signal, and baseband RDS generated by the synchronous demodulation means
A data decoding means for restoring the digital data from a signal, wherein the synchronous demodulation means converts the multiplexed signal into two baseband signals whose phases are orthogonal to each other, and an orthogonal demodulation means from the two baseband signals. A filter means for removing unnecessary components having a frequency higher than a predetermined frequency and thinning out sampled data, and detecting and correcting a phase error remaining in the two baseband signals output from the filter means, Phase synchronization means for generating the baseband RDS signal input to the decoding means.

An RDS decoder according to claim 2 is
The data decoding means receives the baseband RDS signal generated by the synchronous demodulation means, and the sampling frequency conversion means configured to adjust the conversion ratio appropriately, and the data output from the sampling frequency conversion processing unit. And a symbol phase error detection means for detecting a phase error between the transmission symbol timing and the transmission symbol timing, wherein the sampling frequency conversion means, based on the phase error detected by the symbol phase error detection means, It is characterized by adjusting the conversion ratio.

The RDS decoder according to claim 3 is
The quadrature demodulating means has a first input section and a second input section, and outputs a multiplication result of a signal input to the first input section and a signal input to the second input section. It has one multiplication processing section, a third input section and a fourth input section, and outputs a multiplication result of the signal input to the third input section and the signal input to the fourth input section. A second multiplication processing unit,
And a numerical control oscillator that outputs two signals that are 90 ° out of phase with each other, and the numerical control oscillator outputs the two signals to both the first input section of the first multiplication processing section and the third input section of the second multiplication processing section. The multiplexed signal is input, and the second input unit of the first multiplication processing unit and the fourth input unit of the second multiplication processing unit are provided with 90 ° phase difference from each other output from the numerical control oscillator. Each of the two different signals is input, and the output signal from the first multiplication processing unit and the output signal from the second multiplication processing unit are applied to the filter means.

The RDS decoder according to claim 4 is
The filter means includes a first low-pass filter to which an output signal from the first multiplication processing unit is input, and a second low-pass filter to which an output signal from the second multiplication processing unit is input. And a filter.

An RDS decoder according to claim 5 is
The phase synchronization means, the output signal from the first low-pass filter and the output signal from the second low-pass filter is input, the phase-rotated first signal and the second signal. A phase rotation processing unit for outputting, a third multiplication processing unit to which the first signal and the second signal are input, and which outputs a multiplication result of the first signal and the second signal, and the third A loop filter that controls the phase rotation angle in the phase rotation processing unit so that the output result of the multiplication processing unit converges to 0, and outputs the first signal output from the phase rotation processing unit to the baseband. It is characterized in that it is given to the data decoding means as an RDS signal.

Further, the RDS decoder according to claim 6 is
A multiplex signal obtained by multiplexing an RDS signal based on digital data on an FM voice signal is input, and a synchronous demodulation means for generating a baseband RDS signal from the RDS signal, and a baseband RDS signal generated by the synchronous demodulation means And a data decoding means for restoring digital data,
The data decoding means receives the baseband RDS signal generated by the synchronous demodulation means, and the sampling frequency conversion means configured to adjust the conversion ratio appropriately, and the data output from the sampling frequency conversion processing unit. And a symbol phase error detection means for detecting a phase error between the transmission symbol timing and the transmission symbol timing, wherein the sampling frequency conversion means, based on the phase error detected by the symbol phase error detection means, It is characterized by adjusting the conversion ratio.

The RDS decoder according to claim 7 is
The data decoding means adjusts the transmission symbol timing so that the zero-cross point of the transmission symbol output from the sampling frequency conversion processing unit is located at the center of the symbol period.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION In RDS broadcasting, an RDS signal based on digital data is superimposed on an FM audio signal and transmitted. An RDS radio receiver is used to receive the RDS broadcast. The RDS decoder according to the present invention is usually
Equipped as part of S radio receiver.

<Description of Configuration of RDS Decoder> FIG.
It is a block diagram which shows the structure of the RDS decoder which concerns on embodiment of this invention. As shown in FIG. 1, the RDS decoder according to the present embodiment is an FM obtained by detecting an FM broadcast signal in which an RDS signal is superimposed on an FM audio signal and transmitted.
It has a synchronous demodulation means 1 for receiving a composite voice signal and outputting a baseband RDS signal. Further, the RDS decoder according to the present embodiment has a data decoding means 2 which receives the baseband RDS signal from the synchronous demodulation means 1 and outputs the same RDS data as the transmission digital data.

The synchronous demodulation means 1 has a quadrature demodulation means 3, a filter means 4 and a phase synchronization means 5. The quadrature demodulation means 3 includes a first multiplication processing unit 11, a second multiplication processing unit 12, a numerical oscillator (numerical control oscillator:
numerically controlled oscillator) 13. The filter means 4 is an I-branch filter (LPF).
14 and a Q branch filter (LPF) 15. The phase synchronization means 5 has a phase rotation processing unit 16, a third multiplication processing unit 17, and a loop filter 18.

The data decoding means 2 includes a sampling frequency conversion means 6, a symbol phase error detection means 7, an integrated and dump (I & D) processing section 26, a binarization processing section 27, and a differential decoding processing section. 28 and a clock (CL that generates a clock signal based on the symbol clock).
K) The generation processing unit 29. The sampling frequency conversion means 6 includes a sampling frequency conversion processing unit 19, an increment setting processing unit 23, a timing counting processing unit 24, and a filter coefficient setting processing unit 25. The symbol phase error detecting means 7 has a sample number counting processing section 20, a zero-cross (ZC) detection processing section 21, and a timing error accumulation processing section 22.

Each of the above configurations can be configured by hardware having the functions described below, software, or a combination thereof.

<Description of Function of Synchronous Demodulation Unit 1> The input signal of the synchronous demodulation unit 1 is a composite voice signal after FM detection. The sampling frequency of this input signal is approximately 57k.
Aliasing distortion to the RDS signal band with a component of ± 2.4 kHz (aliasing)
It is necessary to set the frequency to about 120 kHz or more (that is, twice or more of 57 kHz ± 2.4 kHz), which is a frequency that can suppress the influence of the above. This can be given directly by digital detection, or an analog composite audio signal can be given digitally (Analog to
Digital) can be converted and given.

The composite audio signal thus input is first converted by the orthogonal demodulation means 3 into two orthogonal baseband signals. The quadrature demodulation means 3 includes the first multiplication processing unit 1.
1, a second multiplication processing unit 12, and a numerical oscillator 13. The numerical oscillator 13 has a frequency substantially equal to the sub-carrier frequency of 57 kHz, and supplies two signals having mutually different 90 ° phases to one input section of the first and second multiplication processing sections 11 and 12. A composite audio signal is given to the other input section of the first and second multiplication processing sections 11 and 12. Therefore, at the output of each of the multipliers 11 and 12, a signal in which the sub-carrier frequency is converted to a substantially zero frequency appears. In addition, the components outside the RDS signal band are converted to higher frequencies. The quadrature demodulation means 3
The two orthogonal baseband signals obtained in this way are given to the filter means 4.

The filter means 4 has both a filter function for removing unnecessary signals and a thinning function for thinning the sample data to reduce the sampling frequency while suppressing the adverse effects of aliasing distortion. The filter means 4 has an I-branch filter 14 and a Q-branch filter 15, which are filters having two equivalent characteristics corresponding to the two orthogonal baseband signals output from the orthogonal demodulation means 3.
At this time, the components of the two signal outputs of the I branch filter 14 and the Q branch filter 15 are approximately 0 to 2.4k.
It will be output after being converted to the Hz band. Therefore, the sampling frequency at this stage should be approximately 5k.
It is possible to reduce the frequency to about Hz or more (that is, twice or more of 2.4 kHz). Therefore, in the I-branch filter 14 and the Q-branch filter 15, a large amount of data can be thinned out, and the filter format is FIR.
When using a (finite impulse response) type, the number of processing steps can be significantly reduced.

For comparison, 57 kHz ± 1.2 kHz
Consider a filter that has almost no attenuation at 40 dB and an attenuation outside the band of 57 kHz ± 3 kHz of 40 dB. In this case, set the sampling frequency to 128 kHz and
It is necessary to process about 43 coefficients. When this is counted as the number of product-sum operations required per second, it is about 18.
It becomes 3 × 10 ⁶ . Therefore, if the same processing is performed for a baseband signal (57 kHz) with a filter having the same characteristics, the required filter coefficient is 14
It becomes 3. On the other hand, like the RDS decoder according to the present embodiment, the output of the filter means 4 is 0 to 2.4 kH.
When converted to the z band, for example, the sampling frequency is lowered to 8 kHz (an example of a frequency of about 5 kHz or higher), and the number of data is 1/16 (= 8 kHz / 128 kHz).
z) can be reduced (that is, thinning-out). Therefore, in the case of the RDS decoder according to the present embodiment, the actual filtering process is performed with the frequency 1/1 against the input
It suffices to perform only for the output that becomes 6. Therefore, the processing man-hour (the number of product-sum operations) is 1/16 as compared with the case where each of the two branch filters 14 and 15 is subjected to the filter processing in the 57 kHz band. Therefore, even if the two branch filters 14 and 15 are combined, the processing man-hour is reduced to ⅛ (= 2 × 1/16).

Further, the I-branch filter 14 and the Q-branch filter 15 are provided with a low-pass characteristic for attenuating and removing unnecessary components, and a roll off rate of 0.5 for waveform shaping is provided. It is possible to improve the decoding processing performance by giving an approximated raised cosine characteristic. This is a filter (reference numerals 101 and 1 in FIG. 7) applied to a signal after synchronous detection in a conventional RDS decoder.
This means that the processing of 04) is simultaneously performed at this stage, and it is possible to reduce the number of constituent elements and the total processing man-hour.

By the way, in the same area as the RDS broadcast, an ARI (Auto
fahrer Rundfunk Information: Radio broadcasting information for car drivers) Broadcasting may be carried out with a traffic information service called broadcasting. This ARI is transmitted with a sub-carrier frequency and a spectrum very close thereto.
Since the RDS broadcast and the ARI broadcast may be simultaneously performed in the same area, it is necessary to prevent the decoding operation of the RDS decoder from being adversely affected by the ARI broadcast.
According to the RDS decoder of this embodiment, the I branch filter 14 and the Q branch filter 15 have ARI
This can be easily achieved by adding a high-pass characteristic that blocks the spectrum of the transmission signal. Actually, the spectrum of the ARI transmission signal is almost 250 Hz.
There is a difference that the spectrum of the RDS signal is distributed around 1.2 kHz, while the spectrum is distributed in the following frequency bands. Therefore, when it is necessary to prevent the RDS decoder from being adversely affected by the ARI broadcasting, it is possible to effectively achieve this object by adding a filter that attenuates only the component of approximately 250 Hz or less.

At the output of the filter means 4, an RDS signal of almost zero frequency is obtained. However, in the RDS decoder according to the present embodiment, at the output stage of the filter means 4, the phase of the input RDS signal carrier and the output of the numerical oscillator 13 are not synchronized, so that the baseband RDS signal is correctly obtained. I can't do that. For this reason, the phase synchronization means 5 adjusts the phase and takes out the baseband RDS signal. The operation will be described below using mathematical expressions.

First, the two signals R _c and R _s that enter the phase synchronization means 5 are _defined as R _c = R (t) cos (φ) R _s = R (t) sin (φ). Here, R (t) is the baseband RDS signal, and φ represents the phase error at that time. The phase rotation processing unit 16 performs an operation represented by the following equation on the two signals R _c and R _s to generate signals R _co and R _so . R _co = R _c · cos (ψ) −R _s · sin (ψ) = R
(T) · cos (φ + φ) R _so = R _c · sin (φ) + R _s · cos (φ) = R
(T) · sin (φ + φ) Here, feedback control is performed through the loop filter 18 so that φ becomes substantially equal to −φ, so that the R _co output eventually becomes approximately equal to the baseband RDS signal R (t). , R _so approaches 0.

The third multiplication processor 17 receives the signal R_coAnd R
_soBy multiplying {R (t)}^Two・ Sin (2
φ + 2ψ) / 2 is obtained as the output. This output is R
Regardless of whether (t) is positive or negative, (φ + ψ) is ± 45 °
In a sufficiently small range, it is almost proportional to the size of (φ + ψ)
Give output. Therefore, the output of the third multiplication processing unit 17
{R (t)}^Two・ Converging sin (2φ + 2ψ) / 2 to 0
The feedback control by setting the value of ψ.
Then, as described above, the output R of the phase rotation processing unit 16
_coAs the baseband RDS signal R (t)
It can be given to the decoding unit 2.

It should be noted that the feedback control may be performed on the numerical oscillator 13 to omit the phase rotation processing unit 16, but in reality, the feedback is performed due to the influence of delay in the filter means 4. Loop operation tends to be unstable. Therefore, the configuration of the present embodiment has a great advantage that stable operation can be achieved.

<Explanation of Function of Data Decoding Means 2> When the processing for decoding the baseband RDS signal is performed by the conventional integration and dump processing by the analog circuit (processing by the configurations 105 to 109 in FIG. 7), The sampling frequency of the processed data may be an even multiple of the symbol frequency of the RDS signal, the sample data in the first half of the symbol period may be cumulatively added as it is, and the sign of the sample data in the latter half of the symbol period may be inverted to further perform cumulative addition. it can. For example, FIG. 4 (b) and FIG.
(B) shows the case where the sampling frequency is 6 times the symbol frequency. In this way, by synchronizing the sampling frequency with the symbol frequency, the data decoding process can be easily realized.

However, the RDS according to the present embodiment
In the decoder, the data given as the output of the phase synchronization means 5 is not synchronized with the symbol frequency. The sampling frequency conversion processing unit 19 generates data of a sample frequency that is synchronized with the symbol frequency from data of a sample frequency that is not synchronized with the symbol frequency. Specifically, as shown in FIG. 2, the sampling frequency conversion processing unit 19 compares the original data (input data “◯” in FIG. 2) with N pieces of data (in FIG. 2) that interpolate between the data. The virtual output data “×”) is configured to be generated, and the data that is closest to the desired timing at the virtual output data is selected and output.

The actual processing in the sampling frequency conversion processing section 19 uses, for example, a K times oversampling filter. The K-fold oversampling filter consists of a subset of K sets of L coefficients based on a filter of K × L coefficients at a sampling frequency K times the input sampling frequency. In other words, by convolving one of the K coefficient sets with the L data, new data located at an intermediate timing of the original data is generated and output.

The filter coefficient setting processing section 25 instructs the sampling frequency conversion processing section 19 to select this filter coefficient set, and determines the timing of the data generated thereby.

The timing counting processing section 24 gives a data generation instruction to the sampling frequency conversion processing section 19, and at the same time controls the timing of the data generated via the filter coefficient setting processing section 25.

FIG. 3 is an explanatory diagram for explaining the sampling frequency conversion processing in the data decoding means 2.
In FIG. 3, “count value” indicates the count value of the timing count processing unit 24. Further, in FIG. 3, “input data timing” is the sampling frequency conversion processing unit 1
9 shows the timing at which data is input, and “output data timing” is the sampling frequency conversion processing unit 19
Indicates the timing at which data is output from.

As shown in FIG. 3, the timing counting processing unit 24 sets the count value of the built-in counter to a numerical value N each time data is input to the sampling frequency conversion processing unit 19.
Perform processing to add. When the count value exceeds the numerical value M, the timing count processing unit 24 gives an instruction for data generation to the sampling frequency conversion processing unit 19. At the same time, the timing count processing unit 24 subtracts the numerical value M from the count value of the built-in counter (see FIG.
(M1, M2) is used as the count value of the counter, and this value is given to the filter coefficient setting processing unit 25 to control the timing of the data generated by the sampling frequency conversion processing unit 19.

At this time, the values M1 and M2 shown in FIG.
Is a value in the range of 1 to N. The filter coefficient setting processing unit 25 sets the filter coefficient so as to generate data with advanced timing in inverse proportion to this value. Therefore, the data output from the sampling frequency conversion processing unit 19 has timings at substantially equal intervals corresponding to the numerical value M, as shown in FIG.

Here, the sample number counting processing unit 20 gives the sample number repeated in the symbol period to the data output from the sampling frequency conversion processing unit 19, and actually the data generation from the timing counting processing unit 24 is performed. By incrementing P (P = 6 in this embodiment) by 1 (ie, 0, 0,
1, 2, 3, 4, 5). According to the detection of the symbol timing by the zero-cross detection processing unit 21, initialization is performed so that the number immediately after the occurrence of the zero-cross at the symbol center is P / 2.

As shown in FIGS. 4 and 5, the timing error accumulation processing section 22 cumulatively adds the data values in the central part of the symbol period. In the example of FIGS. 4 and 5, among the data with sample numbers 0 to 5 synchronized with the symbols, the values of the data corresponding to the sample numbers 1 to 4 are cumulatively added. For the result, the integration and
The output (= D _t ) of the dump processing unit 20 is multiplied by the sign to obtain the final output T _e . This can be expressed as a mathematical expression as follows. T _e = (s ₁ + s ₂ + s ₃ + s ₄ ) · sign (D _t ) D _t = s ₀ + s ₁ + s ₂ − (s ₃ + s ₄ + s ₅ ), where s ₀ to s ₅ are samples, respectively. Number 0
Is the value of the data corresponding to 5 to 5
_t) is a function that takes a "1" or "-1" depending on the sign of the output _{D t.}

As shown in FIGS. 4A and 5A, when the output sample timing is delayed from the symbol timing, T _e becomes negative. Further, as shown in FIGS. 4C and 5C, when the output sample timing is ahead of the symbol timing, T _e
Is positive. Furthermore, as shown in FIGS. 4B and 5B, when the output sample timing coincides with the symbol timing, T _e becomes almost 0. From this, it can be seen that the output T _{e of} the timing error accumulation processing unit 22 is effective as a signal representing the timing error.

The increment setting processing section 23 receives the output of the timing error accumulation processing section 22 and controls the operation of the timing counting processing section 24. The increment setting processing unit 23 normally sets the timing counting processing unit 24 so as to increase the count value of the built-in counter by a numerical value N, but temporarily when there is a timing error in the advance direction, The increment of the count value of the built-in counter is set to be larger than the numerical value N. Conversely, if there is a timing error in the delay direction,
The increment of the count value of the built-in counter is temporarily set to be smaller than the numerical value N. By changing the increment of the built-in counter in this way, the output sample timing operates so as to reduce the error from the symbol timing.

Therefore, once this initial setting is correctly performed, the sampling frequency conversion processing section 19 acts to reduce the output of the filter coefficient setting processing section 25 by feedback control. The synchronous relationship with will be maintained.

The zero-cross detection processing section 21 synchronizes the sample number output from the sample number counting processing section 20 with the RDS symbol by utilizing the characteristic that the zero-cross always exists in the center of the RDS symbol. actually,
The zero-cross detection processing unit 21 first monitors the output of the sampling frequency conversion processing unit 19 and detects and holds a change in the sign of the previous data and the current data. The zero-cross detection processing unit 21 checks this until the final data of the symbol,
Sign change, that is, the sample number immediately after zero crossing is P
If it is / 2, it is determined that the synchronization with the symbol is correctly maintained, and if not, it is determined that the synchronization is lost. The zero-cross detection processing unit 21 further determines the frequency of the out-of-synchronization, and if the frequency is larger than a predetermined value, the sample number update processing of aligning the sample number immediately after the zero-cross that has recently been observed to P / 2. I do.

By this update processing, when the recently observed zero cross is located at the center of the symbol period, the synchronization relationship between the symbol timing and the sample number will be established. Further, even if the observed zero-cross is located at the symbol boundary, if the sample number is updated in this way, as shown in the column of “erroneous sequence of sample number” in FIG. Since the case where the code does not change frequently occurs at / 2 and the sample number is updated again, the synchronization relationship between the symbol timing and the sample number will be established soon.

Integrated and dump processing unit 2
6 cumulatively adds the sample data in the first half of the symbol period to the sample data synchronized with the symbol timing as it is, inverts the sign of the sample data in the latter half of the symbol period, and further performs cumulative addition. The integration and dump processing unit 26 outputs the result when the accumulation of one symbol is completed.

The binarization processing unit 27 follows the sign of the output from the integrate and dump processing unit 26.
Binary data of "1" or "0" is output.

The differential decoding processing unit 28 takes the exclusive OR of the input corresponding to the previous symbol and the current input, reproduces the RDS data, and outputs it.

According to the RDS decoder of this embodiment, by reducing the man-hours of the RDS decoder process and relaxing the requirements for the basic clock of the process, the RDS decoder of the signal processing system including the FM radio reception process can be incorporated. This can be realized easily and the device manufacturing cost can be reduced.

[0055]

As described above, according to the RDS decoder of the first to fifth aspects of the present invention, the man-hour of the filtering process for extracting the RDS signal from the FM composite audio signal can be reduced and the baseband RDS signal can be obtained. There is an effect that the operation of the phase synchronization means for obtaining a signal can be stabilized.

The RD according to the inventions of claims 2, 6 and 7
According to the S decoder, the signal processing clock (time reference)
With respect to the above, there is an effect that it is possible to easily integrate the device into a digital signal processing device or the like that performs the main audio signal processing of FM broadcasting, by eliminating the restriction that is conventionally imposed on synchronizing with the RDS symbol frequency. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an RDS decoder according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining sampling frequency conversion processing in the data decoding means of the RDS decoder according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram for explaining sampling frequency conversion processing in the data decoding means of the RDS decoder according to the embodiment of the present invention.

4A to 4C are explanatory diagrams for explaining a sampling frequency conversion process of the RDS decoder according to the embodiment of the present invention.

5A to 5C are explanatory diagrams for explaining a sampling frequency conversion process of the RDS decoder according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining a zero-cross detection process of the RDS decoder according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional RDS decoder.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 synchronous demodulation means, 2 data decoding means, 3 orthogonal demodulation means, 4 filter means, 5 phase synchronization means,
6 sampling frequency conversion means, 7 symbol phase error detection means, 11 first multiplication processing section, 12
Second multiplication processing unit, 13 numerical oscillator,
14 I branch filter (LPF), 15 Q branch filter (LPF), 16 phase rotation processing unit, 1
7 Third multiplication processing unit, 18 loop filter, 1
9 sampling frequency (fs) conversion processing unit, 20
Sample number counting processor, 21 zero cross (ZC)
Detection processing unit, 22 Timing error accumulation processing unit, 2
3 increment setting processing unit, 24 timing counting processing unit,
25 filter coefficient setting processing unit, 26 integrated and dump (I & D) processing unit, 27 binarization processing unit, 28 differential decoding processing unit, 29 clock (C
LK) generation processing unit, 101 BPF, 102 multiplier, 103 subcarrier reproducing means, 104 LP
F, 105 inverting amplifier, 106 symbol clock recovery means, 107 switch, 108 switch,
109 integrator, 110 slicer, 111 flip-flop circuit, 112 flip-flop circuit,
113 exclusive OR circuit (XOR), 114 differential decoder.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masayuki Tsuji             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Masayuki Ishida             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F term (reference) 5K061 AA11 BB04 CC00 FF12 JJ24

Claims (7)

[Claims] 1. A multiplexed signal obtained by multiplexing an RDS signal based on digital data with an FM voice signal is input, and the RD
Synchronous demodulation means for generating a baseband RDS signal from the S signal, and data decoding means for restoring the digital data from the baseband RDS signal generated by the synchronous demodulation means, wherein the synchronous demodulation means comprises: Quadrature demodulation means for converting the signal into two baseband signals whose phases are orthogonal to each other, a filter means for removing unnecessary components having a frequency higher than a predetermined frequency from the two baseband signals, and thinning out sample data, Phase synchronization means for detecting and correcting a phase error remaining in the two baseband signals output from the filter means and generating the baseband RDS signal input to the data decoding means. RDS decoder to do. 2. The sampling frequency conversion means configured so that the data decoding means receives the baseband RDS signal generated by the synchronous demodulation means and can appropriately adjust the conversion ratio, and the sampling frequency conversion processing part. A symbol phase error detecting means for detecting a phase error between the data output from and the transmission symbol timing, the sampling frequency converting means, based on the phase error detected by the symbol phase error detecting means, The RDS decoder according to claim 1, wherein the conversion ratio of the sampling frequency conversion means is adjusted. 3. The quadrature demodulating means has a first input section and a second input section, and multiplies a signal input to the first input section and a signal input to the second input section. A first multiplication processing unit that outputs a result; and a third input unit and a fourth input unit, which include a signal input to the third input unit and a signal input to the fourth input unit. A second multiplication processing unit that outputs a multiplication result, and a numerical control oscillator that outputs two signals that are 90 ° out of phase with each other, the first input unit of the first multiplication processing unit and the second The multiplex signal is input to both of the third input unit of the multiplication processing unit, to the second input unit of the first multiplication processing unit and the fourth input unit of the second multiplication processing unit, respectively, Each of two signals output from the numerically controlled oscillator and having a phase difference of 90 ° from each other is input, RD according to claim 1 or 2, characterized in that providing an output signal and an output signal from the second multiplication processing section from one multiplication unit to said filter means
S decoder. 4. A first low-pass filter to which the output signal from the first multiplication processing unit is input, and a second low-pass filter to which the output signal from the second multiplication processing unit is input. The RDS decoder according to claim 3, further comprising two low pass filters. 5. The phase synchronization means receives the output signal from the first low pass filter and the output signal from the second low pass filter, and rotates the phase of the first signal and A phase rotation processing unit which outputs a second signal, and a third multiplication processing unit which receives the first signal and the second signal and outputs a multiplication result of the first signal and the second signal A loop filter that controls the phase rotation angle in the phase rotation processing unit so that the output result of the third multiplication processing unit converges to 0, and the first filter output from the phase rotation processing unit 5. The RDS decoder according to claim 4, wherein said signal is applied to said data decoding means as said baseband RDS signal. 6. A multiplexed signal obtained by multiplexing an RDS signal based on digital data with an FM voice signal is input, and the RD is provided.
Synchronous demodulation means for generating a baseband RDS signal from the S signal, and data decoding means for restoring the digital data from the baseband RDS signal generated by the synchronous demodulation means, wherein the data decoding means comprises: A baseband RDS signal generated by the demodulation means is input, and a sampling frequency conversion means configured to appropriately adjust the conversion ratio, and a phase error between the data output from the sampling frequency conversion processing unit and the transmission symbol timing. And a symbol phase error detecting means for detecting, wherein the sampling frequency converting means adjusts the conversion ratio of the sampling frequency converting means based on the phase error detected by the symbol phase error detecting means. RDS decoder. 7. The data decoding means adjusts the transmission symbol timing so that the zero-cross point of the transmission symbol output from the sampling frequency conversion processing unit is located at the center of the symbol period.
Or the RDS decoder according to any one of 6).