GB2383481A

GB2383481A - RDS Decoder

Info

Publication number: GB2383481A
Application number: GB0228781A
Authority: GB
Inventors: Kenichi Taura; Masahiro Tsujishita; Masayuki Tsuji; Masayuki Ishida
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2001-12-17
Filing date: 2002-12-10
Publication date: 2003-06-25
Anticipated expiration: 2022-12-10
Also published as: JP2003188748A; DE10260403A1; DE10260403B4; JP3865628B2; GB2383481B; GB0228781D0

Abstract

An RDS decoder includes a synchronous demodulator 1 and a data decoder 2. The synchronous demodulator 1 receives a multiplex signal in which an RDS signal based on digital data is superimposed on an FM audio signal and generates a baseband RDS signal from the RDS signal. The data decoder 2 decodes the baseband RDS signal generated by the synchronous demodulator 1 into the digital data. The synchronous demodulator 1 includes a quadrature demodulator 3 which converts the multiplex signal into two baseband signals which differ in phase by 90 degrees, a filter 4 which removes unwanted components having frequencies higher than a predetermined frequency level from the two baseband signals to reduce sample data, and a phase-locked loop 5 which receives the two baseband signals output from the filter and generates the baseband RDS signal to be input to the data decoder from the two baseband signals. The phase-locked loop detects and corrects phase error remaining in the baseband RDS signal.

Description

RDS DECODER BACKGROUND OF THE INVENTION The present invention relates to an RDS decoder for use in the Radio Data System (RDS) in which an RDS signal based on digital data is superimposed on an FM audio signal.

The RDS broadcasting adopts a transmission method (i. e., multiplex transmission) in which an FM audio signal having a pilot frequency of 19 kHz accompanied with an RDS signal modulated into a frequency band of 57 kHz, triple of the pilot frequency, is transmitted. The RDS signal to be transmitted is generated by subj ecting differentially encodedbinary time-series data to binary phase-shift keying (BPSK) and carrying out double-sideband modulation of the 57 kHz subcarrier using the BPSK signal. An RDS radio receiver is used to catch RDS broadcasts. The RDS radio receiver includes a circuit for receiving the FM broadcast signal (i. e. , FM tuner), a digital audio signal processing circuit for audio reproduction, and an RDS decoder for demodulating and decoding the RDS signals. Figs. 7A and 7B show the configuration and waveforms of a conventional RDS decoder disclosed in the Japanese Patent No. 2,593, 079 publication.

In the RDS decoder shown in Fig. 7A, the band-pass filter (BPF) 101 passes just RDS signals in the 57 kHz band, out of the FM composite audio signal obtained by detecting the FM broadcast signal. The subcarrier regenerator 103 synchronously detects a

double-sideband modulated RDS signal without carrier and supplies a reproduced carrier signal having the same phase and frequency as the RDS subcarrier to the multiplier 102. The subcarrier regenerator 103 is configured as a Costas-loop-type phase-locked loop, for instance.

The output of the multiplier 102 contains the baseband RDS signal and an unwanted 114 kHz signal component. The low-pass filter (LPF) 104 removes the unwanted signal component and outputs the baseband RDS signal. The LPF 104 also has a function to improve the performance of the RDS decoder by eliminating noise and passing just the spectrum needed for decoding.

The symbol clock regenerator (i. e. , bit-rate symbol regenerator) 106 detects a break between BPSK symbols from the baseband RDS signal output by the LPF 104. The symbol clock regenerator 106 determines the symbol clock cycle (symbol rate: 1187.5 Hz) utilizing the fact that the symbol clock period is forty-eighth times as long as the period of the 57 kHz subcarrier, and determines the phase of the BPSK signal utilizing the fact that the BPSK signal always has a zero-cross point in the middle of the waveform.

The inverting amplifier 105 has a gain ouf"1". The switch 107 is controlled in accordance with the symbol clock (a waveform SC shown in Fig. 7B) supplied from the symbol clock regenerator 106. The switch 107 supplies the integrator 109 with the baseband RDS signal (a waveform Ri shown in Fig. 7B) during the first half

of each symbol clock cycle (i. e., symbol period) and with the output from the inverting amplifier 105 (a waveform R2 shown in Fig. 7B) during the second half of each symbol period. Accordingly, if the phase of the BPSK signal is 0 degree, a positive potential is applied to the integrator 109 over the whole symbol period, and if the phase of the BPSK signal is 180 degrees, a negative potential is applied to the integrator 109 over the whole symbol period, for instance.

At the end of the symbol period, the slicer 110 determines whether the result of integration by the integrator 109 (a waveform R3 shown in Fig. 7B) is positive or negative, then the result is decoded to binary data. This processing performed in synchronization with the symbol period is referred to as integrate-and-dump processing. The switch 108 temporarily closes at the beginning of the symbol period to initialize the integrator 109.

The flip-flop circuit 111 captures the output of the slicer 110 at the end of the symbol period (or at the beginning of the next symbol) and keeps outputting the same value during the next symbol period. The flip-flop circuit 112 holds the output of the previous flip-flop circuit 111 with a delay of one symbol period. Then, the exclusive OR circuit (XOR) 113 carries out differential decoding by outputting a value of true (i. e. , a logical value" 1") if chronologically adjacent data carried by the BPSK symbols are different or outputting a value of false (i. e. , a logical value

"O") if the chronologically adjacent data are the same.

As has been described above, the conventional RDS decoder is configured as a specialized decoder. As a first step, the BPF 101 which passes signals in the subcarrier band extracts RDS signals from the FM composite audio signal. The master clock synchronized with the subcarrier frequency or symbol rate is used as the clock signal for determining the processing timing of the RDS signal extracted by the BPF 101. Therefore, if the RDS decoder is incorporated as a part of a digital signal processing system which carries out processing for catching FM audio broadcasts, digital audio signal processing for audio reproduction, and the like, two big problems as described below arise.

A first problem relates to the BPF 101 which functions as a subcarrier filter. Functional requirements for the BPF 101 include the following.

< i > The passband must be in a relatively high subcarrier frequency band.

< ii > Although the subcarrier frequencies are relatively high, the passband must be narrow.

< iii > The attenuation beyond the passband must be sufficiently great.

Therefore, the BPF 101 must be a filter having a high sampling frequency and a high filter order, which will result in many processing steps.

A second problem relates to the sampling frequency of decoding.

In RDS signal decoding, it is desired that data processing is carried out in accordance with the transmission symbol. However, if the reference clock is determined in accordance with the other processing such as radio signal processing and digital audio signal processing, the sampling frequency derived from a simple integral ratio of the reference clock frequency cannot agree with the frequency of symbol transmission. In other words, it is difficult to adjust the reference clock frequency to the frequency of RDS symbol transmission, due to the operation of the other system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an RDS decoder that can reduce the number of processing steps required to extract an RDS signal from the FM composite audio signal.

It is another object of the present invention to provide an RDS decoder which can eliminate a condition that the clock (reference timing) of RDS signal processing must be synchronized with the RDS symbol frequency and can facilitate its integration into a digital signal processing system that per forms the main audio signal processing concerning FM broadcasts.

According to one aspect of the present invention, an RDS decoder includes a synchronous demodulator which receives a multiplex signal in which an RDS signal based on digital data is superimposed on an FM audio signal and generates a baseband RDS signal from the RDS signal, and a data decoder which decodes the

baseband RDS signal generated by the synchronous demodulator into the digital data. The synchronous demodulator includes a quadrature demodulator which converts the multiplex signal into two baseband signals which differ in phase by 90 degrees, a filter which removes unwanted components having frequencies higher than a predetermined frequency level from the two baseband signals to reduce sample data, and a phase-locked loop which receives the two baseband signals output from the filter and generates the baseband RDS signal to be input to the data decoder from the two baseband signals, the phase-locked loop detecting and correcting phase error remaining in the baseband RDS signal.

According to another aspect of the present invention, an RDS decoder includes a synchronous demodulator which receives a multiplex signal in which an RDS signal based on digital data is superimposed on an FM audio signal and generates a baseband RDS signal from the RDS signal, and a data decoder which decodes the baseband RDS signal generated by the synchronous demodulator into the digital data. The data decoder includes a sampling frequency converter which receives the baseband RDS signal generated by the synchronous demodulator and performs conversion of a frequency of the baseband RDS signal, the sampling frequency converter being capable of adjusting a rate of the conversion, and a symbol phase error detector which detects a phase error of data output from the sampling frequency converter as compared with a transmission symbol. The sampling frequency converter adjusts the rate of the

conversion in accordance with the phase error detected by the symbol phase error detector.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: Fig. 1 is a block diagram showing the configuration of an RDS decoder in accordance with an embodiment of the present invention; Fig. 2 is an explanatory diagram for explaining sampling frequency conversion by a data decoder of the RDS decoder in accordance with the embodiment of the present invention; Fig. 3 is an explanatory diagram for explaining the sampling frequency conversion by the data decoder of the RDS decoder in accordance with the embodiment of the present invention; Figs. 4A to 4C are explanatory diagrams for explaining the sampling frequency conversion by the data decoder of the RDS decoder in accordance with the embodiment of the present invention; Figs. 5A to 5C are explanatory diagrams for explaining the sampling frequency conversion by the data decoder of the RDS decoder in accordance with the embodiment of the present invention; Fig. 6 is an explanatory diagram for explaining zero-cross

detection by the RDS decoder in accordance with the embodiment of the present invention; and Figs. 7A and 7B are a block diagram and a waveform diagram of the conventional RDS decoder respectively.

DETAILED DESCRIPTION OF THE INVENTION Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter.

However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications will become apparent to those skilled in the art from the detailed description.

In RDS broadcasting, an RDS signal based on digital data is superimposed on an FM audio signal. An RDS radio receiver is used to receive RDS broadcasts. The RDS decoder in accordance with the present invention is generally equipped as a part of the RDS radio receiver.

< Structure of RDS Decoder > Fig. 1 is a block diagram showing the configuration of an RDS decoder in accordance with an embodiment of the present invention.

As shown in Fig. 1, the RDS decoder in accordance with the embodiment

includes a synchronous demodulator 1, which receives an FM composite audio signal obtained by detecting a transmitted FM broadcast signal

in which an RDS signal is superimposed on an FM audio signal and outputs a baseband RDS signal. The RDS decoder in accordance with the embodiment further includes a data decoder 2, which receives the baseband RDS signal output from the synchronous demodulator 1 and outputs RDS data, the contents of which are the same as those of the transmitted digital data.

The synchronous demodulator 1 includes a quadrature demodulator 3, a filter 4, and a phase-locked loop (PLL) 5. The quadrature demodulator 3 includes a first multiplier 11, a second multiplier 12, and a numerically controlled oscillator 13. The filter 4 includes an I-branch filter (low pass filter (LPF)) 14 and a Q-branch filter (LPF) 15. The phase-locked loop 5 includes a phase rotator 16, a third multiplier 17, and a loop filter 18.

The data decoder 2 includes a sampling frequency converter 6, a symbol phase error detector 7, an integrate-and-dump (I & D) filter 26, a binarizer 27 which converts an input signal into a binary signal, a differential decoder 28, and a clock (CLK) generator 29 which generates a clock signal (RDS CLK) in accordance with the symbol clock. The sampling frequency converter 6 includes a frequency (fs) converter 19, an increment selector 23, a timing counter 24, and a filter coefficient selector 25. The symbol phase error detector 7 includes a sampling number counter 20, a zero-cross (ZC) detector 21, and a timing error accumulator 22.

Each component described above can be configured by a hardware having functions as described below, a software having functions

as described below, or their combination.

< Function of Synchronous Demodulator 1 > The signal input to the synchronous demodulator 1 is a composite audio signal after FM detection. The sampling frequency of the input signal should be set to a level with which the influence of aliasing distortion and the like in the RDS signal band of approximately 57 kHz : t 2. 4 kHz can be suppressed, that is, about 120 kHz (= 2x (57 kHz : t 2. 4 kHz) ) or higher. This frequency can be given directly by digital detection or through analog-to-digital conversion of a composite audio signal.

The input composite audio signal is first converted into two quadrature baseband signals by the quadrature demodulator 3. The quadrature demodulator 3 includes the first multiplier 11, the second multiplier 12, and the numerically controlled oscillator 13. The numerically controlled oscillator 13 supplies the input portions of the first multiplier 11 and of the second multiplier 12 with each of the two signals, which have a frequency approximately equal to the subcarrier frequency of 57 kHz and differ in phase by 90 degrees. The other input portions of the first multiplier 11 and of the second multiplier 12 are supplied with the composite audio signal. Therefore, both the multiplier 11 and multiplier 12 output a signal, the subcarrier frequency of which is changed to approximately zero. The components other than the RDS signal band are converted into higher frequencies. The quadrature

demodulator 3 gives these two quadrature baseband signals to the filter 4.

The filter 4 has both a filtering function to eliminate unwanted signals and a thinning function to reduce the sampling frequency by thinning the sample data while suppressing the influenceofaliasingdistortion. Thefilter4includesanI-branch filter 14 and a Q-branch filter 15, which have characteristics corresponding to the two quadrature baseband signals output from the quadrature demodulator 3. The I-branch filter 14 and Q-branch filter 15 output the two signals, converting the frequencies into the band ranging approximately from 0 kHz to 2.4 kHz. Therefore, the sampling frequency can be reduced to about 5 kHz or higher (more than twice as high as 2.4 kHz) at this stage. Accordingly, the I-branch filter 14 and Q-branch filter 15 can extensively thin data, and if the Finite Impulse-Response (FIR) filters are used, the number of required processes can be substantially reduced.

For the sake of comparison, suppose what would occur if a filter which hardly attenuates within the band of 57 kHz 1. 2 kHz and provides 40 dB attenuation outside the band of 57 kHz 3 kHz. In this case, if the sampling frequency is 128 kHz, the processing must be performed using a filter coefficient of"143" or around there. The corresponding number of product-sum operations required per second is about 18.3 x 106. If the same

processing is carried out by a filter having the same characteristics with respect to the baseband signal (57 kHz), the filter coefficient

of"143"will be required likewise. On the other hand, if the output of the filter 4 is converted into the band of 0 kHz to 2.4 kHz, as in the RDS decoder in accordance with the embodiment, the sampling frequency can be lowered to 8 kHz (as an example of the sample frequency above the level of about 5 kHz), and the number of data can be reduced (or thinned) to 1/16 (=8 kHz/128 kHz), for instance.

Therefore, in the RDS decoder in accordance with the embodiment, the actual filtering processing must be carried out just for the output, the frequency of which is one-sixteenth of the frequency of the input. Accordingly, the number of required processes (number of product-sum operations) is only one-sixteenth of the number of processes that would be needed if the I-branch filter 14 and Q-branch filter 15 separately carry out filtering in the 57 kHz band. Even if the numbers of processes by the I-branch filter 14 and Q-branch filter 15 are added, the reduction ratio in total number of processes is one eighth (= 2 x 1/16).

The decoding performance can be improved by giving the I-branch filter 14 and Q-branch filter 15 a low-pass property to attenuate or eliminate unwanted components and a property similar to the raised cosine characteristics with a roll-off ratio of 0.5 to shape waveforms. This means that the processing for the synchronously detected signals which has been performed by filters (i. e. , the filters 101 and 104 in Fig. 7A) in the conventional RDS decoder is carried out simultaneously at this stage, so that the number of components and the total number of processing steps

can be reduced.

In an RDS broadcast area, a different broadcast referred to as ARI (Autofahrer Rundfunk Information, i. e. , radio broadcast information for drivers) broadcast may also be carried out. The ARI broadcast adopts a different system from the RDS broadcast and provides a traffic information service. The ARI signals are transmitted with the subcarrier frequency and across the spectrum

very close to the subcarrier frequency. Because the RDS broadcast and ARI broadcast may be performed simultaneously in the same area, the decoding operation of the RDS decoder must be protected from the effect of the ARI broadcast. The protection can be easily implemented by the RDS decoder in accordance with the embodiment if the I-branch filter 14 and Q-branch filter 15 are given a high-pass property to reject the spectrum of the ARI transmission signal.

The spectrum of the ARI transmission signal generally extends in the frequency band not greater than 250 Hz while the center of the spectrum of the RDS signal is about 1.2 kHz. Therefore, if necessary, the RDS decoder can be efficiently protected from the influence of the ARI broadcast just by adding a fil ter for attenuating the components of up to about 250 Hz.

The filter 4 outputs the RDS signal of approximately zero frequency. The RDS decoder in accordance with the embodiment, however, cannot obtain a correct baseband RDS signal at the output of the filter 4 because the input RDS signal carrier and the output of the numerically controlled oscillator 13 are out of phase. The

phase-locked loop 5 tunes the phase and provides the baseband RDS signal. This behavior will be mathematically explained below.

Suppose the following two signals Re and Rs are input to the

phase-locked loop 5 : Rc = R (t)-cos () Rs = R (t)-sin () where R (t) is the baseband RDS signal, and is the current phase difference. The phase rotator 16 controls the two signals Re and Rs, as expressed by the following expressions, and generates signals Rco and Rso.

Reo = Rc-cos ( (p)-Rs-sin ( (p) = R (t).cos (#+#) Rso = Rc-sin ( (p) + Rs.cos (#) = R (t)-sin ( < )) + < p) Because feedback control through the loop filter 18 brings < p very close to -#, the output Rco becomes nearly equal to the baseband RDS signal R (t), and Rso approaches zero.

The third multiplier 17 multiplies the signal Rco by the signal

Rso and outputs {R (t)} 2-sin (2 < )) +2 (p)/2. While (+ < p) is sufficiently smaller than 45 , the output is roughly proportional to the magnitude of (o + (p), regardless of whether R (t) is positive or negative. Accordingly, ifthevalueof (pissetandfeedbackcontrol is performed in such a manner that the output {R (t)} 2. sin (20 + 29)/2 of the third multiplier 17 converges to zero, the output Rco of the phase rotator 16 can be supplied to the data decoder 2 as a baseband RDS signal R (t), as has been described above.

One might conceive of performing the feedback control to the

numerically controlled oscillator 13 in order to remove the phase rotator 16 from the configuration. With the simplified configuration, however, the delay and the like of the filter 4 are likely to result in unstable operation of the feedback loop.

One of big advantages of the configuration in accordance with the embodiment is stable operation.

< Function of Data Decoder 2 > The conventional analog circuit performs the integrate-and-dump processing (i. e. , the processing performed by the components 105 to 109 shown in Fig. 7A) to decode the baseband RDS signal as follows: (i) Set the sampling frequency of the processing data to an even multiple of the symbol frequency of the RDS signal and obtain a direct cumulative sum of the sample data of the first half of the symbol period.

(ii) Invert the sign of the sample data of the second half of the symbol period and obtain a direct cumulative sum of the sample data of the first and second halves of the symbol period.

For instance, in Fig. 4B and Fig. 5B, the sampling frequency is six times higher than the symbol frequency. By setting the sampling frequency to be in synchronization with the symbol frequency, as described above, data decoding can be simplified.

However, in the RDS decoder in accordance with the embodiment, the data output from the phase-locked loop 5 is not synchronized

with the symbol frequency. The fs converter 19 generates data having a sample frequency in synchronization with the symbol frequency from the data having a sample frequency out of synchronization with the symbol frequency. To be more specific, the fs converter 19 is configured to generate N pieces of data (virtual output data represented by crosses in Fig. 2) which interpolate intermediate data items between the original data (input data represented by circles in Fig. 2), as shown in Fig.

2, and to selectively output the virtual output data closest to a desired timing.

In the processing by the fs converter 19, a K-times oversampling filter is used, for instance. The K-times oversampling filter includes a filter having K x L coefficients at a sampling frequency K-times greater than the input sampling frequency. In other words, new data are generated and output at intermediate points between the original data by selecting one of the K sets of coefficients for L pieces of data.

The filter coefficient selector 25 gives the fs converter 19 an instruction to select the set of filter coefficients, which determines the timing of data generation.

The timing counter 24 gives the fs converter 19 an instruction to generate data and controls the timing of data generation through the filter coefficient selector 25.

Fig. 3 is an explanatory diagram for explaining the sampling frequency conversion by the data decoder of the RDS decoder in

accordance with the embodiment. The"COUNT"in Fig. 3 is a count obtained by the timing counter 24. The"DATA INPUT TIMING"in Fig.

3 is the timing at which data is input to the fs converter 19, and the"DATA OUTPUT TIMING"is the timing at which data is output from the fs converter 19.

As shown in Fig. 3, the timing counter 24 adds a numeric value N to the count obtained by the built-in counter each time data is input to the fs converter 19. When the count exceeds a numeric value M, the timing counter 24 gives the fs converter 19 an instruction to generate data. At the same time, the timing counter 24 sets the count to a value obtained by subtracting the numeric value M from the count obtained by the built-in counter (Ml or M2 in Fig. 3) and gives this value to the filter coefficient selector 25. The timing of data generation by the fs converter 19 is controlled accordingly.

The values Ml and M2 indicated in Fig. 3 can range from 1 to N. The filter coefficient selector 25 sets a filter coefficient so that the timing of data generation is advanced inversely with these values. Therefore, the timing of data output from the fs converter 19 will be evenly spaced in accordance with the numeric value M, as shown in Fig. 3.

Meanwhile, the sampling number counter 20 gives a cyclic sample number repeated in a symbol period to the data output from the fs converter 19. To be more specific, the sampling number counter 20 is a modulo P counter (P = 6 in this embodiment) and

counts data generation instructions made by the timing counter 24 and assigns a numeric value incremented by one (the numeric value is 0,1, 2,3, 4, or 5 in this embodiment). As the symbol timing is detected by the zero-cross detector 21, initialization is carried out so that the sample number becomes P/2 immediately after the occurrence of a zero-cross point in the middle of the symbol.

The timing error accumulator 22 obtains the cumulative sum of data values in the middle of the symbol period, as shown in Figs. 4A-AC and Figs. 5A-5C. In the examples shown in Figs. 4A-4C and Figs. 5A-5C, sample numbers 0 to 5 are assigned to the data of each symbol, the cumulative sum of the values of data having sample numbers 1 to 4 is obtained, and the resultant sum multiplied by the sign of the output concerning the same symbol (= Dt) from the integrate-and-dump filter 26 is provided as the final output Te. This processing is mathematically expressed as follows: Te = (si + S2 + S3 + S4)-sign (Dt) Dt = so + si + S 2 - (S 3 + s4 + s5) where so to Ss are data values corresponding to sample numbers 0 to 5, and sign (Dt) is a function that returns''I"or"- !"' depending on the sign of the output Dt.

If the output sample timing lags behind the symbol timing, as shown in Fig. 4A and Fig. 5A, Te becomes negative. If the output sample timing leads the symbol timing, as shown in Fig. 4C and Fig. 5C, Te becomes positive. If the output sample timing matches

the symbol timing, as shown in Fig. 4B and Fig. 5B, Te becomes almost zero. This indicates that the output Te of the timing error accumulator 22 is valid as a signal representing the timing error.

The increment selector 23 controls the behavior of the timing counter 24 in accordance with the output received from the timing error accumulator 22. The increment selector 23 usually sets the increment of the built-in counter of the timing counter 24 to a numericvalueN. Ifanytimingerrorresultsinalead, theincrement selector 23 temporarily sets the increment of the built-in counter to a value greater than the numeric value N. If any timing error results in a delay, the increment selector 23 temporarily sets the increment of the built-in counter to a value smaller than the numeric value N. The increment of the built-in counter is varied as described above, so that the difference between the output sample timing and the symbol timing is reduced.

Once the initialization is correctly performed, the fs converter 19 reduces the output of the filter coefficient selector 25 in accordance with the feedback control, so that synchronization between the subsequent symbol timing and sample numbers will be maintained.

The zero-cross detector 21 brings the sample numbers output from the sampling number counter 20 into synchronization with the RDS symbol, utilizing the characteristic that the RDS symbol always has a zero-cross point at its center. To be more specific, the zero-cross detector 21 first monitors the output of the fs converter

19 to detect and hold any difference in sign between the previous sample data and the current sample data. The zero-cross detector 21 checks all the sample data of the same symbol for difference in sign, and judges that synchronization with the symbol is correctly maintained if the sample number immediately after a sign-changing point or zero-cross point is P/2. Otherwise, the zero-cross detector 21 judges that synchronization is not maintained. The zero-cross detector 21 further determines the frequency of occurrence of the loss of synchronization. If the frequency is greater than a predetermined value, the zero-cross detector 21 updates the sample numbers so that P/2 becomes the sample number immediately after the most recently detected zero-cross point.

If the most recently detected zero-cross point is in the middle of the symbol period, the update processing establishes synchronization between the symbol timing and sample numbers. If the most recently detected zero-cross point is on a symbol boundary, an update of sample numbers will produce many P/2 numbers that do not follow a sign-changing point, as indicated in the"WRONG NUMBER SEQUENCE"in Fig. 6. These sample numbers must be updated again, then in due course, synchronization between the symbol timing and sample numbers will be established.

The integrate-and-dump filter 26 obtains the cumulative sum of the sample data that have been brought into synchronization with the symbol timing normally in the first half of the symbol period, and continues obtaining the cumulative sum in the second

half of the symbol period with the inverted sign. The integrate-and-dump filter 26 outputs the result at the completion of the cumulative summation for a single symbol.

The binarizer 27 outputs binary data"1"or 0, depending on the sign of the output from the integrate-and-dump filter 26.

The differential decoder 28 exclusive-ORs the input corresponding to the previous symbol and the current input and outputs reproduced RDS data.

The RDS decoder in accordance with the embodiment can reduce the number of processes performed by the RDS decoder and relaxes

the requirements concerning the reference clock of the processing, so that the signal processing system which incorporates the decoder and performs processing including FM radio reception processing can be easily implemented and the apparatus production cost can be reduced.

As has been described above, the RDS decoder in accordance with the present invention can reduce the number of filtering processes performed to extract an RDS signal from an FM composite audio signal and can stabilize the behavior of the phase-locked loop for obtaining the baseband RDS signal.

In addition, the RDS decoder in accordance with the present invention eliminates a conventional condition that the clock (reference timing) of signal processing must be synchronized with the RDS symbol frequency, so that its integration into apparatuses such as a digital signal processor that performs the main audio

signal processing concerning FM broadcasts is facilitated.

Claims

CLAIMS:

1. An RDS decoder comprising: a synchronous demodulator which receives a multiplex signal in which an RDS signal based on digital data is superimposed on an FM audio signal and generates a baseband RDS signal from the RDS signal; and a data decoder which decodes the baseband RDS signal generated by said synchronous demodulator into the digital data; wherein said synchronous demodulator includes: a quadrature demodulator which converts the multiplex signal into two baseband signals which differ in phase by 90 degrees; a filter which removes unwanted components having frequencies higher than a predetermined frequency level from the two baseband signals to reduce sample data; and a phase-locked loop which receives the two baseband signals output from said filter and generates the baseband RDS signal to be input to said data decoder from the two baseband signals, said phase-locked loop detecting and correcting phase error remaining in the baseband RDS signal.

2. The RDS decoder according to Claim 1, wherein said data decoder includes: a sampling frequency converter which receives the baseband RDS signal generated by said synchronous demodulator and performs

conversion of a frequency'of the baseband RDS signal, said sampling frequency converter being capable of adjusting a rate of the conversion; and a symbol phase error detector which detects a phase error of data output from said sampling frequency converter as compared with a transmission symbol; said sampling frequency converter adjusting the rate of the conversion in accordance with the phase error detected by said symbol phase error detector.

3. The RDS decoder according to Claim 1 or 2, wherein said quadrature demodulator includes: a first multiplier which includes a first input portion and a second input portion and outputs an output signal generated from a product of a signal input to said first input portion and a signal input to said second input portion; a second multiplier which includes a third input portion and a fourth input portion and outputs an output signal generated from a product of a signal input to said third input portion and a signal input to said fourth input portion; and a numerically controlled oscillator which outputs two quadrature signals which differ in phase by 90 degrees; wherein the multiplex signal is input to both said first input portion of said first multiplier and said third input portion of said second multiplier;

wherein the two quadrature signals output from said numerically controlled oscillator are input to said second input portion of said first multiplier and said fourth input portion of said second multiplier respectively; and wherein the output signal from said first multiplier and the output signal from said second multiplier are supplied to said filter.

4. The RDS decoder according to Claim 3, wherein said filter includes: a first low-pass filter which receives the output signal from said first multiplier; and a second low-pass filter which receives the output signal from said second multiplier.

5. The RDS decoder according to Claim 4, wherein said phase-locked loop includes: a phase rotator which receives an output signal from said first low-pass filter and an output signal from said second low-pass filter and outputs a phase rotated first signal and a phase rotated second signal; a third multiplier which receives the first signal and the second signal and outputs a signal generated by a product of the first signal and the second signal; and a loop filter which controls a phase rotation angle in said

phase rotator in such a way that the signal output from said third multiplier converges to zero; the first signal output from said phase rotator being supplied to said data decoder as the baseband RDS signal.

6. An RDS decoder comprising: a synchronous demodulator which receives a multiplex signal in which an RDS signal based on digital data is superimposed on an FM audio signal and generates a baseband RDS signal from the RDS signal; and a data decoder which decodes the baseband RDS signal generated by said synchronous demodulator into the digital data; said data decoder including: a sampling frequency converter which receives the baseband RDS signal generated by said synchronous demodulator and performs conversion of a frequency of the baseband RDS signal, said sampling frequency converter being capable of adjusting a rate of the conversion; and a symbol phase error detector which detects a phase error of data output from said sampling frequency converter as compared with a transmission symbol; said sampling frequency converter adjusting the rate of the conversion in accordance with the phase error detected by said symbol phase error detector.

7. The RDS decoder according to Claim 2 or 6, wherein said data decoder adjusts a transmission symbol in such away that a zero-cross point of the transmission symbol output from said sampling frequency converter is placed in the middle of a symbol period.

8. An RDS decoder substantially as hereinbefore described and as shown in the accompanying drawings.