JP3865628B2 - RDS decoder - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an RDS decoder used in a radio data system (RDS) that transmits an RDS signal based on digital data superimposed on an FM audio signal.
[0002]
[Prior art]
In RDS broadcasting, a method of transmitting an RDS signal modulated in a frequency band (57 kHz) three times that of a pilot signal on an FM audio signal having a pilot signal of 19 kHz (that is, multiplex transmission) is employed. . The transmitted RDS signal is obtained by performing binary phase modulation (BPSK) on binary time-series data that has been differentially encoded, and performing double-sided modulation on a 57 kHz subcarrier using the BPSK signal. An RDS radio receiver is used to receive RDS broadcasts. The RDS radio receiver has an RDS decoder for demodulating and decoding an RDS signal, in addition to a receiving circuit (FM tuner unit) for receiving an FM broadcast signal and a digital audio signal processing circuit for audio reproduction. . FIG. 7 is a block diagram showing a configuration of a conventional RDS decoder disclosed in Japanese Patent No. 2593079.
[0003]
In the RDS decoder shown in FIG. 7, a band pass filter (BPF) 101 extracts only an RDS signal centered on 57 kHz from an FM composite audio signal obtained by detecting an FM broadcast signal. The subcarrier reproducing means 103 synchronously detects an RDS signal that is modulated on both sides and does not have a carrier, and provides the multiplier 102 with a reproduced carrier signal having the same phase and frequency as the RDS subcarrier. The subcarrier reproducing means 103 is configured as a phase locked loop of, for example, a Costas loop format.
[0004]
The output of the multiplier 102 includes a baseband RDS signal and an unnecessary component signal of 114 kHz. A low-pass filter (LPF) 104 removes unnecessary component signals and outputs a baseband RDS signal. The LPF 104 also has a function of improving the performance of the RDS decoder by passing only the spectrum necessary for decoding and eliminating noise.
[0005]
The symbol clock recovery means 106 detects a BPSK symbol break from the baseband RDS signal output from the LPF 104. The symbol clock recovery means 106 determines the symbol clock period (symbol rate 1187.5 Hz) by utilizing the fact that the period of the symbol clock is 48 times the 57 kHz subcarrier period, and the BPSK signal is placed at the center of the waveform. The phase of the BPSK signal is determined using the fact that it always has a zero cross point.
[0006]
The inverting amplifier 105 is an inverting amplifier having a gain of 1. Switch 107 is controlled by a symbol clock (waveform SC in FIG. 7) provided from symbol clock recovery means 106. The switch 107 directly controls the baseband RDS signal (waveform R in FIG. 7) only in the first half cycle period of one cycle (symbol period) of the symbol clock.₁) To the integrator 109, and the output from the inverting amplifier 105 (waveform R in FIG. 7) during the second half cycle period of the symbol period.₂) To the integrator 109. Thus, when the BPSK modulation phase is 0 degree, for example, a positive potential is applied to the integrator 109 throughout the entire symbol period, and when the BPSK modulation phase is 180 degrees, for example, the integrator 109 is transmitted through the entire symbol period. A negative potential is applied.
[0007]
Integration result by integrator 109 (waveform R in FIG. 7₃) Is determined to be positive or negative by the slicer 110 at the end of the symbol period, and decoded into binary data. Processing performed in synchronization with this symbol period is called integration and dump processing. Switch 108 closes at the beginning of the symbol period to initialize the state of integrator 109.
[0008]
The flip-flop circuit 111 takes in the output of the slicer 110 at the last timing of the symbol period (which is also the first timing of the next symbol), and holds the value at the output during the next symbol period. The flip-flop circuit 112 holds the output of the preceding flip-flop circuit 111 with a delay of one symbol period. Therefore, the exclusive OR circuit (XOR) 113 gives an output of “true” when adjacent data in the time series of the data carried by the BPSK symbol are different, and “false” when they are the same. To perform differential decoding.
[0009]
[Problems to be solved by the invention]
As described above, the conventional RDS decoder is configured as a circuit dedicated to decoding processing. First, an RDS signal is extracted from an FM composite audio signal by the BPF 101 that passes a signal in a band centered on a subcarrier. We were processing. Further, a master clock synchronized with the subcarrier frequency or the symbol rate is used as the clock signal for determining the processing timing of the RDS signal extracted by the BPF 101. For this reason, when an RDS decoder is incorporated as part of a digital signal processing system that performs reception processing for receiving FM audio broadcasting, digital audio signal processing for audio reproduction, and the like, the following two types are shown. There was a big problem.
[0010]
The first problem relates to the BPF 101 that is a subcarrier extraction filter. The BPF 101 has the following functional requirements.
(1) It is necessary to have a pass band at a subcarrier frequency which is a relatively high frequency.
(2) It is necessary to narrow the pass band even though the subcarrier frequency is a relatively high frequency.
(3) It is necessary to sufficiently increase the attenuation outside the passband.
For this reason, the BPF 101 needs to use a filter having a high sampling frequency and a large order, and there is a problem that the number of processes is increased.
[0011]
The second problem relates to the sampling frequency of the decoding process. In the decoding process of the RDS signal, it is desired to process the data in synchronization with the timing of the transmission symbol. However, when the basic clock is determined by giving priority to other processes such as radio signal processing and digital audio signal processing, it is generally impossible to generate a sampling frequency synchronized with a transmission symbol from a simple integer ratio of the basic clock frequency. . In other words, there is a problem that it is difficult to adjust the basic clock frequency to synchronize with the frequency of the RDS transmission symbol in the operation of other systems.
[0012]
Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object thereof is an RDS decoder capable of reducing the number of processes for extracting an RDS signal from an FM composite audio signal. Is to provide.
[0013]
Another object of the present invention is to eliminate the restriction that the RDS signal processing clock (time reference) must be synchronized with the RDS symbol frequency, and to provide a digital signal processing system that performs FM audio main audio signal processing. An object of the present invention is to provide an RDS decoder that can be easily integrated.
[0015]
The RDS decoder according to claim 2 is:
The data decoding means is
Sampling frequency conversion means configured to receive the baseband RDS signal generated by the synchronous demodulation means and adjust the conversion ratio as appropriate,
Symbol phase error detection means for detecting a phase error between data output from the sampling frequency conversion processing unit and transmission symbol timing;
Have
The sampling frequency converting means adjusts the conversion ratio of the sampling frequency converting means based on the phase error detected by the symbol phase error detecting means.
It is characterized by that.
[0016]
The RDS decoder according to claim 3 is:
The orthogonal demodulation means comprises:
A first multiplication processing unit that has a first input unit and a second input unit, and outputs a multiplication result of the signal input to the first input unit and the signal input to the second input unit; ,
A second multiplication processing unit that has a third input unit and a fourth input unit, and outputs a multiplication result of the signal input to the third input unit and the signal input to the fourth input unit; ,
A numerically controlled oscillator that outputs two signals that are 90 ° out of phase with each other;
Have
The multiplexed signal is input to both the first input unit of the first multiplication processing unit and the third input unit of the second multiplication processing unit,
Two signals output from the numerical control oscillator and having a phase difference of 90 ° are respectively input to the second input unit of the first multiplication processing unit and the fourth input unit of the second multiplication processing unit. Entered,
An output signal from the first multiplication processor and an output signal from the second multiplication processor are provided to the filter means.
It is characterized by that.
[0019]
[Means for Solving the Problems]
  An RDS decoder according to claim 1 comprises:
  Synchronous demodulation means for receiving a multiplexed signal obtained by multiplexing an RDS signal based on digital data on an FM audio signal and generating a baseband RDS signal from the RDS signal;
  Data decoding means for restoring the digital data from the baseband RDS signal generated by the synchronous demodulation means,
  The data decoding means is
  in frontRecordingSource band RDS signal is inputRuSampling frequency conversion means;
  Sampling frequency conversionmeansSymbol phase error detection means for detecting a phase error between data output from the transmission symbol and transmission symbol timing;Composed of
  TheSampling frequency conversion means,
  A low-pass filter capable of generating a plurality of timing data that interpolates input data with a plurality of coefficient sets is provided, and the data at the time closest to the desired timing synchronized with the RDS symbol is selected by the coefficient set selection of the low-pass filter. It is configured to perform sampling frequency conversion at a desired conversion ratio through sequential generation and output, and at the same time, it is configured to be able to adjust this conversion ratio based on the phase error detected by the symbol phase error detection means. Ru
  It is characterized by that.
[0020]
  Claims2The RDS decoder according to
  The data decoding means adjusts the transmission symbol timing so that the zero cross point of the transmission symbol output from the sampling frequency conversion processing unit is located at the center of the symbol period.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
In RDS broadcasting, an FM audio signal is transmitted by superimposing an RDS signal based on digital data. An RDS radio receiver is used to receive RDS broadcasts. The RDS decoder according to the invention is usually equipped as part of an RDS radio receiver.
[0022]
<Description of configuration of RDS decoder>
FIG. 1 is a block diagram showing a configuration of an RDS decoder according to an embodiment of the present invention. As shown in FIG. 1, the RDS decoder according to the present embodiment receives an FM composite audio signal obtained by detecting an FM broadcast signal transmitted by superimposing an RDS signal on an FM audio signal, and receives a baseband RDS. Synchronous demodulation means 1 for outputting a signal is provided. In addition, the RDS decoder according to the present embodiment has data decoding means 2 that receives the baseband RDS signal from the synchronous demodulation means 1 and outputs the same RDS data as the transmission digital data.
[0023]
The synchronous demodulating unit 1 includes an orthogonal demodulating unit 3, a filter unit 4, and a phase synchronizing unit 5. The orthogonal demodulation unit 3 includes a first multiplication processing unit 11, a second multiplication processing unit 12, and a numerically controlled oscillator (numerically controlled oscillator) 13. The filter unit 4 includes an I branch filter (LPF) 14 and a Q branch filter (LPF) 15. The phase synchronization means 5 includes a phase rotation processing unit 16, a third multiplication processing unit 17, and a loop filter 18.
[0024]
The data decoding unit 2 includes a sampling frequency conversion unit 6, a symbol phase error detection unit 7, an integration and dump (I & D) processing unit 26, a binarization processing unit 27, a differential decoding processing unit 28, A clock (CLK) generation processing unit 29 for generating a clock signal based on the symbol clock. The sampling frequency conversion means 6 includes a sampling frequency conversion processing unit 19, an increment setting processing unit 23, a timing counting processing unit 24, and a filter coefficient setting processing unit 25. The symbol phase error detection unit 7 includes a sample number counting processing unit 20, a zero cross (ZC) detection processing unit 21, and a timing error accumulation processing unit 22.
[0025]
Each said structure can be comprised by the hardware which has a function demonstrated below, software, or these combination.
[0026]
<Description of Function of Synchronous Demodulation Unit 1>
The input signal of the synchronous demodulation means 1 is a composite audio signal after FM detection. The sampling frequency of this input signal is about 120 kHz or higher (that is, 57 kHz ± 2.P) which can suppress the influence of aliasing distortion or the like on the RDS signal band having a component of approximately 57 kHz ± 2.4 kHz. 4 times or more of 4 kHz). This can be given directly by digital detection, or can be given after analog (digital to analog) conversion of an analog composite audio signal.
[0027]
The composite audio signal thus input is first converted into two orthogonal baseband signals by the orthogonal demodulation means 3. The orthogonal demodulation means 3 includes a first multiplication processing unit 11, a second multiplication processing unit 12, and a numeric oscillator 13. The numeric oscillator 13 has a frequency substantially equal to the subcarrier frequency 57 kHz and supplies two signals having a phase difference of 90 ° to one input section of the first and second multiplication processing sections 11 and 12. A composite audio signal is given to the other input section of the first and second multiplication processing sections 11 and 12. For this reason, a signal in which the subcarrier frequency is converted to a substantially zero frequency appears at the output section of each multiplier 11, 12. In addition, components outside the RDS signal band are converted to higher frequencies. The quadrature demodulating means 3 gives the two orthogonal baseband signals thus obtained to the filter means 4.
[0028]
The filter unit 4 has both a filter function for removing unnecessary signals and a thinning function for thinning sample data while reducing the adverse effects of aliasing distortion to reduce the sampling frequency. The filter means 4 includes an I branch filter 14 and a Q branch filter 15 which are two filters having equivalent characteristics corresponding to two orthogonal baseband signals output from the orthogonal demodulation means 3. At this time, the two signal output components of the I-branch filter 14 and the Q-branch filter 15 are converted to a band of approximately 0 to 2.4 kHz and output. For this reason, the sampling frequency at this stage can be reduced to about 5 kHz or more (that is, twice or more of 2.4 kHz). Therefore, in the I branch filter 14 and the Q branch filter 15, a large amount of data can be thinned out, and when the filter format is an FIR (Finite Impulse Response) type, the number of processing steps is greatly reduced. be able to.
[0029]
For comparison, a filter is considered in which there is almost no attenuation at 57 kHz ± 1.2 kHz and the attenuation outside the band of 57 kHz ± 3 kHz is 40 dB. In this case, it is necessary to perform processing of about 143 coefficients with a sampling frequency of 128 kHz. When this is counted as the number of product-sum operations required per second, it is about 18.3 × 10.⁶It becomes. Therefore, if the same processing is performed with a filter having the same characteristics for the baseband signal (57 kHz), the required filter coefficient is also 143. On the other hand, when the output of the filter unit 4 is converted into a band of 0 to 2.4 kHz as in the RDS decoder according to the present embodiment, for example, the sampling frequency is 8 kHz (an example of a frequency of about 5 kHz or more). ) To reduce the number of data to 1/16 (= 8 kHz / 128 kHz) (that is, a thinning process). Therefore, in the case of the RDS decoder according to the present embodiment, the actual filtering process needs to be performed only for the output having a frequency of 1/16 with respect to the input. For this reason, the number of processing steps (the number of product-sum operations) can be reduced to 1/16 compared to the case where filter processing is performed in the 57 kHz band for each of the two branch filters 14 and 15. Therefore, even if the two branch filters 14 and 15 are combined, the number of processes is reduced to 1/8 (= 2 × 1/16).
[0030]
Further, the I branch filter 14 and the Q branch filter 15 have a low-pass characteristic for attenuating and removing unnecessary components, and a raised cosine (roll off rate 0.5 for waveform shaping) ( By providing an approximation to the raised cosine characteristic, it is possible to improve the decoding processing performance. This means that the processing of the filters (reference numerals 101 and 104 in FIG. 7) applied to the signal after synchronous detection in the conventional RDS decoder is simultaneously performed at this stage, and the reduction of the components and the total It is possible to reduce the number of processing steps.
[0031]
By the way, in the same area as the RDS broadcast area, there is a case where a broadcast with a traffic information service called an ARI (Autofahrer Rundfunk Information) broadcast adopting a method different from the RDS broadcast is performed. is there. This ARI is transmitted with a subcarrier frequency and a spectrum very close to this. Since RDS broadcasting and ARI broadcasting may be performed simultaneously in the same area, it is necessary to prevent the decoding operation of the RDS decoder from being adversely affected by ARI broadcasting. According to the RDS decoder according to the present embodiment, this can be easily realized by adding to the I branch filter 14 and the Q branch filter 15 a high-pass characteristic that blocks the spectrum of the ARI transmission signal. Actually, the spectrum of the ARI transmission signal is distributed in a frequency band of approximately 250 Hz or less, whereas the spectrum of the RDS signal is distributed around about 1.2 kHz. Therefore, when it is necessary to prevent the RDS decoder from being adversely affected by the ARI broadcast, this object can be effectively achieved by adding only a filter that attenuates only a component of approximately 250 Hz or less.
[0032]
At the output of the filter means 4, an RDS signal having substantially zero frequency is obtained. However, in the RDS decoder according to the present embodiment, the phase of the input RDS signal carrier and the output of the numeric oscillator 13 are not synchronized at the output stage of the filter means 4, so that the baseband RDS signal is correctly obtained. I can't. Therefore, the phase synchronization means 5 performs an operation of adjusting the phase and extracting the baseband RDS signal. The operation will be described below using mathematical expressions.
[0033]
First, the two signals R entering the phase synchronization means 5_cAnd R_sThe
R_c= R (t) · cos (φ)
R_s= R (t) · sin (φ)
And Here, R (t) is a baseband RDS signal, and φ represents a phase error at that time. The phase rotation processing unit 16 outputs the two signals R_cAnd R_sTo the signal R_coAnd R_soIs generated.
R_co= R_c・ Cos (ψ) -R_sSin (ψ) = R (t) · cos (φ + ψ)
R_so= R_c・ Sin (ψ) + R_sCos (ψ) = R (t) sin (φ + ψ)
Here, since feedback control is performed through the loop filter 18 so that ψ is substantially equal to −φ, R_coThe output will eventually be approximately equal to the baseband RDS signal R (t) and R_soApproaches 0.
[0034]
The third multiplication processing unit 17 receives the signal R_coAnd R_so{R (t)} by multiplying²・ Sin (2φ + 2ψ) / 2 is obtained as an output. This output gives an output substantially proportional to the magnitude of (φ + ψ) in a range where (φ + ψ) is sufficiently smaller than ± 45 °, regardless of whether R (t) is positive or negative. Therefore, the output {R (t)} of the third multiplication processing unit 17²By setting the value of ψ and performing feedback control so that sin (2φ + 2ψ) / 2 converges to 0, as described above, the output R of the phase rotation processing unit 16_coCan be given to the data decoding unit 2 as a baseband RDS signal R (t).
[0035]
Although it may be considered that the phase rotation processing unit 16 is omitted by performing this feedback control on the numeric oscillator 13, the operation of the feedback loop is actually caused by the influence of the delay or the like in the filter unit 4. Tends to be unstable. Therefore, the configuration of the present embodiment has a great advantage that stable operation can be achieved.
[0036]
<Description of Function of Data Decoding Unit 2>
When the processing for decoding the baseband RDS signal is performed by the integration and dump processing (processing by the configurations 105 to 109 in FIG. 7) using the conventional analog circuit, the sampling frequency of the processing data is set to an even symbol frequency of the RDS signal. It is possible to multiply the sample data in the first half of the symbol period as they are, add them as they are, invert the sign of the sample data in the second half of the symbol periods, and further add them cumulatively. For example, FIGS. 4B and 5B show a case where the sampling frequency is 6 times the symbol frequency. Thus, by synchronizing the sampling frequency with the symbol frequency, the data decoding process can be realized simply.
[0037]
However, in the RDS decoder according to the present embodiment, the data given as the output of the phase synchronization means 5 is not synchronized with the symbol frequency. The sampling frequency conversion processing unit 19 generates sample frequency data synchronized with the symbol frequency from the sample frequency data not synchronized with the symbol frequency. Specifically, as shown in FIG. 2, the sampling frequency conversion processing unit 19 performs N data (in FIG. 2) for interpolating between the original data (input data “◯” in FIG. 2). Virtual output data “×”) can be generated, and the process of selecting and outputting the data at the time closest to the desired timing from the virtual output data is performed.
[0038]
The actual processing in the sampling frequency conversion processing unit 19 uses, for example, a K-times oversampling filter. The K-times oversampling filter consists of a subset of K sets of L coefficients based on a K × L coefficient filter at a sampling frequency K times the input sampling frequency. In other words, by convolving one of the K coefficient sets with the L data, new data positioned at an intermediate timing of the original data is generated and output.
[0039]
The filter coefficient setting processing unit 25 instructs the sampling frequency conversion processing unit 19 to select this filter coefficient group, and determines the timing of data generated thereby.
[0040]
The timing counting processing unit 24 gives a data generation instruction to the sampling frequency conversion processing unit 19 and controls the timing of data generated via the filter coefficient setting processing unit 25.
[0041]
FIG. 3 is an explanatory diagram for explaining the sampling frequency conversion processing in the data decoding means 2. In FIG. 3, “count value” indicates a count value of the timing count processing unit 24. In FIG. 3, “input data timing” indicates the timing at which data is input to the sampling frequency conversion processing unit 19, and “output data timing” indicates the timing at which data is output from the sampling frequency conversion processing unit 19. Show.
[0042]
As shown in FIG. 3, the timing count processing unit 24 performs a process of adding a numerical value N to the count value of the built-in counter every time data is input to the sampling frequency conversion processing unit 19. When the count value exceeds the numerical value M, the timing count processing unit 24 gives a data generation instruction to the sampling frequency conversion processing unit 19. At the same time, the timing counting processing unit 24 uses the values obtained by subtracting the numerical value M from the count value of the built-in counter (M1, M2 in FIG. 3) as the counter count value, and further sets this value as the filter coefficient setting. By giving it to the processing unit 25, the timing of data generated by the sampling frequency conversion processing unit 19 is controlled.
[0043]
At this time, the values M1 and M2 shown in FIG. 3 are values in the range of 1 to N. The filter coefficient setting processing unit 25 sets the filter coefficient so as to generate data with advanced timing in inverse proportion to this value. For this reason, the data output from the sampling frequency conversion processing unit 19 has substantially equal intervals corresponding to the numerical value M as shown in FIG.
[0044]
Here, the sample number counting processing unit 20 gives a sample number repeated in the symbol period to the data output from the sampling frequency conversion processing unit 19, and actually instructs the data generation from the timing counting processing unit 24. By counting, a numerical value (that is, 0, 1, 2, 3, 4, 5) that sequentially increases by 1 modulo P (P = 6 in the present embodiment) is used. According to the detection of the symbol timing by the zero cross detection processing unit 21, initial setting is performed so that the number immediately after the occurrence of the zero cross at the center of the symbol is P / 2.
[0045]
As shown in FIGS. 4 and 5, the timing error accumulation processing unit 22 accumulates and adds data values in the central part of the symbol period. In the examples of FIGS. 4 and 5, the data values corresponding to the sample numbers 1 to 4 are cumulatively added to the data with the sample numbers 0 to 5 in synchronization with the symbols. For the result, the output of the integration and dump processing unit 20 of the same symbol (= D_t) Multiplied by the sign of the final output T_eAnd This is expressed by the following formula.
T_e= (S₁+ S₂+ S₃+ S₄) ・ Sign (D_t)
D_t= S₀+ S₁+ S₂-(S₃+ S₄+ S₅)
Where s₀To s₅Are data values corresponding to sample numbers 0 to 5, respectively, and sign (D_t) Is the output D_tIs a function that takes "1" or "-1" according to the sign of.
[0046]
As shown in FIGS. 4A and 5A, when the output sample timing is delayed from the symbol timing, T_eBecomes negative. As shown in FIGS. 4C and 5C, when the output sample timing is ahead of the symbol timing, T_eBecomes positive. Furthermore, as shown in FIGS. 4B and 5B, if the output sample timing matches the symbol timing, T_eBecomes almost zero. From this, the output T of the timing error accumulation processing unit 22_eIs effective as a signal representing a timing error.
[0047]
The increment setting processing unit 23 receives the output of the timing error accumulation processing unit 22 and controls the operation of the timing count processing unit 24. The increment setting processing unit 23 normally sets the count value of the built-in counter to increase the count value of the built-in counter by a numerical value N, whereas if there is a timing error in the advance direction, The increment of the count value of the built-in counter is set larger than the numerical value N. Conversely, if there is a timing error in the delay direction, the increment of the count value of the built-in counter is temporarily set smaller than the numerical value N. Thus, by changing the increment of the built-in counter, the output sample timing operates so as to reduce the error from the symbol timing.
[0048]
For this reason, once this initial setting is correctly performed, the sampling frequency conversion processing unit 19 acts to reduce the output of the filter coefficient setting processing unit 25 by feedback control, so that the symbol timing and the sample number are synchronized thereafter. The relationship will be maintained.
[0049]
The zero cross detection processing unit 21 synchronizes the RDS symbol with the sample number output from the sample number counting processing unit 20 by utilizing the characteristic that a zero cross always exists in the center of the RDS symbol. Actually, the zero-cross detection processing unit 21 first monitors the output of the sampling frequency conversion processing unit 19 to detect and hold a change in the sign between the previous data and the current data. The zero cross detection processing unit 21 checks this up to the final data of the symbol, and determines that the synchronization with the symbol is correctly maintained when the sign change, that is, the sample number immediately after the zero cross is P / 2, Otherwise, it is determined that synchronization is lost. The zero-cross detection processing unit 21 further determines the frequency of this synchronization loss, and if this frequency is greater than a predetermined value, the sample number update processing of aligning the recently observed sample number immediately after the zero-cross to P / 2 I do.
[0050]
By this update processing, when the recently observed zero cross is located at the center of the symbol period, the synchronization relationship between the symbol timing and the sample number is established. Further, even if the observed zero cross is located at the symbol boundary, when the sample number is updated in this way, the sample number P is shown as shown in the column of “missequence of sample numbers” in FIG. The case where the code does not change at / 2 occurs frequently, and the sample number is updated again, so that the synchronization relationship between the symbol timing and the sample number is established soon.
[0051]
The integration and dump processing unit 26 accumulates and adds the sample data of the first half of the symbol period as it is to the sample data synchronized with the symbol timing in this way, and further performs the cumulative addition by inverting the sign of the sample data of the second half of the symbol period. The integration and dump processing unit 26 outputs the result when accumulation for one symbol is completed.
[0052]
The binarization processing unit 27 outputs binary data “1” or “0” in accordance with the sign of the output from the integration and dump processing unit 26.
[0053]
The differential decoding processing unit 28 performs exclusive OR of the input corresponding to the previous symbol and the current input, and reproduces and outputs the RDS data.
[0054]
According to the RDS decoder according to the present embodiment, it is possible to easily realize a signal processing system including an FM radio reception process in which the RDS decoder process is reduced and the requirements regarding the basic clock of the process are relaxed. As a result, the device manufacturing cost can be reduced.
[0056]
【The invention's effect】
  Claims 1 and 2According to the RDS decoder of the present invention, the digital signal for performing the main audio signal processing of FM broadcasting is eliminated by eliminating the restriction of synchronizing with the RDS symbol frequency conventionally imposed on the clock (time reference) of signal processing. There is an effect that it can be easily integrated into a processing apparatus or the like.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an RDS decoder according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram for explaining sampling frequency conversion processing in data decoding means of the RDS decoder according to the embodiment of the present invention;
FIG. 3 is an explanatory diagram for explaining sampling frequency conversion processing in data decoding means of the RDS decoder according to the embodiment of the present invention;
FIGS. 4A to 4C are explanatory diagrams for explaining sampling frequency conversion processing of the RDS decoder according to the embodiment of the present invention.
FIGS. 5A to 5C are explanatory diagrams for explaining sampling frequency conversion processing of the RDS decoder according to the embodiment of the present invention.
FIG. 6 is an explanatory diagram for explaining zero-cross detection processing of the RDS decoder according to the embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a conventional RDS decoder.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Synchronous demodulation means, 2 Data decoding means, 3 Orthogonal demodulation means, 4 Filter means, 5 Phase synchronization means, 6 Sampling frequency conversion means, 7 Symbol phase error detection means, 11 1st multiplication process part, 12 2nd multiplication Processing unit, 13 numeric oscillator, 14 I branch filter (LPF), 15 Q branch filter (LPF), 16 phase rotation processing unit, 17 third multiplication processing unit, 18 loop filter, 19 sampling frequency (fs) conversion processing Unit, 20 sample number counting processing unit, 21 zero cross (ZC) detection processing unit, 22 timing error accumulation processing unit, 23 increment setting processing unit, 24 timing counting processing unit, 25 filter coefficient setting processing unit, 26 integration and dump (I & D) processor 27 Binary processing unit, 28 differential decoding processing unit, 29 clock (CLK) generation processing unit, 101 BPF, 102 multiplier, 103 subcarrier recovery means, 104 LPF, 105 inverting amplifier, 106 symbol clock recovery means, 107 switch, 108 switches, 109 integrators, 110 slicers, 111 flip-flop circuits, 112 flip-flop circuits, 113 exclusive OR circuits (XOR), 114 differential decoders.

Claims (2)

Synchronous demodulation means for receiving a multiplexed signal obtained by multiplexing an RDS signal based on digital data on an FM audio signal and generating a baseband RDS signal from the RDS signal;
Data decoding means for restoring the digital data from the baseband RDS signal generated by the synchronous demodulation means,
The data decoding means is
And Lusa sampling frequency conversion means is pre Kibe baseband RDS signal is input,
A symbol phase error detecting means for detecting a phase error between the data output from the sampling frequency converting means and the transmission symbol timing ;
The sampling frequency conversion means,
A low-pass filter capable of generating a plurality of timing data that interpolates input data with a plurality of coefficient sets is provided, and the data at the time closest to the desired timing synchronized with the RDS symbol is selected by the coefficient set selection of the low-pass filter. It is configured to perform sampling frequency conversion at a desired conversion ratio through sequential generation and output, and at the same time, it is configured to be able to adjust this conversion ratio based on the phase error detected by the symbol phase error detection means. RDS decoder, characterized in that that.   2. The RDS decoder according to claim 1, wherein the data decoding means adjusts a transmission symbol timing so that a zero cross point of a transmission symbol output from the sampling frequency conversion processing unit is located at the center of a symbol period.

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