JPH05257872A - Multisignal processing system and signal processing element - Google Patents

Abstract

PURPOSE:To provide the multisignal processing system of simple constitution which has a high degree of freedom of connection and performs high-speed signal processing. CONSTITUTION:The multisignal processing system which has two communication paths of a common bus system and a local bus system is constituted by providing plural signal processing elements 11-14 which have signal processors and are provided with at least two bus connection parts for the signal processors, a common memory 9 that the signal processing elements 11-14 share, a common bus 8 which connects the signal processing elements 11-14 to the common memory 9, an interface circuit 10 which controls interface processing between an external bus 2 and the common bus 8 and data transfer among the signal processing elements, and local buses 15-19 which mutually connect the respective signal processing elements 11-14. The local bus system between those two communication paths is used to preform real-time signal processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-signal processing system for performing high-speed signal processing using a plurality of signal processing devices such as DSPs and a signal processing element applicable to the system.

[0002]

2. Description of the Related Art Recent advances in semiconductor technology have led to the emergence of signal processing devices such as DSPs that can perform floating-point arithmetic at high speed. However, even with such a signal processing device, it is difficult for one signal processing device to perform a large amount of calculation such as voice recognition in real time in voice processing that often requires real-time processing. Therefore, it is conceivable to configure a so-called multi-signal processing system that enables real-time processing by combining a plurality of signal processing devices.

FIG. 6 is a diagram showing a configuration example of this multi-signal processing system. In the figure, 1 is a host computer (hereinafter referred to as a host) including a workstation, 2 is a host bus such as a VME bus, 3 is an interface circuit (IF), 4, 5, 6 and 7 are signal processing devices,
Reference numeral 8 indicates a shared bus, and 9 indicates a shared memory.
In this configuration, the signal processors 4, 5, 6, 7 and the shared memory 9 are connected by the shared bus 8, and the host bus 2
The interface circuit 3 manages the interface processing between the signal processing apparatus and the shared bus 8 and the data transfer between the signal processing devices.

[0004]

However, in the above-described multi-signal processing system, when the memory on the shared bus 8 is accessed, other signal processing devices cannot be accessed. Further, when a signal processing device such as a DSP is directly connected to the host 1 such as a workstation, when the number of signal processing devices increases, the traffic of the shared bus 8 increases and the host 1
Burdens you. Further, a general-purpose bus such as the VME bus has a drawback that the speed of the bus is slow. Further, if communication between signal processing devices and transfer of real-time data from the analog / digital converter are performed on the shared bus 8, it takes time to acquire the bus, and a delay may occur with respect to data input in real time. is there.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a multi-signal processing system having a simple structure, a high degree of freedom in connection, and a high-speed signal processing. ..

[0006]

In order to achieve the above object, the present invention has a plurality of signal processing elements having a signal processing device and having at least two system bus connection parts for the signal processing device, and a plurality of these signal processing elements. A shared memory shared by a plurality of signal processing elements, a shared bus connecting each signal processing element to the shared memory, an interface processing between an external bus and a shared bus, and management of data transfer between each signal processing element. An interface circuit,
A local bus that connects the signal processing elements to each other, each of the signal processing elements is connected to the interface circuit via the shared bus,
It is configured to be connected to another adjacent signal processing element via the local bus.

According to the present invention, the above-mentioned signal processing element is provided with a switching means for switching between connection and non-connection with the shared bus at a connection portion with the shared bus, and a bus connection between the signal processing device and the switching means. And a shared local memory that can be shared by the signal processing devices of the respective signal processing elements via a shared bus, and the shared local memory is connected to the other through the shared bus when the switching means is in the connected state. The signal processing device of the signal processing element is also accessed, and when the switching means is in the unconnected state, it is accessed only from the signal processing device of the signal processing element.

A signal processing device is provided, and a first internal bus and a second internal bus are provided for connecting the signal processing device to two communication paths consisting of at least a first bus and a second bus. A signal processing element, which is provided in the first internal bus and includes switching means for switching connection / disconnection with the first bus, and a first internal bus between the signal processing device and the switching means. It is configured to have a shared local memory connected thereto and at least one port connected to the second internal bus and connected to the second bus.

[0009]

According to the present invention, a shared bus system and a local bus system are provided.
The communication channel of the grid is established. In the shared bus system, data transfer is performed in packet units, for example. That is, in each signal processing element, the packet to be transmitted is transferred to the interface circuit. The interface circuit deciphers the transfer destination of the input packet and transfers the packet to another signal processing element or the host computer which is the transfer destination.

On the other hand, the data output from the input / output device via the local bus is converted into digital data by an analog / digital converter or the like and input to a certain signal processing element. This data is subjected to predetermined processing by the signal processing device according to a predetermined flow, and the result is output to one or a plurality of signal processing elements of the next stage via the local bus.

In the present invention, when the switching means provided in the signal processing element is switched to the non-connection state, the shared local bus is disconnected from the shared bus system. This allows
By the signal processing device, the shared local memory is accessed at high speed without being involved in so-called arbitration.

According to the present invention, the shared local bus is disconnected from the first bus when the switching means is switched to the unconnected state. As a result, the signal processing apparatus can access the shared local memory at high speed without being involved in so-called arbitration, and data transfer is performed only by the second bus system. Also, the connection with the second bus is changed via the port. Thereby, when there are a plurality of signal processing elements, the signal processing elements are connected in an arbitrary connection form.

[0013]

1 is a block diagram showing an embodiment of a multi-signal processing system according to the present invention, in which the same components as those in FIG. 6 are designated by the same reference numerals. That is, 1 is a host (host computer) including a workstation,
2 is a host bus as an external bus composed of a VME bus or the like, 8 is a shared bus, 9 is a shared memory, 10 is an interface processor (hereinafter, IFP (Interface Processor))
11, 12, 13, 14 are signal processing elements including a signal processing device (hereinafter, PE (Processing Elemen).
t)), 15, 16, 17, 18, 19 are local buses, 20 is an analog / digital (A / D) converter, 2
Reference numeral 1 denotes a digital / analog (D / A) converter.

The IFP 10 is, for example, a DSP, more specifically, a DSP96002 (clock 3) manufactured by Motorola.
3.3 MHz, floating-point multiply-accumulate operation 60 ns), and the interface function between the relatively low-speed host bus 2 and high-speed shared bus 8 and each PE 11, 12, 13,
The data transfer between 14 is managed.

As shown in FIG. 2, the PEs 11, 12, 13, and 14 respectively include a signal processing device 101 and an internal bus 10.
2, 103, a changeover switch (SW) 104, a shared local bus 105, a local bus connection right port 106, a local bus connection left port 107, a dual port memory 108 and a local memory 109. Each PE11,
12, 13, 14 are of a predetermined size, for example 234 mm
The respective parts 101 to 109 are mounted or formed on a substrate of 220 mm.

The signal processing device 101 includes two ports P1 and P1.
2 with a DSP, such as IFP10, Motorola DSP96002 (clock 33.3MH)
z, floating point multiply-accumulate operation 60 ns), the port P1 is connected to the shared bus 8 via the internal bus 102, and the port P2 is connected via the internal bus 103 to the right port 106, the dual port memory 108, and It is connected to the left port 107 and the local memory 109.

The changeover switch 104 is provided in the middle of the internal bus 102 and switches connection / disconnection of the data path with the shared bus 8. Specifically, IFP10
The connection state is switched based on the interrupt processing of.

The shared local memory 105 is the signal processing device 1.
01 is connected to the internal bus 102 connecting the port P1 of 01 and the changeover switch 104.
When 04 is in the non-connection state, it is accessed at high speed by the signal processing device 101 in the PE, and when the changeover switch 104 is in the connection state, it is accessed by the signal processing device 101 in the IFP 10 or another PE.

The right port 106 and the left port 107 are
It is configured to be connectable to a connector (not shown) provided at the end of the local buses 15 to 19 so that the connection can be arbitrarily changed, and the connectors of the arbitrary local buses 15 to 19 are connected. Specifically, in FIG. 1, PE1
The left port 107 of No. 1 is connected to the other end of the local bus 15 whose one end is connected to the A / D converter 20.
One end of the local bus 16 is connected to 06. PE
The other end side of the local bus 16 is connected to the left port 107 of 12 and the one end side of the local bus 17 is connected to the right port 106. Local bus 1 at left port 107 of PE13
7 is connected to the other end side, and the local bus 1 is connected to the right port 106.
One end side of 8 is connected. Left port 10 of PE14
7, the other end of the local bus 18 is connected, and the right port 10
One end side of the local bus 19 whose other end side is connected to the D / A converter 21 is connected to 6. Also, the left port 107
As shown in FIG. 1, the A / D converter 20 and the D / A converter 21 are connected to the right port 106 and the local buses 15 and 19, respectively. As a result, the PE and the input / output device can be treated equivalently, and the data can be directly input / output without using the shared bus 8.

The dual port memory 108 is provided on the internal bus 103 connected to the left port 107.
This allows multiple PEs for one right port 106.
The left port 107 can be connected. The local memory 109 stores various data input via the left port 107 and the dual port memory 108, and this stored data is accessed by the signal processing device 101.

As described above, the present multi-signal processing system uses the PEs 11 to 14 and the host 1 as communication between PEs.
A shared bus system used to perform data transfer with the main unit and a general data transfer, and a local bus system used to perform signal processing according to a data flow that requires real-time processing. It has a lineage.

The connection form (configuration) of the local bus system is changed according to the flow of signals to be processed. As a connection form of the local bus system, for example, as shown in FIG. 3, pipeline connection ((a) in FIG. 3), broadcast connection ((b) in FIG. 3), ring connection ((c) in FIG. 3)
)and so on. As described above, the change of the connection form is made by connecting the connector physically attached to the end of the local bus and the right port 106 and the left port 10 of each PE 11-14.
7 by changing the connection with the connector.
The pipeline connection shown in (a) of FIG. 3 is similar to the connection form of FIG. 1, and is applicable to, for example, a case where a large amount of calculation is performed and a complicated calculation is performed. The broadcast connection shown in FIG. 3B is composed of a plurality of left ports 107 that can be connected to one right port 106 as described above. It becomes possible to simultaneously write in the local memories 109 of the PEs 12, 13, and 14, and it is applicable to calculation such as voice recognition. The ring connection shown in (c) of FIG. 3 is the right port 1 of the PE 14 located at both ends of the pipeline connection.
06 and the left port 108 of the PE 11 are connected by the local bus 22 so that the data flow has a ring shape, and is applicable to, for example, matrix operation.

Next, the operation of the above configuration will be described. In the local bus system, for example, the changeover switch 104 of each of the PEs 11 to 14 is controlled in the non-connection state. In this state, analog data output from an input / output device (not shown) is converted into digital data by the A / D converter 20,
It is input to the left port 107 of the PE 11 via the local bus 15 and written to the local memory 109 via the dual port memory 108. This data is used in the signal processing device 1
With 01, a predetermined process is performed according to a predetermined flow, and the result is output from the right port 106. The data output from the PE 11 is the local bus 1
It is input to the PE 12 of the next stage via 6 and written in the local memory 109. For this data, PE1
Similar to the case of 1, predetermined processing is performed according to a predetermined flow, and the result is output from the right port 106. Further, the above-described operation is sequentially performed in PE13 and PE14. The data output from the PE 14 is input to the D / A converter 21 via the local bus 19, converted into an analog signal, and output to a predetermined input / output device.

On the other hand, in the shared bus system, data transfer is performed in packet units, for example. That is, in the PEs 11 to 14, the packet to be transmitted is stored in the shared local memory 105 and the attention signal is transferred to the IFP 10. As a result, IFP10
Is interrupted, and the changeover switch 104 of the PE that has sent the attention signal is controlled to be in the connected state. Along with this, the packet stored in the shared local memory 105 is sent to the IFP 10. IFP10
Then, the transfer destination or the like of the input packet is decoded, and the packet is transferred to another PE or host 1 which is the transfer destination.

As described above, according to this embodiment,
In addition to having the signal processing device 101, a plurality of PEs 11 to 14 provided with at least two-system bus connection parts for the signal processing device 101 are provided, and each PE 11 to 14 and the shared memory 9 are connected by the shared bus 8. Each PE
11 to 14 are connected to each other by a local bus 16 or the like, and an interface between the host bus 2 and the shared bus 8 and each P
An IFP 10 for managing data transfer between Es is provided to configure a communication path of two systems of a shared bus system and a local bus system, and in the local bus system, the connection form can be arbitrarily changed by changing the connection of a connector. As a result, real-time input / output devices can be directly connected to the local bus system, and processing with a large amount of calculation such as voice recognition can be performed in real time.
Further, it is possible to realize a multi-signal processing system having a simple configuration, high flexibility, and capable of high-speed processing. Further, in the shared bus system, the presence of the IFP 10 makes it possible to realize packet transfer in which the PEs and the host 1 are integrated. Also, IFP
Since the host bus 2 and the shared bus 8 are separated by 10 and the interface between them is performed by the IFP 10, data transfer between PEs can be performed at high speed using the shared bus 8.

The shared bus 8 is provided to each PE 11-14.
A switch 104 for switching between connection and non-connection with the shared bus 8 is provided in a connection portion with the internal bus 10 between the signal processing device 101 and the switch 104.
Since the shared local memory 105 is provided in No. 2, the shared local memory 105 can be accessed by the signal processing device 101 at high speed by controlling the changeover switch 104 in the non-connection state. When the changeover switch 104 is in the connected state and directly connected to the shared bus 8, it may be involved in so-called arbitration with the shared bus 8 and access may take time.

A digital audio interface (DIF), for example, can be attached to each PE as an input / output device. As a result, it is possible to input / output an audio signal to / from a DAT or the like. In fact, in order to confirm the system performance and operation in this case, continuous DP
We performed word spotting by matching. Figure 4
Is the configuration diagram of the main part of the system in this case, and
Using five PE31-35 having the same configuration as E,
Right port 106 of PE31 and left port 107 of PE32
Is connected by a local bus 36, and the right port 106 of the PE 32 and the left port 107 of the PEs 33, 34, 35 are broadcast-connected by a local bus 37, a DIF is attached to the PE 31, and a sampling frequency of 4 from the DAT 38.
The system was configured to input 8 kHz data.

In the configuration of FIG. 4, DAT 38 through P
Data having a sampling frequency of 48 kHz is input to E31. In PE31, the input data is 12 kHz
And is sampled into the PE 32 via the local bus 16. In the PE 32, the signal processing apparatus 101 detects the voice section and calculates the 12th-order LPC cepstrum, and the result is transmitted via the local bus 37 to the PE.
Broadcast to 33, 34, and 35. In this case, the frame period is 10.7 msec and the frame length is 2
It took 1.3 msec. In each of the PEs 33, 34, and 35, continuous DP matching is performed in each signal processing apparatus 101, and processing is performed on different reference words, and the one that has detected the minimum distance point is the shared local memory 105 as a word candidate. Stored in. The word candidates thus obtained are stored in the IFP 10 from each shared local memory 105.
Is transferred to the workstation as the host 1 via. As a result of the above processing, about 18 words (average length 50 frames) could be processed in real time by one PE. This is a workstation, such as Sony's NWS3870, 25 MIPS with about 1.
It was four times.

In this embodiment, a 2-port DSP is used as the signal processing apparatus 101, but the signal processing apparatus 101 is not limited to this. For example, as shown in FIG. 5, a 1-port DSP may be used. The same effect as described above can be obtained. In this case, a changeover switch (S) that divides the shared local memory 105 and the local memory 109 into a connection portion between the internal bus 102 on the shared bus side and the internal bus 103 on the local bus side is provided.
W) 110 is preferably provided. Further, instead of the dual port memory provided in PE, for example, FIF
O can be used.

Further, the IFP and the plurality of PEs are regarded as one cluster, and the plurality of clusters are connected to an external bus, for example, VME.
It is also possible to extend the system by connecting to a bus and connecting different clusters with a local bus.

[0031]

As described above, according to the present invention, since the two communication paths of the shared bus system and the local bus system are constructed, real-time input / output devices can be directly connected to the local bus system. It is possible to realize a multi-signal processing system that can perform a large amount of calculation processing such as voice recognition in real time, and that has a simple configuration and has a high degree of freedom and high-speed processing. Further, in the shared bus system, the presence of the interface circuit makes it possible to realize packet transfer in which the signal processing element and the host computer are integrated. Further, since the external bus and the shared bus are separated by the interface circuit and the interface between them is performed by the interface circuit, data transfer between the signal processing elements can be performed at high speed by using the shared bus.

Further, the signal processing element is provided with a switching means for switching connection / non-connection with the shared bus at a connection portion with the shared bus, and a shared local memory is provided between the signal processing device and the switching means. Since the shared local memory is provided, the signal processing device can access the shared local memory at high speed when the switching unit is in the disconnected state. Further, in the local bus (second bus) system, the connection form can be arbitrarily changed, so that the system according to the processing can be easily configured.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a multi-signal processing system according to the present invention.

FIG. 2 is a diagram showing a configuration example of a signal processing element according to the present invention.

FIG. 3 is a diagram showing a connection form example of a local bus system according to the present invention.

FIG. 4 is a diagram for explaining an operation example at the time of broadcast connection.

FIG. 5 is a diagram showing another configuration example of the signal processing element according to the present invention.

FIG. 6 is a configuration diagram of a general multi-signal processing system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Host computer (host) 2 ... Host bus 8 ... Shared bus 9 ... Shared memory 10 ... Interface processor (IFP) 11, 12, 13, 14, 31, 32, 33, 34, 3
5 ... Signal processing element (PE) 101 ... Signal processing device 104 ... Changeover switch (SW) 105 ... Shared local memory 106 ... Right port 107 ... Left port 108 ... Dual port memory 109 ... Local memory 110 ... Changeover switch (SW) 15 , 16, 17, 18, 19, 22, 36, 37 ... Local bus 20 ... Analog / digital (A / D) converter 21 ... Digital / analog (D / A) converter 38 ... DAT

Claims (3)

[Claims] 1. A plurality of signal processing elements having a signal processing device, comprising at least two system bus connection parts for the signal processing device, a shared memory shared by the plurality of signal processing elements, and each signal. A shared bus that connects the processing elements and the shared memory, an interface circuit that performs interface processing between the external bus and the shared bus and data transfer between the signal processing elements, and a local bus that connects the signal processing elements to each other. Each of the signal processing elements is configured to be connected to the interface circuit via the shared bus and to be connected to another adjacent signal processing element via the local bus. And multi-signal processing system. 2. The signal processing element is connected to a connection part with a shared bus, a switching means for switching connection / disconnection with the shared bus, and a bus connection part between the signal processing device and the switching means. And a shared local memory that can be shared by the signal processing devices of the respective signal processing elements via the shared bus, and the shared local memory can be used for other signal processing through the shared bus when the switching means is in the connected state. The multi-signal processing system according to claim 1, wherein the multi-signal processing system is also accessed by the signal processing device of the element, and is accessed only by the signal processing device of the signal processing element when the switching means is in the non-connection state. 3. A first internal bus and a second circuit for connecting the signal processing device to a communication path of two systems consisting of at least a first bus and a second bus.
A signal processing element having a first internal bus, the switching means being provided on the first internal bus for switching connection / disconnection with the first bus; and a signal processing device between the signal processing device and the switching means. A signal processing element, comprising: a shared local memory connected to one internal bus; and at least one port connected to the second internal bus and connected to the second bus.