JP2000112881A - High-speed arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed arithmetic unit capable of simultaneously executing the storage of input data and the reading of a stored operation result during the arithmetic operation of an operation part and accessing devices in a wide range with a simple constitution by individually applying the storage of input data, the storage of an operation result of input data and the reading of the stored operation result at least to three shared memories or multi-port memories. SOLUTION: One of shared memories 1-1 to 1-3 cyclicly executes a 1st stage for storing input data by connecting the shared memory itself to an input control part 4, a 2nd stage for performing an arithmetic operation and storing the operation result by connecting itself to an operation part 3 and a 3rd stage for outputting the operation result by connecting itself to an output control part 5. Since the other shared memories cyclicly execute the 1st to 3rd stages temporally shifted states, three shared memories are driven on respectively different stages at the same time. The operation part 3 instructs the cyclic connection switching to the bus connection control part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed operation device, and more particularly to a high-speed operation device suitable for application to a communication protocol processor or the like for performing a predetermined operation on digital signals at a high speed.

[0002]

2. Description of the Related Art A communication protocol processor and a general-purpose microcomputer, which are known as a series of devices that perform predetermined digital signal processing (for example, filtering) on input data and then output the processed data, include an arithmetic unit (central processing unit). Apparatus: A serial port, a memory connection port, a timer, a DMAC (direct memory access controller), and the like are built in, mainly a CPU (hereinafter abbreviated as CPU). In such communication protocol processors and general-purpose microcomputers, it is desired to increase the speed of arithmetic processing.

In such a communication protocol processor or general-purpose microcomputer, when data is externally DMA-transferred to a memory, the right to use the bus is set to DMA.
C, and the CPU has no right to use the bus.
Cannot access the memory, and cannot perform communication protocol processing or the like by the CPU. However, a high-speed operation device that realizes high-speed operation utilizing this fact has been disclosed (Japanese Patent Laid-Open No. 7-121500).

In this conventional high-speed processing device, a bus is divided by a bus switch circuit, so that a memory access path by a CPU and a DMAC transfer control path by a DMAC are formed separately, whereby parallel operation of the CPU and the DMAC is performed. High-speed operation is performed by making it possible.

[0005] A high-speed arithmetic unit having two system buses, a memory connected to one of the system buses, and a DMA transfer between the two system buses is also known (Japanese Patent Laid-Open No. 5-205). No. 307597).

[0006]

However, in the former conventional high-speed processing device in which the bus is divided by the bus switch circuit to enable the parallel operation of the CPU and the DMAC, the parallel operation has a limit, and the CPU has no access. There is a problem that the devices that can be used are limited to random access memory (RAM) and read only memory (ROM). Further, the latter conventional high-speed arithmetic device having two system buses has a limited use and is not versatile.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a high-speed arithmetic device that can access a wide range of devices with a simple configuration.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides N (N) which can be individually written and read.
Is an integer of 3 or more), a bus connection control unit that selectively connects the N shared memories with the bus,
An input control unit that externally transfers and stores data in accordance with an input instruction in a first shared memory connected via a bus connection control unit among the N shared memories; A predetermined operation is performed on the data read from the second shared memory connected via the control unit, the operation result is written into the second shared memory, and an instruction is issued to each unit in the apparatus. An arithmetic unit, and an output control unit that reads data from the third shared memory connected via the bus connection control unit among the N shared memories according to an output instruction and transfers the data to the outside; Sets the second shared memory connected to the operation unit to the first shared memory previously connected to the input control unit, and sets the third shared memory connected to the output control unit to the first shared memory The first connected to From among the N shared memories so that the first shared memory connected to the input control unit is the third shared memory previously connected to the output control unit. The connection is instructed to the bus connection control unit, an input instruction is issued to the input control unit, and an output instruction is issued to the output control unit.

According to the present invention, the storage of the input data, the storage of the operation result of the input data, and the reading of the stored operation result can be performed separately for at least three shared memories. During operation, input data can be stored and stored operation results can be read.

In order to achieve the above object, the present invention instructs an arithmetic unit to connect a shared memory from N shared memories to an input control unit to a bus connection control unit, and A first stage that issues an input instruction and transfers data from the outside, and instructs a bus connection control unit to connect the one shared memory and the arithmetic unit to a predetermined stage for data from the one shared memory. A second stage of performing the operation of the above, and storing the operation result in the one shared memory;
A third stage for instructing the bus connection control unit to connect the one shared memory to the output control unit, issuing an output instruction, and transferring an operation result stored in the one shared memory to the outside; Is performed cyclically, and the first to third stages are similarly performed cyclically for shared memories other than one shared memory, and different stages are executed at the same time. It is something to do.

According to the present invention, when attention is paid to one of the N shared memories, the first of the input data storage is stored.
, A second stage for storing the operation and the result of the operation, and a third stage for outputting the operation result are performed cyclically, and the other shared memories are shifted in time from the first to the above. Since the third stage is performed cyclically, each of the three shared memories is operated at a different stage at the same time.

Further, in order to achieve the above object, the present invention provides an M (M is an integer of 3 or more) multiport memory having three or more write / read ports, and a first write / read port, respectively. M connected to
An input control unit for externally transferring and storing data in accordance with an input instruction in a first multi-port memory of the plurality of multi-port memories; and M multi-port memories respectively connected to a second write / read port An arithmetic unit that performs a predetermined operation on data read from the second multiport memory of the memory, writes the operation result in the second multiport memory, and issues an instruction to each unit in the device; An operation control unit for reading data from the third multiport memory among the M multiport memories connected to the third write / read port and transferring the data to the outside according to an output instruction; Sets the second multi-port memory connected to the arithmetic unit to the first multi-port memory previously connected to the input control unit. The third multi-port memory connected to the output control unit and the second multi-port memory connected to the arithmetic unit before that, first connected to the input control unit
In order to make the multi-port memory of the third multi-port memory the third multi-port memory previously connected to the output control unit, the M multi-port memories are cyclically switched and connected, and an input instruction is issued to the input control unit. And an output instruction to the output control unit.

According to the present invention, the multi-port memory is used instead of the shared memory to store the input data, store the operation result of the input data, and read out the stored operation result separately, so that the operation of the operation unit can be performed. It can store input data and read out the stored operation results.

According to the present invention, in order to achieve the above object, an arithmetic unit issues an input instruction to an input control unit and externally transfers data to one of the M multiport memories. A first stage to perform a predetermined operation on the data from the one multi-port memory, store the operation result in the one multi-port memory, and output an instruction to the output control unit. And the third stage of transferring the operation result stored in the one multi-port memory to the outside is carried out cyclically, and the same applies to the multi-port memories other than the one multi-port memory. The first to third stages are controlled cyclically, and at the same time, different stages are controlled to be executed.

According to the present invention, the first stage for storing input data, the second stage for storing operation and operation results, and the third stage for outputting operation results for one multiport memory are cyclic. In the other multi-port memories, the first to third stages are performed cyclically with a time lag, so that at the same time, each of the three multi-port memories operates at a different stage. Is done.

Further, in the present invention, an input / output control unit may be used instead of the input control unit and the output control unit. The present invention cannot execute the input operation and the output operation in parallel, but is effective when the operation time for the input / output time is relatively long.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of the high-speed operation device according to the present invention. In FIG. 1, shared memories 1-1, 1-2, and 1-3 are connected to a bus connection control unit 2 via a bus 11 such as a data bus and an address bus. , The input control unit 4 and the output control unit 5 via a bus 12 such as a data bus and an address bus. Shared memory 1-
Reference numerals 1, 1-2, and 1-3 denote general RAMs, each having a write / read (R / W) control signal, a data bus, an address bus, and the like (chip select, write clock, etc.) independently. (Ie, writing and reading can be performed separately). Here, the shared memory is divided into three, but the present invention is not limited to this.

The operation unit 3 is connected to the bus connection control unit 2, and the operation unit 3, the input control unit 4 and the output control unit 5 are connected to any of the shared memories 1-1, 1-2 and 1-3. To indicate. According to the instruction, the bus connection control unit 2 sends, for example, the arithmetic unit 3 and the shared memory 1-1, the input control unit 4 and the shared memory 1-2, the output control unit 5 and the shared memory 1-3.
A predetermined signal group is connected.

Further, the arithmetic unit 3 issues an input instruction 7 to the input control unit 4, issues an output instruction 8 to the output control unit 5, and performs a desired operation on the connected shared memory. Calculation performed by the calculation unit 3 and the bus connection control unit 2;
A series of operations for giving instructions to the input control unit 4 and the output control unit 5 are performed according to a program stored in a ROM (or RAM or the like) 10 connected via a local bus 9 included in the arithmetic unit 3.

It should be noted that the input control unit 4 and the output control unit 5
It may be in the form of a MAC. For example, for an input instruction,
A transfer source address of an external device (not shown), a transfer destination address of a connected shared memory, and a transfer data number are indicated.

Next, the operation of the embodiment shown in FIG.
This will be described with reference to the flowchart of FIG. 2 and the schematic diagram for explaining the operation of FIG. In the following flowcharts, the shared memories 1-1, 1-2, and 1-3 are also referred to as and for convenience. In addition, here, an input end signal indicating that the input has ended and an output end signal indicating that the output has ended are used. For example, when the time required for the operation is longer than the input operation or the output operation, these are used. Need not be used (the step of confirming termination can be omitted).

First, the bus connection control unit 2 is instructed to connect the input control unit 4 and the shared memory 1-1 () (step 101). Subsequently, an input instruction 7 is issued to the input control unit 4 (step 102). As a result, the data to be calculated, which is input from the outside, is input to the input control unit 4, and the data to be calculated is further stored in the shared memory 1-1 () via the bus connection control unit 2 in FIG. To I
1 is stored as schematically shown. And the calculation unit 3
Monitors whether an input end signal has been input from the input control unit 4 (step 103).

When the data input to the input control unit 4 is completed, an input end signal is output from the input control unit 4 to the operation unit 3, whereby the operation unit 3 is connected to the input control unit 4 and the shared memory 1-2 (). And the arithmetic unit 3 and the shared memory 1
-1 () is instructed to the bus connection control unit 2 (step 104).

Next, the arithmetic unit 3 issues the input instruction 7 again to the input control unit 4 (step 105), and executes the arithmetic processing (step 106). As a result, the data to be calculated, which is input from the outside, is input to the input control unit 4, and is further transmitted to the shared memory 1-2 via the bus connection control unit 2.
The data to be calculated is stored in () as schematically shown by I2 in FIG. 3B, and the calculation unit 3 is input from the shared memory 1-1 () via the bus connection control unit 2. Start calculating data.

The arithmetic unit 3 monitors whether an input end signal has been input from the input control unit 4 even during the execution of the arithmetic operation (step 107). Normally, before the input of data to the input control unit 4 ends and before the input control unit 4 outputs an input end signal to the operation unit 3, the operation by the operation unit 3 ends, and the operation result is transferred to the bus connection control. It is stored in the shared memory 1-1 () via the section 2 and has been completed. The above operation and the operation of storing the operation result in the shared memory 1-1 () are shown in FIG.
(A) schematically shows P1.

When the input end signal is input from the input control unit 4, the arithmetic unit 3 turns to the input control unit 4 and the shared memory 1.
-3 (), the arithmetic unit 3 and the shared memory 1-2.
(), Output control unit 5 and shared memory 1-1.
The bus connection control unit 2 is instructed to connect () (step 108).

Subsequently, the operation unit 3 issues an input instruction 7 to the input control unit 4 and an output instruction 8 to the output control unit 5 (step 109), and executes the operation (step 110).
In response to the input instruction 7, data to be calculated from the outside is input to the input control unit 4, and further data to be calculated in the shared memory 1-3 () via the bus connection control unit 2 is shown in FIG. C), the output control unit 5 stores the shared memory 1-1 via the bus connection control unit 2 in response to the output instruction 8.
The data stored in (), that is, the calculation result, is transferred to the outside as schematically shown by O1 in FIG. 3A, and an output end signal is issued to the calculation unit 3 when the transfer is completed.

In parallel with the input control operation of the input control unit 4 and the output control operation of the output control unit 5,
Starts the operation of the data input from the shared memory 1-2 () via the bus connection control unit 2, and calculates the operation result before the input end signal is output from the input control unit 4 to the operation unit 3. Is completed, and the calculation result is stored in the shared memory 1-2 () via the bus connection control unit 2. The above operation and the operation of storing the operation result in the shared memory 1-2 () are schematically shown by P2 in FIG.

The operation unit 3 monitors whether an input end signal has been input from the input control unit 4 and whether an output end signal has been input from the output control unit 5 even during the execution of this operation (step 111). When it is confirmed that an input end signal has been input from the input control unit 4 to the arithmetic unit 3 and that an output end signal has been input from the output control unit 5, the input control unit 4 and the shared memory 1-1 () are now connected. The bus connection control unit 2 connects the arithmetic unit 3 and the shared memory 1-3 (), and connects the output control unit 5 and the shared memory 1-2 ().
(Step 108).

Thereafter, the processing of steps 109, 110, 111 and 108 is repeated. However, step 10
In step 8, the shared memory to be connected is designated cyclically.
It goes without saying that the arithmetic processing performed in 10 is also the corresponding shared memory. The shared memory to be connected for the second and subsequent times in step 108 is shown on the right side of step 108 in FIG. 2, and the top in the vertical direction is a value indicating what number the step 108 was activated. The third from the top indicates the shared memory connected to the input control unit 4, the third from the top indicates the shared memory connected to the arithmetic unit 3, and the bottom indicates the shared memory connected to the output control unit 5.

As a result, as schematically shown in FIG.
An operation of storing data in the shared memory by the input control unit 4,
Predetermined arithmetic processing and arithmetic result storage processing for the data stored in the shared memory in the previous step by the arithmetic unit 3 and transfer operation of the arithmetic result stored in the shared memory in the previous step to the outside by the output control unit 5 Are performed in parallel, so that high-speed operation can be performed.

Next, the effectiveness of this embodiment will be shown using specific numerical values. As the input data, two sets of 16-bit data having 1024 data numbers are input, ie, 1 set.
A case where 2048 pieces of 6-bit data are transferred will be described as an example. For fast input, combine the two sets into one
1024 data bits are transferred. Set transfer clock to 100
When the frequency is set to MHz (10 ns), the transfer is completed in 10.24 μs. The output also operates at 100 MHz,
The transfer is completed in 0.24 μs.

Assuming that the operation time is equivalent to that in such a case, the operation is 1 in consideration of a high-speed processor.
Assuming that each operation (instruction) (instruction) takes 5 ns, approximately 2048 operations (instructions) can be executed, and data of 3.2 Gbps (= 1024 × 16)
× 2 bits / 10.24 μs).

Conventionally, the ratio of the total calculation time to the total calculation time is large, and the time required for data input / output is negligible. However, as can be seen from the above example, a high-speed processor has appeared with the advance of the semiconductor technology, and it has become possible to execute about 5 ns per instruction. Of course,
The time required for input and output has become relatively long and cannot be ignored. If this embodiment is not used, the performance of the high-speed processor portion cannot be sufficiently exhibited, and in the above example, the result is that only 1/3 of the performance can be obtained as a whole. With the structure described above, a high-speed arithmetic circuit or a semiconductor integrated circuit is realized.

In the above description, an example has been shown in which input data is input in predetermined units (blocks) and arithmetic operations are performed. However, the arithmetic operation (digital signal processing) is not limited to block units. This is also effective when the digital data is used to filter the sampled data of the time signal. At this time, input / output of data is handled in a predetermined block unit. Regarding calculation, if information between blocks is required, it may be stored in a RAM or the like connected to a local bus.

As a modification of this embodiment, the arithmetic unit 3
And two shared memories.
This is effective when the desired digital operation processing time is about twice as long as the data input / output time. Focusing on a specific shared memory, stage 1 as an input operation, stage 2 as an operation 1, stage 3 as an operation 2 and stage 4 as an output operation are cyclically repeated. This modification can be easily developed from the first embodiment.

As another modified example of the first embodiment, the structure of the first embodiment is simplified, and a function of performing input and output is provided instead of the input control unit 4 and the output control unit 5. A configuration including an input / output control unit is conceivable. In this case, the input operation and the output operation cannot be performed in parallel, but this is an effective configuration when the calculation time for the input / output time is relatively long.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a second embodiment of the high-speed operation device according to the present invention. The high-speed operation device shown in FIG. 1 includes an operation unit 20, multiport memories 21-1, 21-2, and 21-3 having three ports, an input control unit 22, and an output control unit 23. .

Multiport memories 21-1 to 21-3
Is a general 3-port multi-port memory, and R
/ W control signal, a data bus, an address bus, and others (such as a chip select and a write clock) independently (three multi-port memory configurations are shown in the figure). The first ports of the multiport memories 21-1 to 21-3 are connected to the input control unit 22, the second port is connected to the operation unit 20, and the third port is connected to the output port. It is connected to the control unit 23.

The processor 20 issues an input instruction 24 to the input controller 22, issues an output instruction 25 to the output controller 23, and performs a desired operation on data from a desired multiport memory. It is. A series of operations performed by the arithmetic unit 20 and instructing the input control unit 22 and the output control unit 23 are performed by the ROM (or RAM or the like) 2 connected to the local bus 26 of the arithmetic unit 20.
7 is executed in accordance with the program stored in.

The input control unit 22 externally transfers data to a desired multi-port memory in accordance with an input instruction, and issues an input end signal to the arithmetic unit 20 when the transfer is completed. The output control unit 23 transfers data from a desired multiport memory to the outside in accordance with the output instruction, and issues an output end signal to the arithmetic unit 20 when the transfer is completed.

The input control unit 22 and the output control unit 23
May be in the form of a DMAC. For example, regarding the input instruction, a transfer source address of an external device (not shown), a transfer destination address of a connected multiport memory,
Indicates the number of data to be transferred.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. Here, an input end signal indicating that the input has been completed and an output end signal indicating that the output has been completed are used. However, as in the embodiment of FIG. If it is longer than the output operation, there is no need to use these signals (the step of confirming termination can be omitted).

First, the arithmetic unit 20 issues an input instruction 24 and sends a multi-port memory 21-1 to the input control unit 22.
Is instructed to transfer data (step 201).
As a result, the data to be calculated, which is input from the outside, is input to the input control unit 22, and is further transferred and stored in the multiport memory 21-1. Then, the arithmetic unit 20 monitors whether an input end signal has been input from the input control unit 22 (step 202).

When data input to the input control unit 22 is completed, an input end signal is output from the input control unit 22 to the calculation unit 20, whereby the calculation unit 20 issues an input instruction 24 and Multi-port memory 21-2
Is instructed to transfer data (step 203).
As a result, the data to be calculated, which is input from the outside, is input to the input control unit 22, and is further transferred and stored in the multiport memory 21-2.

Next, the arithmetic section 20 performs a predetermined arithmetic processing on the data stored in the multiport memory 21-1, and stores the arithmetic result in the multiport memory 21-1 again (step 204). . Subsequently, the input control unit 2
2 and waits until the input is completed (step 205). When an input end signal is output from the input control unit 22 to the arithmetic unit 20, the arithmetic unit 20 issues an input instruction 24 again and instructs the input control unit 22 to transfer data to the multiport memory 21-3. Along with
An output instruction 25 is issued to the output control unit 23 to instruct to transfer data from the multiport memory 21-1 to the outside (step 206).

As a result, the data to be calculated, which is input from the outside, is input to the input control unit 22, and is further transferred and stored in the multiport memory 21-3. The stored operation result is read by the output control unit 23 and transferred to the outside.

Next, the operation unit 20 performs a predetermined operation on the data stored in the multiport memory 21-2, and stores the operation result in the multiport memory 21-2 again (step 207). . Subsequently, the input control unit 2
2 and waits until the input is completed, and monitors the output end signal from the output control unit 23 to wait for the output to divert (step 208).

When the operation unit 20 confirms that the input of the input control unit 22 has been completed and also confirms that the output of the output control unit 23 has been completed, the process returns to step 206 again.
Steps 06 to 209 are repeated. However, step 20
Needless to say, the multiport memory specified in 6 is cyclically specified, and the multiport memory specified in step 207 is also specified cyclically.

Thus, the operation of storing data in the multiport memory by the input control unit 22 and the operation of the arithmetic unit 2 on the data stored in the multiport memory in the previous step are performed.
The predetermined operation processing and the operation result storage processing by 0 and the operation of transferring the operation result stored in the multiport memory in the previous step to the outside by the output control unit 23 are performed in parallel, so that high-speed operation is possible. Becomes

In this embodiment, an example has been shown in which input data is input in a predetermined unit (block) and operated. However, the operation (digital signal processing) is not limited to a block unit. For example, the present invention is also effective in a case where sample data of a continuously input time signal is filtered by a digital filter. At this time, input / output of data is handled in a predetermined block unit. Regarding calculation, if information between blocks is required, it may be stored in a RAM or the like connected to a local bus.

Next, the effectiveness of the operation will be shown using specific numerical values. As in the first embodiment, two sets of 16-bit data having 1024 data are input as input data.
A case where 048 data is transferred is taken as an example. For high-speed input, two sets are combined into one, and 1024 pieces are transferred with a 32-bit length. When the transfer clock is 100 MHz (10 ns), the transfer is completed in 10.24 μs. Similarly, the output is operated at 100 MHz, and the transfer is completed in 10.24 μs.

Assuming that the operation time is equivalent to that in such a case, the operation is 1 in consideration of a high-speed processor.
Assuming that each operation (instruction) (instruction) takes 5 ns, approximately 2048 operations (instructions) can be executed, and data of 3.2 Gbps (= 1024 × 16)
(* 2 bits / 10.24 μs), it is possible to implement an arithmetic circuit or a semiconductor integrated circuit that is faster than the conventional one, as in the first embodiment.

As a modification of the second embodiment, a mode in which two arithmetic units 20 and four multi-port memories 21 are provided can be considered. This is effective when the desired digital operation processing time is about twice as long as the data input / output time. Focusing on a specific multiport memory, stage 1 which is an input operation, stage 2 which is an operation 1, stage 3 which is an operation 2 and stage 4 which is an output operation are cyclically repeated. An example of such an application is
The embodiment can be easily developed.

FIG. 6 is a block diagram of a third embodiment of the high-speed operation device according to the present invention. The third embodiment simplifies the configuration of the second embodiment, and the input control unit 22
And an input / output control unit 28 instead of the output control unit 23. The input / output control unit 28 has a function of performing input and output. In this case, the input operation and the output operation cannot be performed in parallel, but this is an effective configuration when the calculation time for the input / output time is relatively long. The number of ports of the multiport memories 21-1 and 21-2 may be two.

The present invention can have a configuration other than the above-described embodiment and modified examples. For example, as for the types of bus signal lines (ports) of the multi-port memory, an embodiment using a FIFO memory in addition to a general signal line group can be considered. In this case, the number of signal lines can be reduced and the circuit scale can be reduced, so that the cost can be reduced.

More specifically, since various operation processes are performed between the operation unit 20 and the multiport memories 21-1 to 21-3 (21-1 and 21-2 in FIG. 6), data can be randomly accessed. There must be. In this case, for example, control signals such as a select signal, a write signal, a read signal, an output enable signal and a data signal line,
An address signal line or the like is required (a signal line used in a normal RAM or the like).

The input control unit 22, the output control unit 23 (or the input / output control unit 28) and the multiport memories 21-1 to 21-1
It is not necessary to randomly access data between 21-3 (21-1 and 21-2 in FIG. 6), and it is only necessary to be able to put data in and out in order. In this case, for example, a control signal such as a select signal, a write signal, a read signal, and an output enable signal and a data signal line may be provided, and an address signal line is not required (a signal line used in a FIFO memory). Therefore, it is not necessary to prepare an address signal line only for a port connected to the operation unit 20 and to prepare an address signal line for a port connected to the input control unit 22, the output control unit 23, or the input / output control unit 28.

[0059]

As described above, according to the present invention,
By separately storing at least three input memories, storing the operation results of the input data, and reading out the stored operation results for at least three shared memories or multiport memories, the input data can be stored during the operation of the operation unit. Can be stored and the operation results stored can be read, so that the input and output operations of data do not deprive the bus of the right to operate, and the operation unit (CPU) can sufficiently exhibit its performance. it can.

Further, according to the present invention, at the same time, three or two shared memories or multiport memories are operated at different stages (storage of input data, calculation and storage of calculation results, output of data). So that
At least three memory access operations can be performed in parallel, the overall throughput can be improved, and a high-speed arithmetic device with a simple configuration can be provided.

Further, according to the present invention, the device that can be accessed by the arithmetic unit is not limited to the ROM (or RAM).
A shared memory or a multiport memory, an input control unit, an output control unit, an input / output control unit, and the like can also be accessed. Further, according to the present invention, since it is constituted by a digital circuit, the present invention can be applied to a semiconductor integrated circuit, and can be applied to a communication protocol processor, a DSP (digital signal processor) and the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a high-speed operation device of the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG. 1;

FIG. 3 is an explanatory diagram of a state of a shared memory in FIG. 1;

FIG. 4 is a configuration diagram of a second embodiment of the high-speed operation device of the present invention.

FIG. 5 is a flowchart for explaining the operation of FIG. 4;

FIG. 6 is a configuration diagram of a high-speed operation device according to a third embodiment of the present invention.

[Explanation of symbols]

1-1, 1-2, 1-3 Shared memory 2 Bus connection control unit 3, 20 Operation unit 4, 22 Input control unit 5, 23 Output control unit 7 Input instruction to input control unit 8 Output instruction to output control unit 9 , 26 Local bus 10 Read-only memory (ROM) for storing programs 21-1, 21-2, 21-3 Multiport memory 27 Read-only memory (ROM) 28 I / O controller

Claims (6)

[Claims] 1. A shared memory divided into N pieces (N is an integer of 3 or more) that can be individually written and read, a bus connection control section that selectively connects to the N pieces of shared memories by a bus, An input control unit that externally transfers and stores data according to an input instruction in a first shared memory connected via the bus connection control unit, among the N shared memories, and the N shared memories A predetermined operation is performed on the data read from the second shared memory connected via the bus connection control unit, and the operation result is written into the second shared memory; An operation unit for issuing an instruction to each unit; and an output control unit for reading data from a third shared memory connected via the bus connection control unit among the N shared memories in accordance with an output instruction and transferring the data to the outside When The arithmetic unit includes the second shared memory connected to the arithmetic unit as the first shared memory previously connected to the input control unit, and the second shared memory connected to the output control unit. The third shared memory is a second shared memory previously connected to the arithmetic unit, and the first shared memory connected to the input control unit is the second shared memory previously connected to the output control unit. The N shared memory is used as a third shared memory.
And instructing the bus connection control unit to perform a cyclic switching connection from among the shared memories, issuing the input instruction to the input control unit, and issuing the output instruction to the output control unit. High-speed computing device. 2. The arithmetic unit instructs the bus connection control unit to connect one of the N shared memories to the input control unit and issues the input instruction. A first stage for transferring data from the outside, and instructing the bus connection control unit to connect the one shared memory and the operation unit to perform a predetermined operation on the data from the one shared memory. A second stage for storing the operation result in the one shared memory, and instructing the bus connection control unit to connect the one shared memory to the output control unit, and issuing the output instruction. And a third stage of transferring the operation result stored in the one shared memory to the outside. The third stage is performed cyclically, and the first through the third stages are similarly performed for shared memories other than the one shared memory. Third
2. The high-speed operation apparatus according to claim 1, wherein the control is performed so as to cyclically execute the stages and execute different stages at the same time. 3. A shared memory divided into two or more units that can be individually written and read, a bus connection control unit selectively connected to the shared memory via a bus, and a bus connection control unit connected via the bus connection control unit. An input / output control unit that transfers data from the outside in accordance with an input instruction and stores the data in accordance with an input instruction, and transfers the stored data to the outside in accordance with an output instruction; An operation unit for executing a predetermined operation on the data read from the second shared memory, writing the operation result in the second shared memory, and issuing an instruction to each unit in the device; The unit instructs the bus connection control unit to perform a cyclic switching connection of the two or more shared memories, and issues one of the input instruction and the output instruction to the input / output control unit. High-speed computing device. 4. A multiport memory having M (M is an integer of 3 or more) multiport memories having three or more write / read ports, and the M multiport memories connected to the first write / read ports, respectively. An input control unit for externally transferring and storing data in accordance with an input instruction in a first multiport memory; and an input control unit of the M multiport memories connected to a second write / read port, respectively. A predetermined operation is performed on the data read from the second multiport memory, the operation result is written in the second multiport memory, and an operation unit that issues an instruction to each unit in the apparatus is provided. According to an output instruction from a third multiport memory among the M multiport memories connected to the write / read port, An output control unit that reads data and transfers the read data to the outside, wherein the arithmetic unit is configured to store the second multiport memory connected to the arithmetic unit with the first multiport memory previously connected to the input control unit. And the third multiport memory connected to the output control unit is a second multiport memory previously connected to the arithmetic unit, and the third multiport memory connected to the input control unit is The M multi-port memories are cyclically switched so that one multi-port memory is the third multi-port memory previously connected to the output control unit. Wherein the input instruction is issued to the control unit and the output instruction is issued to the output control unit. 5. A first stage for issuing the input instruction to the input control unit and externally transferring data to one of the M multiport memories, and A second stage for performing a predetermined operation on the data from the one multiport memory and storing the operation result in the one multiport memory; and issuing the output instruction to the output control unit to output the one And a third stage for transferring the operation result stored in the multiport memory to the outside. The third stage is similarly performed for the multiport memories other than the one multiport memory. 5. The high-speed arithmetic device according to claim 4, wherein control is performed so as to cyclically execute the third to third stages and to execute different stages at the same time. 6. A plurality of multi-port memories having two or more write / read ports, and a first multi-port memory of the plurality of multi-port memories connected to the first write / read port, respectively. An input / output control unit for externally transferring and storing data in accordance with an input instruction, and transferring stored data to an external unit in accordance with an output instruction; and an input / output control unit of the plurality of multi-port memories respectively connected to a second write / read port An arithmetic unit for performing a predetermined operation on the data read from the second multiport memory, writing the operation result to the second multiport memory, and issuing an instruction to each unit in the device; The arithmetic unit cyclically switches between the plurality of multi-port memories, and inputs and outputs the input instruction to the input / output control unit. Fast arithmetic apparatus characterized by emitting one of the output instruction.