JP2005286277A - Semiconductor integrated circuit and method for developing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for developing a semiconductor integrated circuit with which an interface speed can be easily set for each port to a multi-port. <P>SOLUTION: In a method for developing a semiconductor integrated circuit including a memory in one of on-chip circuit modules, in individual memory design, a memory array (11), a memory logic circuit (14) for performing logic operation for accessing the memory array and memory interface circuits (16, 17, 18) are designed, and a plurality of access ports are comprised of the memory logic circuit and the memory interface circuits. In individual access port design, a plurality of standard cells having the same circuit configuration and the equal arrangement area are used for each kind, and the difference among operating speeds of the plurality of access ports is set by the difference in the operating speed of the same kind of standard cells. Even if interface specifications of the access ports are made individual, man-hour for design can be reduced and an interface speed can be easily set neither too much nor too little for a requested specification. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit having a memory unit and a method for developing the same, and more particularly to a design technique that enables a required speed to be set in an access port of a memory unit, for example, a small memory mounted in a logic LSI such as a microcomputer. The present invention relates to a technology effective when applied to a multiport memory having a large capacity.

  Patent Document 1 describes a multi-port memory that controls the operation speed for each port, and the speed control is performed by switching the threshold voltage of the transistor. Patent Document 2 describes a multi-port memory that controls the speed of a read / write port in accordance with the application, and the speed control is performed based on the magnitude of the current drive capability of the transistors constituting the port.

JP 09-198870 A (FIG. 1)

JP 05-2558569 A (FIG. 1)

  The inventor has studied a design method for setting a required operation speed for each port of a multi-port memory on-chip in a logic LSI. In particular, the present inventor is used in a distributed manner at several locations on a logic LSI, such as a buffer between an internal bus and a logic circuit of a semiconductor integrated circuit and a buffer between an external interface circuit and an internal logic circuit. A relatively small multi-port memory was studied. In such a multi-port memory, the interface speed corresponding to the interface object must be set. This interface speed is usually set by individual design for each circuit module after logic design. In short, individual multi-port memories satisfying such specifications are prepared as macro parts. However, the interface speed depends on the type of the logic LSI on which the multiport memory is mounted, and also on the use of the multiport memory inside the logic LSI, so the entire multiport memory is designed for each required specification. It has been found by the present inventor that the design time and cost increase if a plurality of multiport memories are prepared as necessary macro parts. In addition, the placement and routing of the semiconductor integrated circuit is performed using the result of the individual design for such a multi-port memory. It is necessary to go back to the individual design for the multiport memory. In order to correct the operation speed of a circuit, it is necessary to change the size of the transistors constituting the circuit or to correct the circuit configuration. In any case, the connection relationship and wiring with parts other than the circuit In some cases, the route may be corrected, and it may not be possible to deal with it only at the mounting design stage such as placement and routing. This also increases the design man-hours and design costs.

  An object of the present invention is to provide a method for developing a semiconductor integrated circuit in which an interface speed can be easily set with no excess or deficiency with respect to required specifications of a memory unit.

  Another object of the present invention is to provide a method for developing a semiconductor integrated circuit in which the interface speed for each port for a multi-port can be easily set.

  Another object of the present invention is to provide a method for developing a semiconductor integrated circuit capable of customizing the interface speed of a memory unit at the mounting design stage.

  Another object of the present invention is to provide a method of developing a semiconductor integrated circuit that can shorten the design period.

  Another object of the present invention is to provide a semiconductor integrated circuit that can contribute to low power consumption in that it operates at an interface speed that does not exceed the required specifications of the memory unit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A method for developing a semiconductor integrated circuit according to the present invention is a method for developing a semiconductor integrated circuit having at least a memory portion in one of circuit modules formed on a semiconductor substrate. A first process to be performed, a second process (cell design) for individually designing circuit modules in accordance with the logic design result, and a third process (mounting design) for determining the placement and routing of the semiconductor integrated circuit reflecting the individual design. A fourth process for performing timing verification and necessary correction on the placement and routing result, a fifth process for generating a mask based on the placement and routing result that has undergone the necessary correction, and a wafer using the generated mask And a sixth process for performing the process. In the second processing, in the individual design of the memory unit, a memory array (11) in which a plurality of memory cells are arranged, a memory logic circuit (14) that performs a logic operation for accessing the memory array, and a memory array The memory interface circuit (16, 17, 18) for performing input / output operations for accessing the memory is designed, and a plurality of access ports are configured by the memory interface circuit and the memory control circuit, and at least the memory interface circuit and the memory In the individual design of the logic circuit, a plurality of standard cells having the same circuit configuration and arrangement area are used for each type, and the difference in operation speed between the plurality of access ports is set by the difference in operation speed of the same standard cell. In short, at the stage of the individual design of the memory unit (cell design of the second process), the operation speeds of the individual standard cells constituting the memory interface circuit and the memory logic circuit are individually set. When attention is also paid to area efficiency, a hard macro having a circuit arrangement denser than a circuit using standard cells may be used for the individual design of the memory array in the second processing.

  According to the above means, in the individual design of the memory unit, the memory interface circuit and the memory logic circuit use a plurality of standard cells having the same circuit configuration and arrangement area for each type, so that the interface with the outside is required. When setting the operation speed with the, select the optimal standard cell from other standard cells of the same type that have different current drive capabilities determined by the threshold voltage of the MOS transistor and the gate width of the MOS transistor. Can do. Therefore, it is possible to easily set the interface speed so as not to exceed the required specifications of the memory unit. This is effective in reducing power consumption.

  Due to the nature of the standard cell, replacement (replacement) between cells of the same type does not require modification of the wiring pattern or circuit configuration itself outside the cell area, so several types of memory units with different interface specifications are available. This also reduces the design man-hours.

  The memory interface circuit and the memory control circuit constitute a plurality of access ports, and in the second process, the difference in the operation speed of the plurality of access ports is set by the difference in the operation speed of the same standard cell. It is possible to easily set the interface speed for each port.

  [2] A semiconductor integrated circuit development method according to another aspect of the present invention provides an operation speed of standard cells constituting the memory interface circuit and the memory logic circuit at the stage of individual design of the memory section (cell design of the second process). Is not set individually, but is set to standard, for example, and standard cell replacement (cell replacement) is selectively performed so as to obtain a necessary operation speed based on the timing verification in the fourth process. That is, in the second process, in the individual design of the memory unit, a memory array in which a plurality of memory cells are arranged, a memory logic circuit that performs a logic operation for accessing the memory array, and a memory array are accessed. The memory interface circuit that performs the input / output operation is designed, and at least the individual memory cell circuit and memory logic circuit are designed using a plurality of standard cells having the same circuit configuration and arrangement area for each type. In the fourth process, as a necessary correction based on the timing verification, standard cells having different operation speeds are mixed in the same type of standard cells constituting one or both of the memory interface circuit and the memory logic circuit. When attention is also paid to area efficiency, a hard macro having a circuit arrangement denser than a circuit using standard cells may be used for the individual design of the memory array.

  According to this method, the interface speed of the memory unit can be customized at the mounting design stage where placement and routing is performed. In other words, because of the nature of standard cells, replacement (replacement) between cells of the same type does not require modification of the wiring pattern or circuit configuration outside the cell area, so it is necessary to return to individual design for the modification. In this sense, it is possible to contribute to reduction in design man-hours and cost. Further, similarly to the above, it is possible to easily set the interface speed without excess or deficiency with respect to the required specifications of the memory unit, which is effective in reducing power consumption.

  In a specific form of the present invention, the same type standard cells having different operation speeds are different in the current drive capability, for example, threshold voltage, gate width or gate length, of the MOS transistors constituting the circuit.

  Further, when the memory interface circuit and the memory control circuit constitute a plurality of access ports, the operation speeds of the same standard cells of the plurality of access ports are formed equal in the second processing, and in the fourth processing, The difference in the operating speed of multiple access ports is set by the difference in operating speed of the same standard cell. Therefore, especially in this case, the interface speed for each port for the multi-port can be easily set.

  [3] A semiconductor integrated circuit according to the present invention has a memory section on a semiconductor substrate, and the memory section includes a memory array in which a plurality of memory cells are arranged, and a memory that performs a logical operation for accessing the memory array. A logic circuit and a memory interface circuit that performs an input / output operation for accessing the memory array are included. At least the memory interface circuit and the memory logic circuit are configured by using a plurality of standard cells having the same circuit configuration and arrangement area for each type, and access ports having different operation speeds are standard cells having different operation speeds as the same type of standard cells. Possess. As a result, it is possible to easily set an interface speed that is not excessive or insufficient with respect to the required specifications for the operation speed of the access port. This is effective in reducing power consumption. In the case where attention is also paid to area efficiency, the memory array may be configured with a circuit arrangement denser than a circuit using the standard cells.

  In a specific form of the present invention, standard cells of the same type having different operation speeds are different in, for example, current drive capability of MOS transistors constituting the circuit, for example, threshold voltage, gate width or gate length.

  In another specific form of the invention, the semiconductor integrated circuit includes a plurality of the memory units, and includes an external interface unit connected to an access port of the memory unit, a data processing unit, and a bus. For example, one access port of the memory unit is connected to the external interface unit, and the other access port is connected to the data processing unit. Also, one access port of the memory unit is connected to the external interface unit, and the other access port is connected to the bus. One access port of the memory unit and another access port are connected to the data processing unit. The present invention is significant when the operation speeds of the one access port and other access ports are different.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the semiconductor integrated circuit development method of the present invention, it is possible to easily set the interface speed without excess or deficiency with respect to the required specifications of the memory unit. In addition, it is possible to easily set the interface speed for each port for the multi-port. In addition, the interface speed of the memory unit can be customized at the mounting design stage. And a design period can be shortened.

  The semiconductor integrated circuit according to the present invention can contribute to low power consumption in that it operates at an interface speed that is not excessive or insufficient with respect to the required specifications of the memory unit.

  FIG. 1 shows a logic LSI such as a microcomputer to which the present invention is applied. The microcomputer 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The microcomputer 1 has an external interface unit (I / O) 2 around the semiconductor substrate, and a data processing unit (CORE) 3 inside thereof. The data processing unit 3 includes a central processing unit (CPU) 4, a digital signal processor (DSP) 5, a read-only memory (ROM) 6, and the like. A random access memory (RAM) 7 used as a work area and program area for the CPU 4 is arranged. The data processing unit 3 is connected to the RAM 7 and the direct memory access controller (DMAC) 22 via the internal bus 8, and the data processing unit 3 is connected to the external interface unit 2. The RAM 7 is composed of a large-capacity SRAM or SDRAM, and a plurality of dual-port RAMs (F_RAMm) 10 for buffer use, for example, are distributed as a small-capacity memory unit. The dual port RAM 10 is disposed between the data processing unit 3 and the bus 8, between different circuits of the data processing unit 3, and between the external interface unit 2 and the data processing unit 3. Further, the microcomputer has a peripheral circuit 21 connected to the peripheral bus 20, and a dual port RAM (F_RAMm) 10 is disposed between the peripheral bus 20 and the bus 8 and used as a shared memory.

  FIG. 2 schematically shows the configuration of the dual port RAM 10. The dual port RAM 10 includes a memory array (ARY) 11 in which a plurality of memory cells are arranged, and one access port (first port PORTa) is configured by an input system circuit 12a and an output system circuit 13a with respect to the memory array. The input system circuit 12b and the output system circuit 13b constitute the other access port (second port PORTb). The input system circuit 12a includes a plurality of address decoders (DEC) 14 and a timing controller (TCNT) 15 that are representatively shown as memory logic circuits that perform a logic operation for accessing the memory array 11, and a memory array. 11 has an address input latch (ADL) 16 and a data input latch (DI) 17 representatively shown as a memory interface circuit for performing an input operation for accessing 11. The address input latch 16 receives and latches an address signal from a plurality of bit address terminals PaRAD and PaWAD. The address terminal PaRAD is for inputting a read address signal, and PaWAD is for inputting a write address signal. The latched address signal is decoded by the address decoder 14 to generate a memory cell selection signal in the memory array 11. The data input latch 17 latches write data from the multi-bit data input terminal PaDI and supplies it to the memory array 11. The output system circuit 13 a has a data output latch (DQ) 18 that performs an output operation for accessing the memory array 11. A data output latch (DQ) 18 latches the read data output from the memory array 11 and supplies it to the data output terminal PaDQ. The timing controller 15 inputs a read signal from the control terminal PaR, inputs a write signal from the control terminal PaW, and inputs a clock signal from the clock terminal PaCLK. When a read operation is instructed, the timing controller 15 controls the address input latch 16 and the data output latch 18 to latch in synchronization with the clock signal so that the read data can be output to the outside. When a write operation is instructed, the timing controller 15 controls the address input latch 16 and the data input latch 17 to be latched in synchronization with the clock signal so that the write data can be written to the memory cell. φ1R is a control clock for an address input latch 16 for inputting a read address signal, φ1W is a control clock for an address input latch 16 for inputting a write address signal, φ2 is a control clock for a data output latch 18, and φ3 is a data input latch 17 Control clock.

  Although not shown, the other input system circuit 12b and output system circuit 13b are similarly configured. Address terminals PbRAD and PbWAD, data input terminals PbDI, control terminals PbW and PbR, and clock terminals PbCLK are assigned to the input system circuit 12b. A data output terminal PbDQ is assigned to the output system circuit 13b.

  FIG. 3 illustrates a circuit configuration of the address input latch 16. The address input latch 16 has inverters 16A and 16B at an input stage and an output stage. Between the input transfer gate 16C and the output inverter 16B, two series of inverters 16D and 16E and a latch transfer gate 16F are arranged in reverse parallel connection. Is done. The transfer gates 16C and 16F are switched in a complementary manner with respect to the change of the latch clock φ1, input the address signal at the low level of the latch clock φ1, and latch the input address signal at the high level of the latch clock φ1.

  FIG. 4 illustrates a circuit configuration of the address decoder 14. The address decoder 14 is constituted by a series circuit of a three-input NAND gate 14A and inverters 14B and 14C, and outputs of a plurality of address input latches 16 are distributed and inputted to the three-input NAND gate 14A.

  FIG. 5 illustrates a circuit configuration for one bit of a memory cell in the memory array. The memory cell 14A has a CMOS static latch configuration in which CMOS inverters 14B and 14C are connected in antiparallel. The memory cell 14A is connected to the input data line 14E through the input gate 14D, and another memory cell 14A is connected to the input data line. The memory cell 14A is connected to the output data line 14H via the output inverter 14F and the output gate 14G, and another memory cell 14A is connected to the output data line 14H. The input gate and the output gate are switch-controlled by a decode signal output from the address decoder 14.

  FIG. 6 illustrates the configuration of one bit of the data output latch 18. The data output latch 18 includes a series path including an input inverter 18A, an input gate 18B, and an output inverter 18C connected to the output data line 14H. An input / output node of a latch stage is provided between the input gate 18B and the output inverter 18C. Combined. The latch stage is formed by feedback connection of an inverter 18D, a latch gate 18E, an inverter 18F, and a latch gate 18G, and a connection point between the inverter 18D and the latch gate 18G is an input / output node of the latch stage. The input gate 18B and the latch gates 18E and 18G are switched in a complementary manner with respect to the change of the latch clock φ2, input read data at the low level of the latch clock φ2, and latch input data at the high level of the latch clock φ2. . In the figure, a and b are complementary signals of the latch clock φ2.

  Although not shown, the data input latch 17 is composed of a circuit similar to the address input latch 16, and the latch operation of the input data is controlled by a latch clock φ3 in FIG.

  FIG. 7 illustrates a first interface form of the first port PORTa and the second port PORTb of the dual port RAM 10. In the figure, the timing controller 15 is shown outside the RAM 10 for convenience. The first port PORTa is connected to the external interface unit 2 via an address line (ADD) and a data line (DAT), and the second port PORTb is connected to the data processing unit 3 via an address line (ADD) and a data line (DAT). Connected. The external interface unit 2 and the data processing unit 3 access the first port PORTa and the second port PROTb in synchronization with different frequencies, respectively. For example, the external interface unit 2 accesses the first port PORTa in synchronization with the clock frequency of 66 MHz, and the data processing unit 3 accesses the second port PORTb in synchronization with the clock frequency of 300 MHz. The dual port RAM 10 used in the first external interface mode operates at a speed of 66 MHz in response to an access request from the first port PORTa side, and 300 MHz in response to an access request from the second port PORTb side. Works at speeds of. FIG. 8 shows an example of the operation timing at that time. The data processing unit 3 outputs a write control signal PbW to the timing controller 15 in synchronization with the 300 MHz clock signal PbCLK and outputs data D1 to the data bus PbDI. Under the control of the timing controller 15, the dual port RAM 10 writes data D1 input to the second port PORTb into the memory array (ARY) 11. Next, the external interface unit 2 outputs a read control signal PaR to the timing controller 15 in synchronization with the 66 MHz clock signal PaCLK. Under the control of the timing controller 15, the dual port RAM 10 outputs data D 1 from the first port PORTa to the external interface unit 2. In this way, the data input / output timing between circuits having different access speeds is adjusted.

  The dual port RAM 10 is required to have an external interface form corresponding to a part in which the dual port RAM 10 is used. In addition, the microcomputer 1 includes a second interface form shown in FIG. 9 and a third interface form shown in FIG. The dual port RAM 10 having the interface form, the fourth interface form shown in FIG. 11, is mounted.

  In the second interface form shown in FIG. 9, the first port PORTa is connected to the bus 8 and the second port PORTb is connected to the data processing unit 3. ADD means address wiring, and DAT means data wiring. The DMAC 22 and the like access the first port PORTa via the internal bus 8 in synchronization with the clock frequency of 150 MHz. The data processing unit 3 accesses the second port PORTb in synchronization with the clock frequency of 300 MHz. The dual port RAM 10 used in the second external interface mode operates at a speed of 150 MHz in response to an access request from the first port PORTa side, and 300 MHz in response to an access request from the second port PORTb side. Works at speeds of.

  In the third interface form shown in FIG. 10, the first port PORTa is connected to the logical unit 3A of the data processing unit 3, and the second port PORTb is connected to the logical unit 3B of the data processing unit 3. ADD means address wiring, and DAT means data wiring. A lot of intermediate logic 3C is interposed between the logic unit 3A and the first port PORTa. The signal propagation in the signal path in which many intermediate logics 3C are interposed takes time compared to the second port PORTb side having a small number of intermediate logics. At this time, high-speed access (or a large driving force) is used for the first port PORTa, and low-speed access (or a small driving force) is used for the second port PORTb. As a result, input / output operations at both ports PORTa and PORTb are performed without lowering the threshold voltage of the intermediate logic 3C, switching to a long-distance wiring on the low load side, and increasing the width of the wiring at the stage of mounting design. It becomes possible to make the speed the same.

  In the fourth interface form shown in FIG. 11, the first port PORTa is connected to the bus 8 and the second port PORTb is connected to the peripheral bus 20. ADD means address wiring, and DAT means data wiring. The peripheral circuit 21 accesses the second port PORTb through the peripheral bus 20 in synchronization with the clock frequency of 66 MHz. The data processing unit 3 or the DMAC 22 accesses the first port PORTa via the bus 8 in synchronization with the clock frequency of 150 MHz. The dual port RAM 10 used in the fourth interface mode operates at a speed of 150 MHz in response to an access request from the first port PORTa side, and 66 MHz in response to an access request from the second port PORTb side. Work at speed.

  A design method suitable for setting a required interface speed represented by the above-described interface form in the dual port RAM 10 will be described below.

  First, the address latch 16, the data input latch 17, the data output latch 18 as the memory interface circuit, the decoder 14 as the memory logic circuit, and the timing controller 15 include a plurality of standard cells having the same circuit configuration and arrangement area for each type. To configure. The above-mentioned types mean standard cell types such as inverters, three-input NAND gates, transfer gates, and the like. For the same type of standard cells, standard cells having different operation speeds are mixed and used as necessary. In the same type of standard cells having different operating speeds, for example, the threshold voltages of the MOS transistors constituting the circuit are different, or the gate widths of the MOS transistors constituting the circuit are different. Setting the operating speed of a standard cell means adopting a standard cell having a required operating speed. The memory array 11 is configured by using, for example, a hard macro cell having a circuit arrangement denser than a circuit using the standard cell. A hard macrocell is a designed circuit component that has been optimized for placement and routing for the functions that it should have, and has undergone various verifications. Recently, it is a module that is provided as a so-called hard IP module. is there.

  FIG. 12 illustrates a layout pattern of a standard cell for a CMOS inverter. FIG. 12 shows a layout of an inverter using a standard MOS transistor (standard MOS inverter) and a layout of an inverter using a low threshold MOS transistor (low threshold MOS inverter). 30 is an n-type well region (n-well) where a p-channel MOS transistor (PMOS transistor) is formed, 31 is a p-type well region (p-well) where an n-channel MOS transistor (NMOS transistor) is formed, and 32 is An n-well power supply contact, 33 is a p-well power supply contact, 34 is an n-type diffusion region, and 35 is a p-type diffusion region. 36 is a power supply wiring to which the power supply voltage Vdd is supplied, 37 is a ground wiring to which the circuit ground voltage Vss is supplied, 38A to 38D are polysilicon gate wirings, 39 is a PMOS transistor source contact, and 40 is a PNOS transistor drain contact. , 41 are drain contacts of the NNOS transistor, and 42 is a source contact of the NNOS transistor. Source contact 39 connects diffusion region 34 to power supply wiring 36. The source contact 42 connects the diffusion region 35 to the ground wiring 37. The drain contacts 40 and 41 are commonly connected through signal wirings 43A to 43D and the like, and serve as CMOS invert output terminals. The polysilicon gate wirings 38A to 38D are commonly connected through signal wirings 44A to 44C and the like, and serve as input terminals for CMOS inversion.

  The operating speed of the standard MOS inverter and the low threshold MOS inverter of FIG. 12 differ only in the impurity concentration with respect to the ion implantation layer (implant layer) in the diffusion region and by providing a difference in threshold voltage. Therefore, there is no difference in the size of the pattern. For example, if the threshold voltage of the standard PMOS transistor is −0.1 V and the threshold voltage of the standard NMOS transistor is 0.1 V, the threshold voltage of the low threshold PMOS transistor is 0 V, and the threshold voltage of the low threshold NMOS transistor is 0 V.

  When changing the current supply capability (mutual conductance) of the MOS transistor by changing the gate electrode width of the MOS transistor, the widths of the polysilicon gate wirings 38A to 38D are different. The basic design of the standard cell is performed so that this difference does not change the layout area of the standard cell for each type. In short, the standard cell has an area margin so that the size of the rectangular area allocated to the cell arrangement does not change even if the pattern width is changed.

  Therefore, even if the standard cell constituting the circuit is replaced with a cell of the same type and having a different operation speed, the size of the rectangular area allocated to the cell arrangement does not change, so the circuit configuration and the arrangement area for each type are not changed. Even if a cell having a different speed is selected from the standard cells of the same type or a cell is replaced with a standard cell having the same, it is not necessary to modify the surrounding wiring pattern.

  As described above, the address input latch 16, the decoder 14, the data input latch 17, and the data output latch are considered when setting the required interface speed as represented by the above-described interface configuration in the dual port RAM 10. For the same type of standard cells constituting the circuit 18, standard cells having the same circuit configuration and arrangement area are adopted for each type, and standard cells having different operation speeds may be mixed. For example, in the address latch 16, a low threshold MOS standard cell is used for each of the inverter 16A, the transfer gate 16C, and the transfer gate 16F illustrated in FIG. In the case of the decoder 14, a low threshold MOS standard cell is used for all of the NAND gate 14A and the inverters 14B and 14C shown in FIG. In the case of the data output latch 18, low threshold MOS standard cells are used for the inverters 18A and 18C and the transfer gate 18C shown in FIG.

  By using a mixture of standard cells with different operating speeds, it is possible to set an interface speed that does not exceed or exceed the required specifications of the dual port RAM 10 for the ports PORTa and PORTb. Alternatively, it can be handled very easily because it can be handled by replacement.

  FIGS. 13 to 17 illustrate the setting mode of standard cells constituting the ports PORTa and PORTb in the dual port RAM 10. In each figure, ADLa16, DECa14, DIa17, and DQa18 constitute a first port PORTa, and ADLb16, DECb14, DIb17, and DQb18 constitute a second port PORTb. A circuit block surrounded by a double frame means a standard cell (low threshold MOS standard cell) using a low threshold MOS transistor, and a circuit block surrounded by a single frame is a standard cell (standard MOS) using a standard MOS transistor. Standard cell). FIG. 13 shows a standard speed type in which standard access speeds are selected for both ports PORTa and PORTb of the dual port RAM 10. In FIG. 14, a high-speed type is selected in which a high-speed access speed is selected for both ports PORTa and PORTb of the dual-port RAM 10. In FIG. 15, the PORTa standard speed and PORTb high speed types are selected, in which the standard access speed is selected for the first port PORTa of the dual port RAM 10 and the high speed access speed is selected for the second PORTb. In FIG. 16, the read high-speed type is selected in which the read access speed is increased and the standard speed of the write access is selected for both ports PORTa and PORTb of the dual port RAM 10. In FIG. 17, a write high-speed type is selected in which both the ports PORTa and PORTb of the dual-port RAM 10 are accelerated in write access and standard speed is selected in read access.

  FIG. 18 illustrates a development flow of the microcomputer 1 using the dual port RAM 10. First, in order to satisfy the necessary functions, the logical path of the entire microcomputer is designed (S1). Next, a cell design process for individually designing various circuit modules mounted on the microcomputer 1 is performed according to the logic design result (S2). Such logic design and cell design can be performed using a hardware description language (HDL). In particular, in the cell design for the dual port RAM 10, as shown in FIG. 13, a hard macro is used for the memory array 11 and various standard cells of standard MOS transistors are used for the ports (S2A). . For the basic design, it is necessary to match the required interface form among the interface forms represented by FIGS. 8 to 11 in accordance with the location of the dual port RAM 10 on the microcomputer 1 and the application logic. Replacement of the standard cell for the circuit portion (RAM development design) is performed so that the necessary operation speed can be obtained for each access port (S2B). Here, a plurality of standard cells having the same circuit configuration and arrangement area are used for each type, and the memory interface circuits 16, 17, 18 and the memory logic circuit 14 are mixed with standard cells having different operation speeds as necessary. become. In short, at the stage of cell design of the memory unit, the operation speeds of the individual standard cells constituting the memory interface circuit and the memory logic circuit are individually set. For example, in the case of a usage mode that requires high-speed read access, as described with reference to FIG. 16, the ADL16, DEC14, and DQ18 of both ports PORTa and PORTb use standard cells composed of low threshold MOS transistors. Next, a mounting design for determining the placement and wiring of the microcomputer 1 is performed by reflecting individual designs for various on-chip circuit blocks by the cell design process (S3). For the placement and routing result, necessary timing adjustment (S4) and timing verification by simulation (S5) are repeated. After completing the timing verification and necessary timing adjustment, mask generation is performed based on the result of the placement and routing (S6). The mask means either a photomask or mask data for wafer direct drawing using an electron beam. Finally, a wafer process is performed using the generated mask to generate a semiconductor chip of the microcomputer (S7). The semiconductor chip is packaged in an appropriate form, tested and shipped. A known CMOS integrated circuit process or the like can be used for the wafer process.

  According to the above development method, in the individual design of the dual port RAM 10, the memory interface circuits 16, 17, 18 and the memory logic circuit 14 use a plurality of standard cells having the same circuit configuration and arrangement area for each type. When setting the operation speed according to the needs of the external interface, select the optimum standard cell from other standard cells of the same type that differ in the threshold voltage of the MOS transistor and the gate width of the MOS transistor. Can be dealt with. In short, the standard cell of the same type constituting either one or both of the memory interface circuits 16, 17, 18 and the memory logic circuit 14 of the dual port RAM 10 has different operation speeds depending on the necessity of an interface with the outside. What is necessary is just to mix a standard cell. Therefore, it is possible to easily set the interface speed so as not to exceed the required specifications of the dual port RAM 10. This is effective in reducing power consumption.

  Due to the nature of standard cells, replacement (replacement) between standard cells of the same type does not require modification of the wiring pattern or circuit configuration itself outside the cell region, and therefore, several types of dual-port RAMs 10 having different interface specifications. Design man-hours can also be reduced when preparing the system.

  The memory interface circuits 16, 17, and 18 and the memory control circuit 14 constitute a plurality of access ports PORT1 and PORT2. In the dual-port RAM development design S2B, the difference in operation speed between the plurality of access ports can be compared with that of the same standard cell. Since the setting is made according to the difference in the operation speed, the interface speed for each port for the dual port can be easily set.

  FIG. 19 illustrates another development flow of the microcomputer 1 using the dual port RAM 10. The difference from FIG. 18 is that, in the individual design process (S2) of the dual port RAM 10, the operation speeds of the standard cells constituting the memory interface circuits 16, 17, 18 and the memory logic circuit 14 are not individually set. Only the standard design as shown in FIG. 13 is performed, and standard cell replacement (cell replacement) is selectively performed so as to obtain a necessary operation speed based on the timing verification in step S5 (S8). For example, if the operation speed of one access port PORTb is insufficient as a result of the timing verification, the standard cell of ADLb16, DECb14, DIb17, DQb18 on the access port PORTb side is replaced with a low threshold MOS standard cell, and the interface configuration of FIG. Realize.

  According to this development method, the interface speed of the dual port RAM 10 can be customized at the mounting design stage where the placement and routing is performed. In other words, because of the nature of standard cells, replacement (replacement) between standard cells of the same type does not require modification of the wiring pattern or circuit configuration outside the cell area. It is not necessary to return to (S2), and in this sense, it is possible to contribute to the reduction of the design man-hours and the cost. As described above, it is possible to easily set an interface speed that is not excessive or deficient with respect to the required specifications of the dual port RAM 10, which is effective in reducing power consumption. In particular, in the cell design (S2), a standard design is performed in which the operation speeds of the same standard cells of the access ports PORT1 and PORT2 are set equal. In the cell replacement process (S8) based on the timing verification, the plurality of access ports PORT1, Since the difference in the operation speed of the PORT 2 is set by the difference in the operation speed of the same standard cell, the interface speed for each port can be easily set. Since speed control is based on cell replacement, timing verification after mounting enables optimization by cell replacement for timing violations or over margins, which is effective in saving design man-hours and reducing power consumption.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory unit is not limited to a dual port RAM, and the present invention can also be applied to a multi-port memory having a larger number of ports. Specific circuit configurations of the memory array, the memory interface circuit, and the memory logic circuit are not limited to the above description, and can be changed as appropriate. Also, the type of standard cell, its layout pattern, etc. can be changed as appropriate. Semiconductor integrated circuits can be widely applied not only to microcomputers but also to LSIs such as controllers specialized in audio processing, graphic processing, security processing, and the like. Further, the current driving capability of the MOS transistor in the standard cell can be controlled by the gate length in addition to the threshold voltage and the gate width.

  In the above description, focusing on area efficiency, a hard macro having a circuit arrangement denser than a circuit using standard cells is used for the individual design of the memory array 11. This is because it is considered that the storage capacity of the memory array 11 is not extremely small like a register. Even if the storage capacity of the memory array 11 is not as large as that of the register, it can be configured using standard cells if it is considerably small. At this time, when high speed operation is selected for the memory array, a low threshold MOS standard cell may be selected as the standard cell constituting the memory array 11.

  In addition, the selection or replacement of standard cells for setting a required operation speed for an access port is not limited to an access port unit or an operation unit such as a read access speed increase or a write access speed increase. It is possible to target a part of an access port such as an address input latch and an address decoder so as to speed up the system. In the dual port RAM, the address input terminal may not be dedicated for reading and writing. Similarly, the data terminal may be used for both input and output.

It is a block diagram of a microcomputer to which the present invention is applied. 2 is a block diagram schematically showing a configuration of a dual port RAM. FIG. FIG. 3 is a circuit diagram illustrating details of an address input latch. It is a circuit diagram which illustrates the detail of an address decoder. 3 is a circuit diagram illustrating details of one bit of a memory cell in a memory array. FIG. FIG. 6 is a circuit diagram illustrating details of a data output latch. It is explanatory drawing which illustrates the 1st interface form of the 1st and 2nd port in dual port RAM. 8 is a timing chart illustrating an access operation in the interface form of FIG. It is explanatory drawing which illustrates the 2nd interface form of the 1st and 2nd port in dual port RAM. It is explanatory drawing which illustrates the 3rd interface form of the 1st and 2nd port in dual port RAM. It is explanatory drawing which illustrates the 4th interface form of the 1st and 2nd port in dual port RAM. It is a top view which illustrates the layout pattern of the standard cell for CMOS inverters. It is explanatory drawing of the standard speed type which selected the standard access speed as a setting mode of the standard cell which comprises the 1st and 2nd port in dual port RAM. It is explanatory drawing of the high-speed type which selected high-speed access speed as the setting aspect of the standard cell which comprises the 1st and 2nd port in dual port RAM. As the setting mode of the standard cells constituting the first and second ports in the dual port RAM, the standard access speed is selected for the first port and the high speed access speed is selected for the second port. It is explanatory drawing. FIG. 5 is an explanatory diagram of a read high-speed type in which a high-speed read access and a standard speed of write access are selected for both ports as a setting mode of standard cells constituting the first and second ports in the dual-port RAM. FIG. 5 is an explanatory diagram of a write high-speed type in which the standard cell constituting the first and second ports in the dual-port RAM is set as a high-speed write access and a standard speed is selected for read access for both ports. It is a flowchart which illustrates the development flow of the microcomputer using dual port RAM. It is a flowchart which illustrates another development flow of the microcomputer using dual port RAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microcomputer 2 External interface part 3 Data processing part 8 Internal bus 10 Dual port RAM
PORTa first port PORTb second port 11 memory array 12a first port configuration input system circuit 13a first port configuration output system circuit 12b second port configuration input system circuit 13b second port configuration output system circuit 14 address decoder 15 Timing Controller 16 Address Input Latch 17 Data Input Latch 18 Data Output Latch 20 Peripheral Bus 21 Peripheral Circuit

Claims (11)

A method for developing a semiconductor integrated circuit having at least a memory portion in one of circuit modules formed on a semiconductor substrate,
A first process for performing logic design of the semiconductor integrated circuit;
A second process for individually designing circuit modules according to the logic design results;
A third process for determining the placement and routing of the semiconductor integrated circuit reflecting the individual design;
A fourth process for performing timing verification and necessary correction on the placement and routing result;
A fifth process for generating a mask based on the result of placement and routing that has undergone the necessary corrections;
A sixth process of performing a wafer process using the generated mask,
In the second processing, in the individual design of the memory unit, a memory array in which a plurality of memory cells are arranged, a memory logic circuit that performs a logic operation for accessing the memory array, and an input for accessing the memory array A memory interface circuit that performs an output operation is designed, and a plurality of access ports are configured by the memory interface circuit and the memory control circuit,
At least, the individual design of the memory interface circuit and the memory logic circuit uses a plurality of standard cells having the same circuit configuration and arrangement area for each type, and the difference in the operation speed of the plurality of access ports is compared with the operation speed of the same standard cell. A method for developing semiconductor integrated circuits that is set according to differences. 2. The method for developing a semiconductor integrated circuit according to claim 1, wherein in the second processing, a circuit arrangement denser than a circuit using standard cells is adopted for the individual design of the memory array. 2. The method of developing a semiconductor integrated circuit according to claim 1, wherein the same type of standard cells having different operating speeds are different in current drive capability of MOS transistors constituting the circuit. A method of developing a semiconductor integrated circuit having at least a memory portion in one of circuit modules formed on a semiconductor substrate,
A first process for performing logic design of the semiconductor integrated circuit;
A second process for individually designing circuit modules according to the logic design results;
A third process for determining the placement and routing of the semiconductor integrated circuit reflecting the individual design;
A fourth process for performing timing verification and necessary correction on the placement and routing result;
A fifth process for generating a mask based on the result of placement and routing that has undergone the necessary corrections;
A sixth process of performing a wafer process using the generated mask,
In the second processing, in the individual design of the memory unit, a memory array in which a plurality of memory cells are arranged, a memory logic circuit that performs a logic operation for accessing the memory array, and an input for accessing the memory array Designing a memory interface circuit that performs output operation,
At least, the individual design of the memory interface circuit and the memory logic circuit uses a plurality of standard cells having the same circuit configuration and arrangement area for each type,
In the fourth process, as a necessary correction based on the timing verification, at least one of the memory interface circuit and the memory logic circuit of the same type constituting both or both of the standard cells having different operation speeds is mixed. , Development method of semiconductor integrated circuit. 5. The method of developing a semiconductor integrated circuit according to claim 4, wherein in the second processing, a circuit arrangement denser than a circuit using standard cells is adopted for the individual design of the memory array. 5. The method of developing a semiconductor integrated circuit according to claim 4, wherein the same type of standard cells having different operating speeds have different current drive capabilities of the MOS transistors constituting the circuit. The memory interface circuit and the memory control circuit constitute a plurality of access ports,
In the second process, the operation speeds of the same standard cells of the plurality of access ports are formed to be equal,
5. The method for developing a semiconductor integrated circuit according to claim 4, wherein, in the fourth process, a difference in operating speed between the plurality of access ports is set according to a difference in operating speed of the same standard cell. A semiconductor integrated circuit having a memory portion on a semiconductor substrate,
The memory unit includes a memory array in which a plurality of memory cells are arranged, a memory logic circuit that performs a logic operation for accessing the memory array, and a memory interface circuit that performs an input / output operation for accessing the memory array. The memory interface circuit and the memory control circuit constitute a plurality of access ports,
At least the memory interface circuit and the memory logic circuit are configured by using a plurality of standard cells having the same circuit configuration and arrangement area for each type, and access ports having different operation speeds are standard cells having different operation speeds as the same type of standard cells. Semiconductor integrated circuit possessed. The semiconductor integrated circuit according to claim 8, wherein the memory array is configured with a circuit arrangement denser than a circuit using the standard cell. 10. The semiconductor integrated circuit according to claim 9, wherein the same type standard cells having different operation speeds are different in current drive capability of MOS transistors constituting the circuit. 9. The semiconductor integrated circuit according to claim 8, comprising a plurality of said memory units, and having an external interface unit, a data processing unit, and a bus connected to an access port of said memory unit.

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