JP2012145990A - Integrated circuit and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a conventional integrated circuit is characterized in that the number of internal states of an LSI is huge, the internal states are fast varied and cannot be reproduced frequently, so that technique of monitoring the internal state or detecting an error by comparing the internal states is present but technique of performing processing by utilizing internal states of another LSI is not present.SOLUTION: An integrated circuit includes signal processing means which receives a signal and processes the signal, and one or more pieces of storage means each being capable of storing an internal state that is information about signal processing. The integrated circuit further includes any one of receiving means which receives an internal state from another integrated circuit, transmitting means which transmits the internal state stored in the storage means to the other integrated circuit, and receiving and transmitting means which receives the internal state from the other integrated circuit and transmits the internal state stored in the storage means to the other integrated circuit. Thus, internal states can be shared between the integrated circuits.

Description

  The present invention relates to an integrated circuit that transmits and receives internal states.

  Conventionally, there are devices that monitor the internal state of LSIs (see Patent Document 1) and devices that detect errors by comparing internal states between LSIs (see Patent Document 2).

JP 05-34003 A JP 06-274360 A

  In the above technique, the internal state of the LSI is monitored, and an error is detected by comparing the internal state. When an error is detected, processing is performed using the internal state of another LSI. I can't.

  The integrated circuit of the first invention is an integrated circuit comprising signal processing means for receiving a signal and processing the signal, and one or more storage means capable of storing an internal state which is information relating to signal processing, Receiving means for receiving an internal state from another integrated circuit, or transmitting means for transmitting an internal state stored in a storing means to another integrated circuit, or receiving an internal state from another integrated circuit and storing it in the storing means It is an integrated circuit provided with either transmission / reception means for transmitting the stored internal state to another integrated circuit.

  With such a configuration, the internal state can be shared between the integrated circuits.

  Further, in the integrated circuit of the second invention, in contrast to the first invention, the signal processing means processes the signal using the internal state when the receiving means or the transmitting / receiving means receives the internal state. Integrated circuit.

  With such a configuration, signal processing can be performed using an internal state received from another integrated circuit.

The integrated circuit according to the third aspect of the invention is a judging means for judging whether or not a predetermined condition is satisfied with respect to the first or second invention, and the judging means satisfies the predetermined condition. If it is determined that the internal state stored in the storage unit is transmitted to another integrated circuit, the transmission unit or the transmission / reception unit is instructed, or the internal state is received from the other integrated circuit. And a control means for instructing
When the transmission unit or the transmission / reception unit receives an instruction from the control unit, the transmission unit or the transmission / reception unit transmits the internal state stored in the storage unit to another integrated circuit, and the reception unit or the transmission / reception unit receives the instruction from the control unit. An integrated circuit that receives an internal state from another integrated circuit.

  With such a configuration, the internal state can be transmitted to another integrated circuit and the internal state can be received from the other integrated circuit according to a predetermined condition.

  In addition, the integrated circuit of the fourth invention is an integrated circuit that transmits a timing signal to another integrated circuit when the transmitting means or the transmitting / receiving means accepts an instruction from the control means. is there.

  With such a configuration, a timing signal can be transmitted to another integrated circuit.

  In the integrated circuit according to the fifth aspect of the present invention, the determination means determines that the signal processing in the signal processing means takes longer to satisfy a predetermined condition than the third or fourth aspect of the invention. In such a case, the integrated circuit determines that a predetermined condition is satisfied.

  With such a configuration, when a time longer than a predetermined time is required for signal processing, the internal state can be transmitted to another integrated circuit.

  Further, in the integrated circuit of the sixth invention, in contrast to the third or fourth invention, the judging means inspects the internal state stored in the storing means and determines that the internal state is abnormal. The integrated circuit determines that a predetermined condition is satisfied.

  With such a configuration, when there is an abnormality in the internal state, the internal state can be received from another integrated circuit.

  Further, in the integrated circuit of the seventh invention, in contrast to the third or fourth invention, the judging means acquires the characteristics of the signal to be processed by the signal processing means, and the characteristics are other integrated circuits. Is an integrated circuit that determines that a predetermined condition is satisfied when it is determined that the characteristics of the signal to be processed are.

  With such a configuration, a signal can be processed according to the characteristics of the integrated circuit.

  Further, in the integrated circuit of the eighth invention, the receiving means or the transmitting / receiving means also receives the timing signal, and the signal processing means is the timing of the receiving means or the transmitting / receiving means. An integrated circuit that processes a signal when the signal is also received.

  With such a configuration, the signal can be processed according to the timing signal.

  Further, the integrated circuit of the ninth invention is a new one based on the internal state received by the receiving means or the transmitting / receiving means and the internal state stored in the storing means with respect to any one of the first to eighth inventions. An internal state generating unit that generates an internal state is further provided, and the signal processing unit is an integrated circuit that processes a signal using the internal state generated by the internal state generating unit.

  With such a configuration, a new internal state can be generated.

  Further, the integrated circuit of the tenth aspect of the present invention is the internal state in which only the information necessary for the signal processing means to perform processing is stored in the storage means as the internal state with respect to any one of the first to ninth aspects. An integrated circuit further comprising processing means.

  With such a configuration, the capacity of the internal state to be saved can be reduced.

  According to the integrated circuit and the like according to the present invention, the internal state can be shared between the integrated circuits.

Block diagram of integrated circuit 1 in the embodiment The figure which shows the structural example of the integrated circuit 2 The figure which shows the structural example of the integrated circuit 3 The figure which shows the example of the process information table The figure which shows the example of the internal state conversion table The figure which shows the example of the internal state processing table

  Hereinafter, embodiments of an integrated circuit and the like according to the present invention will be described with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again.

(Embodiment)
FIG. 1 is a block diagram of an integrated circuit 1 in the present embodiment.

  The integrated circuit 1 includes a signal processing unit 11, a storage unit 12, a determination unit 13, a control unit 14, a transmission / reception unit 15, an internal state generation unit 16, and an internal state processing unit 17. The integrated circuit 1 may include a receiving unit 151 or a transmitting unit 152 instead of the transmitting / receiving unit 15.

  The signal processing unit 11 receives a signal and performs signal processing on the signal. Here, the signal is, for example, a television signal, a video signal, an audio signal, a moving image, or the like. Signal processing includes, for example, high image quality, format conversion, resolution conversion, and the like.

  High image quality means converting low-bit-rate audio, video, etc. to high-bit-rate audio, video, etc., converting low-frame-rate video, etc., to high-frame-rate video, etc. is there. Also, format conversion refers to converting a format (format) of one sound, video, or the like into another audio, video, or the like format. The resolution conversion includes converting a low-resolution video into a high-resolution video, converting a high-resolution image into a low-resolution image, and the like.

  Further, when the transmission / reception unit 15 described later or the reception unit 151 described later receives an internal state from another integrated circuit, the signal processing unit 11 performs signal processing using the internal state. Further, the signal processing unit 11 may perform signal processing when the below-described transmission / reception unit 15 or the later-described reception unit 151 receives an internal state and a timing signal from another integrated circuit. Here, the timing signal is a signal indicating the start timing of signal processing. Further, the signal processing unit 11 may perform signal processing using an internal state generated by an internal state generation unit 16 described later.

  Note that the internal state received by the transmission / reception unit 15 or the reception unit 151 described later and the internal state generated by the internal state generation unit 16 are normally stored in the storage unit 12 described later, resulting in signal processing. The means 11 performs signal processing using the internal state stored in the storage means 12.

  Further, the signal processing means 11 normally performs signal processing according to an instruction from the control means 14 described later.

  The signal processing means 11 can usually be realized by an electronic circuit composed of a diode or a transistor, but may be realized by software.

  The storage unit 12 can store an internal state that is information relating to signal processing. Here, the internal state is a bit string indicating the state of an integrated circuit in which logic circuits, sequential circuits, and the like are integrated. The internal state in the present embodiment is an internal state of the signal processing unit 11. Further, it is assumed that one or more storage means 12 can usually exist. For example, when the signal processing unit 11 divides a signal into two areas for processing, there are two storage units 12. Further, for example, when the signal processing unit 11 divides a signal into 16 regions and processes the signal, there are 16 storage units 12.

  The storage unit 12 can be usually realized by an electronic circuit composed of a diode, a transistor, or the like.

  The determination unit 13 determines whether or not a predetermined condition is satisfied. The predetermined conditions are, for example, that the processing time of one frame of a television signal exceeds the input frame period, the processing time of one frame of the television signal exceeds 1/30 seconds, and is stored in the storage unit 12. The signal processing means 11 performs signal processing with a characteristic of a signal having a lot of noise, and the signal processing means 11 performs signal processing with a characteristic of a blurred video. Etc.

  For example, when the predetermined condition is that the processing time of one frame of the television signal exceeds the input frame period, the determination unit 13 has elapsed since the signal processing unit 11 started the signal processing of the television signal. The time and the frame period of the signal for which the signal processing means 11 is performing signal processing are acquired, and it is determined that a predetermined condition is satisfied when the elapsed time exceeds the frame period.

  Further, for example, when the predetermined condition is that the processing time of one frame of the television signal exceeds 1/30 seconds, the determination unit 13 causes the signal processing unit 11 to start the signal processing of the television signal. The elapsed time from is acquired, and when the elapsed time exceeds 1/30 seconds, it is determined that a predetermined condition is satisfied.

  For example, when the predetermined condition is that the internal state is stored in the storage unit 12, the determination unit 13 acquires the internal state stored in the storage unit 12, and the internal state Are compared with the normal pattern of the internal state, and if the acquired internal state and the normal pattern do not match, it is determined that a predetermined condition is satisfied. In this case, the determination unit 13 acquires the internal state stored in the storage unit 12, compares the internal state with the abnormal pattern of the internal state, and the acquired internal state matches the abnormal pattern. In this case, it may be determined that a predetermined condition is satisfied. A normal pattern is a bit string pattern of an internal state that can occur during signal processing. An abnormal pattern is a bit string pattern in an internal state that cannot occur during signal processing. It is assumed that the normal pattern and the abnormal pattern in the internal state are normally held by the determination unit 13.

  The determination unit 13 can be realized usually by an electronic circuit composed of a diode, a transistor, or the like, but may be realized by software.

  When the determination unit 13 determines that the predetermined condition is satisfied, the control unit 14 stores the internal state stored in the storage unit 12 with respect to the transmission / reception unit 15 or the transmission unit 152 described later. Instruct the circuit to transmit. In other words, the control unit 14 determines whether or not the determination unit 13 determines that a predetermined condition is satisfied, and when determining that the determination unit 13 determines that the predetermined condition is satisfied, The storage unit 12 is instructed to transmit the internal state stored in the storage unit 12 to another integrated circuit.

  The control means 14 can be usually realized by an electronic circuit composed of a diode, a transistor or the like, but may be realized by software.

  The transmission / reception means 15 receives an internal state from another integrated circuit. Further, the transmission / reception means 15 may receive the internal state and the timing signal from another integrated circuit. The transmission / reception unit 15 transmits the internal state stored in the storage unit 12 to another integrated circuit. The transmission / reception unit 15 may transmit the internal state and timing signal stored in the storage unit 12 to another integrated circuit.

  The transmission / reception unit 15 transmits the internal state stored in the storage unit 12 when receiving an instruction from the control unit 14 to transmit the internal state. The transmission / reception unit 15 transmits a timing signal when receiving an instruction from the control unit 14 to transmit a timing signal.

  The transmission / reception means 15 can be usually realized by an electronic circuit composed of a diode or a transistor.

  The internal state generation unit 16 generates a new internal state from the internal state received by the transmission / reception unit 15 or the reception unit 151 described later and the internal state stored in the storage unit 12. At this time, the internal state generating means 16 usually receives a plurality of internal states. The generation of a new internal state is usually determined in advance for each internal state, and the internal state generation unit 16 stores the received internal state and the storage unit 12 according to the processing. A new internal state is generated from the internal state.

  The internal state generation means 16 can be usually realized by an electronic circuit composed of a diode or a transistor, but may be realized by software.

  The internal state processing unit 17 stores the internal state of the signal processing unit 11 in the storage unit 12 when the signal processing unit 11 interrupts the signal processing. At this time, the internal state processing unit 17 stores only information necessary for resuming the processing in the storage unit 12 as an internal state. The information necessary for restarting the process means information necessary for restoring the internal state. For example, when the internal state of the signal processing unit 11 is expressed by a 4-bit bit string, and only the second and fourth bits change while the signal processing unit 11 performs signal processing, The state processing unit 17 does not store the first and third bits that do not change, and stores only the second and fourth bits that change in the storage unit 12.

  The internal state processing means 17 can usually be realized by an electronic circuit composed of a diode, a transistor or the like, but may be realized by software.

  The receiving unit 151 receives an internal state from another integrated circuit. The receiving unit 151 may receive an internal state and a timing signal from another integrated circuit. The receiving means 151 can be usually realized by an electronic circuit composed of a diode or a transistor.

  The transmission unit 152 transmits the internal state stored in the storage unit 12 to another integrated circuit. Further, the transmission unit 152 may transmit the internal state and timing signal stored in the storage unit 12 to another integrated circuit. Note that the transmission unit 152 transmits the internal state stored in the storage unit 12 when receiving an instruction to transmit the internal state from the control unit 14. The transmission unit 152 transmits a timing signal when receiving an instruction from the control unit 14 to transmit a timing signal. The transmission means 152 can be usually realized by an electronic circuit composed of a diode, a transistor, or the like.

(Specific example 1)
In this specific example, an integrated circuit including an internal state transmission / reception circuit that transmits the internal state of the signal processing circuit to the outside and receives the internal state of the signal processing circuit from the outside will be described. Note that the term “external” is a concept including other devices and other circuits.

  FIG. 2 is a diagram illustrating a configuration example of an integrated circuit in the present specific example. The integrated circuit 2 includes an input processing circuit 210, a memory 220, a signal processing circuit 230, a plurality of internal state storage circuits 240, a control circuit 250, switching circuits 261 and 262, an internal state transmission / reception circuit 270, and an output processing circuit 280. The control circuit 250 includes an input queue (not shown) and an output queue (not shown). The signal processing circuit 230 corresponds to the signal processing means 11 in FIG. The internal state storage circuit 240 corresponds to the storage unit 12 of FIG. The control circuit 250 and the switching circuits 261 and 262 correspond to the determination unit 13 and the control unit 14 in FIG. The internal state transmission / reception circuit 270 corresponds to the transmission / reception means 15 of FIG.

  The input processing circuit 210 receives a signal to be subjected to signal processing. Hereinafter, a signal input to the input processing circuit 210 is referred to as an input signal. The memory 220 stores an input signal, a signal processing result that is a result of signal processing of the input signal by the signal processing circuit 230, and the like. The signal processing circuit 230 performs signal processing of the input signal in accordance with the control signal from the control circuit 250. The internal state storage circuit 240 stores the internal state of the signal processing circuit 230. The control circuit 250 controls the signal processing circuit 230, the switching circuits 261 and 262, the internal state transmission / reception circuit 270, and the output processing circuit 280. The switching circuit 261 switches connection between the signal processing circuit 230 and the internal state storage circuit 240. The switching circuit 262 switches connection between the internal state storage circuit 240 and the internal state transmission / reception circuit 270. The internal state transmission / reception circuit 270 transmits the internal state of the signal processing circuit 230 to the outside, and receives the internal state of the signal processing circuit 230 from the outside. The output processing circuit 280 outputs a signal processing result.

  When a signal is input to the input processing circuit 210, the input processing circuit 210 stores the input signal in the memory 220. At this time, the input processing circuit 210 stores each processing unit processed by the signal processing circuit 230. The processing unit is usually a frame. When the storage is completed, the input processing circuit 210 transmits a processing request signal and an input signal storage address to the control circuit 250. The processing request signal is a control signal indicating a request for signal processing. The input signal storage address is an address indicating a storage location of the input signal on the memory 220. The input processing circuit 210 transmits the stored input signal storage address for each processing unit to the control circuit 250 in order to store the input signal for each processing unit.

  Here, for example, it is assumed that the input signal to the input processing circuit 210 is a moving image, and the signal processing circuit 230 divides each frame of the input moving image into 16 regions and performs high resolution processing. The area divided in the input moving image is hereinafter referred to as a divided area. In addition, in order to divide and process each frame of the input moving image into 16 areas, it is assumed that there are 16 internal state storage circuits 240, which is the same number as the division number of 16. Each internal state storage circuit 240 stores the internal state immediately after the signal processing circuit 230 performs signal processing on each divided region. For example, the internal state immediately after processing the first area of the divided area is stored in the first internal state storage circuit 240. For example, the internal state immediately after processing the tenth area of the divided area is stored in the tenth internal state storage circuit 240. As described above, it is assumed that the divided region to be processed and the internal state storage circuit 240 that stores the internal state immediately after the signal processing of the divided region is associated. The method of associating the divided area to be processed with the internal state storage circuit 240 that stores the internal state immediately after the signal processing of the divided area is not limited. Further, the integrated circuit 2 in this specific example is in charge of processing of 8 areas (regardless of position) of the 16 areas, and other integrated circuits are in charge of the remaining 8 areas. Shall be in charge.

  The control circuit 250 receives the processing request signal and the input signal storage address from the input processing circuit 210. Then, the control circuit 250 stores the received items in the input queue.

  Next, the control circuit 250 determines whether or not the signal processing circuit 230 is performing signal processing. When the signal processing circuit 230 is not performing signal processing, the control circuit 250 sends 16 input moving images to the signal processing circuit 230 in order to execute the first request stored in the input queue. Of these areas, control is performed so that areas in charge of processing are processed in order. Specifically, the control circuit 250 first transmits a switching signal indicating that the first internal state storage circuit 240 and the signal processing circuit 230 are connected to the switching circuit 261, and stores the processing start signal and the input signal storage. The address is transmitted to the signal processing circuit 230. The switching signal is a control signal indicating that two circuits are connected. The processing start signal is a control signal indicating that signal processing is started. Whether or not signal processing is being performed is determined based on whether or not the signal processing circuit 230 outputs a non-processing signal that is a control signal indicating that signal processing is not being performed.

  Next, the control circuit 250 receives the processing completion signal and the processing result storage address from the signal processing circuit 230. The processing completion signal is a control signal indicating completion of signal processing. The processing result storage address is an address indicating a storage location of the signal processing result on the memory 220. The control circuit 250 stores the received processing result storage address in the output queue.

  Next, the control circuit 250 transmits a switching signal indicating that the second internal state storage circuit 240 and the signal processing circuit 230 are connected to the switching circuit 261, and the processing start signal and the input signal storage address are It transmits to the signal processing circuit 230. The control circuit 250 repeats such processing the same number of times as the number of regions in charge of processing, and completes processing for one frame.

  In addition, the control circuit 250 constantly monitors the elapsed time since the signal processing circuit 230 starts processing one frame, and determines whether or not the time has exceeded the frame period of the input moving image. When the control circuit 250 determines that the elapsed time has exceeded the frame period of the input moving image, the control circuit 250 causes the internal state storage circuit 240 and the internal state transmission / reception circuit 270 corresponding to the divided area in which the signal processing circuit 230 performs signal processing. A switching signal indicating connection is transmitted to the switching circuit 262. At this time, the control circuit 250 transmits a transmission request signal to the internal state transmission / reception circuit 270. The transmission request signal is a control signal indicating that the internal state is transmitted. Thereafter, the control circuit 250 reduces the number of areas in which the integrated circuit 2 is in charge of processing by one.

  Further, the control circuit 250 receives the internal state reception signal from the internal state transmission / reception circuit 270. The internal state reception signal is a control signal indicating that the internal state transmission / reception circuit 270 has received the internal state from the outside. When receiving the internal state reception signal, the control circuit 250 increases the number of areas in which the integrated circuit 2 is in charge of processing, and stores the internal state corresponding to the divided area indicated by the internal state received by the internal state transmission / reception circuit 270. A switching signal indicating that the circuit 240 and the internal state transmission / reception circuit 270 are connected is transmitted to the switching circuit 262.

  In addition, the control circuit 250 receives the output request signal from the output processing circuit 280. The output request signal is a control signal indicating a request for outputting a signal processing result. Then, when receiving the output request signal, the control circuit 250 transmits the area number for one frame and the processing result storage address stored in the output queue to the output processing circuit 280.

  The switching circuit 261 receives a switching signal for switching the connection between the signal processing circuit 230 and one of the internal state storage circuits 240 from the control circuit 250. When the switching circuit 261 receives the switching signal, the switching circuit 261 switches the connection between the signal processing circuit 230 and one of the internal state storage circuits 240. For example, when the switching circuit 261 receives a switching signal for connection to the first internal state storage circuit 240, the switching circuit 261 connects the signal processing circuit 230 and the first internal state storage circuit 240. Further, for example, when the switching circuit 261 receives a switching signal indicating that it is connected to the tenth internal state storage circuit 240, the switching circuit 261 connects the signal processing circuit 230 and the tenth internal state storage circuit 240.

  The switching circuit 262 receives from the control circuit 250 a switching signal for switching the connection between any of the internal state storage circuits 240 and the internal state transmission / reception circuit 270. When the switching circuit 262 receives the switching signal, the switching circuit 262 switches the connection between any of the internal state storage circuits 240 and the internal state transmission / reception circuit 270. For example, when the switching circuit 262 receives a switching signal for connection to the first internal state storage circuit 240, the switching circuit 262 connects the first internal state storage circuit 240 and the internal state transmission / reception circuit 270. Further, for example, when the switching circuit 262 receives a switching signal indicating that it is connected to the tenth internal state storage circuit 240, the switching circuit 262 connects the tenth internal state storage circuit 240 and the internal state transmission / reception circuit 270.

  The internal state transmission / reception circuit 270 receives a transmission request signal from the control circuit 250. When the internal state transmission / reception circuit 270 receives the transmission request signal, the internal state transmission / reception circuit 270 transmits the internal state request signal to the switching circuit 262, and the internal state stored in the internal state storage circuit 240 is changed to the switching circuit 262 via the switching circuit 262. Receive from. Then, the internal state transmission / reception circuit 270 transmits the received internal state to the outside. The internal state request signal is a control signal indicating an internal state request.

  The internal state transmission / reception circuit 270 receives the internal state from the outside. When the internal state transmission / reception circuit 270 receives the internal state, the internal state transmission / reception circuit 270 transmits an internal state reception signal to the control circuit 250 and transmits the received internal state to the switching circuit 262.

  The output processing circuit 280 transmits an output request signal to the control circuit 250. Then, the output processing circuit 280 receives from the control circuit 250 an area number and a processing result storage address for one frame corresponding to the output request signal. Then, the output processing circuit 280 reads out the signal processing result stored in the storage location on the memory 220 indicated by the processing result storage address, and outputs it according to the output format. The output format is usually instructed by a control signal from the control circuit 250.

(Specific example 2)
In this specific example, an integrated circuit including an internal state processing circuit that detects an abnormality of the signal processing circuit will be described. FIG. 3 is a diagram illustrating a configuration example of the integrated circuit in the present specific example. The integrated circuit 3 includes an input processing circuit 210, a memory 220, a signal processing circuit 230, a plurality of internal state storage circuits 240, a control circuit 350, switching circuits 261 and 262, an internal state transmission / reception circuit 370, an output processing circuit 280, and an internal state processing. A circuit 390 is provided. The internal state processing circuit 390 corresponds to the determination unit 13, the control unit 14, and the internal state processing unit 17 in FIG.

  The internal state processing circuit 390 detects an abnormality in the signal processing circuit 230. Specifically, the internal state processing circuit 390 normally holds an internal state normal pattern, constantly monitors the internal state stored in the internal state storage circuit 240 by the signal processing circuit 230, and the signal processing circuit 230 stores the internal state. It is determined whether the internal state thus matched does not match the normal internal state pattern. The internal state processing circuit 390 determines that an abnormality has been detected when the internal state stored by the signal processing circuit 230 does not match the internal state normal pattern. The normal state normal pattern is a bit string pattern indicating the internal state when the signal processing circuit 230 is operating normally. For example, when the internal state normal pattern is “01010101” and the bit string indicating the internal state stored by the signal processing circuit 230 is “01010101”, the internal state processing circuit 390 determines that the signal processing circuit 230 is normal. To do. If the internal state normal pattern is “01010101” and the bit string indicating the internal state stored by the signal processing circuit 230 is “10101010”, the internal state processing circuit 390 determines that the signal processing circuit 230 is abnormal. To do. For example, when the internal state normal pattern is “1100 ***” and the bit string indicating the internal state stored by the signal processing circuit 230 is “11000011”, the internal state processing circuit 390 may Is determined to be normal. Further, for example, when the internal state normal pattern is “1100 ***” and the bit string indicating the internal state stored by the signal processing circuit 230 is “00111100”, the internal state processing circuit 390 may include the signal processing circuit 230. Is determined to be abnormal. Note that “*” is a symbol indicating an arbitrary bit value (0 or 1).

  Further, for example, the internal state processing circuit 390 holds an internal state abnormality pattern, constantly monitors the internal state stored in the internal state storage circuit 240 by the signal processing circuit 230, and the internal state stored by the signal processing circuit 230. And whether or not the internal state abnormality pattern matches. The internal state processing circuit 390 detects an abnormality when the internal state stored by the signal processing circuit 230 matches the internal state abnormality pattern. The internal state abnormality pattern is a bit string pattern indicating the internal state when the signal processing circuit 230 is operating abnormally. For example, when the internal state abnormality pattern is “01010101” and the bit string indicating the internal state stored by the signal processing circuit 230 is “01010101”, the internal state processing circuit 390 determines that the signal processing circuit 230 is abnormal. To do. When the internal state abnormality pattern is “01010101” and the bit string indicating the internal state stored by the signal processing circuit 230 is “10101010”, the internal state processing circuit 390 determines that the signal processing circuit 230 is normal. To do. Further, for example, when the internal state abnormality pattern is “1100 ***” and the bit string indicating the internal state stored by the signal processing circuit 230 is “11000011”, the internal state processing circuit 390 includes the signal processing circuit 230. Is determined to be abnormal. Further, for example, when the internal state abnormality pattern is “1100 ***” and the bit string indicating the internal state stored by the signal processing circuit 230 is “00111100”, the internal state processing circuit 390 includes the signal processing circuit 230. Is determined to be normal. Note that “*” is a symbol indicating an arbitrary bit value (0 or 1).

  The internal state processing circuit 390 may always monitor the internal state of the signal processing circuit 230 and detect an abnormality in the signal processing circuit 230. In this case, the internal state processing circuit 390 receives the internal state from the signal processing circuit 230 and determines whether the internal state is abnormal using the internal state normal pattern or the internal state abnormal pattern. . The determination method is the same as described above. In this case, the internal state processing circuit 390 normally stores the received internal state in one of the internal state storage circuits 240.

  Further, when the internal state processing circuit 390 detects an abnormality of the signal processing circuit 230, the internal state processing circuit 390 transmits an abnormality detection signal to the control circuit 350. The abnormality detection signal is a control signal indicating that the signal processing circuit 230 is abnormal.

  The control circuit 350 receives the abnormality detection signal from the internal state processing circuit 390. When receiving the abnormality detection signal, the control circuit 350 transmits an internal state reception request signal to the internal state transmission / reception circuit 370. The internal state reception request signal is a control signal indicating a request for reception of the internal state.

  Further, the control circuit 350 receives the internal state reception signal from the internal state transmission / reception circuit 370. When the control circuit 350 receives the internal state reception signal, the control circuit 350 generates a switching signal indicating that the internal state storage circuit 240 and the internal state transmission / reception circuit 370 corresponding to the internal state received by the internal state transmission / reception circuit 370 are connected. Send to. Further, when the control circuit 350 receives the internal state receiving circuit, the control circuit 350 sends a switching signal indicating that any one of the internal state storage circuits 240 storing the internal state received by the internal state transmission / reception circuit 370 and the signal processing circuit 230 is connected. The internal state overwriting signal is transmitted to the internal state processing circuit 390. The internal state overwriting signal is a control signal indicating that the internal state of the signal processing circuit 230 is overwritten by an internal state stored in one of the internal state storage circuits 240 connected to the signal processing circuit 230. is there.

  Thereafter, the internal state processing circuit 390 overwrites the internal state of the signal processing circuit 230 with the internal state stored in any of the internal state storage circuits 240 in accordance with the received internal state overwriting signal.

  The internal state transmission / reception circuit 370 receives the internal state reception request signal from the control circuit 350. When the internal state transmission / reception circuit 370 receives the internal state reception request signal, the internal state transmission / reception circuit 370 transmits the internal state transmission request signal to the outside. The internal state transmission request signal is a control signal indicating a request for transmission of the internal state.

  The internal state transmission / reception circuit 370 receives an internal state transmission request signal from the outside. When the internal state transmission / reception circuit 370 receives the internal state transmission request signal, the internal state transmission / reception circuit 370 transmits the internal state request signal to the switching circuit 262 and switches the internal state stored in the internal state storage circuit 240 via the switching circuit 262. Receive from circuit 262. Then, the internal state transmission / reception circuit 370 transmits the received internal state to the outside.

  The internal state transmission / reception circuit 370 receives the internal state from the outside. When the internal state transmission / reception circuit 370 receives the internal state, the internal state transmission / reception circuit 370 transmits an internal state reception signal to the control circuit 350 and transmits the received internal state to the switching circuit 262.

  Note that the abnormality detection circuit (not shown) may detect the abnormality of the signal processing circuit 230 by the internal state processing circuit 390. In this case, the abnormality detection circuit is normally provided in the signal processing circuit 230.

(Specific example 3)
In this specific example, an integrated circuit including an internal state processing circuit that determines whether an input signal processed by the signal processing circuit is suitable for processing of the signal processing circuit will be described. The configuration example of the integrated circuit in this specific example is the same as that of FIG. 3. In FIG. 3, the integrated circuit 3 is integrated circuit 4, the control circuit 350 is control circuit 450, and the internal state processing circuit 390 is internal state processing circuit. It is read as 490. The integrated circuit 4 includes an input processing circuit 210, a memory 220, a signal processing circuit 230, a plurality of internal state storage circuits 240, a control circuit 450, switching circuits 261 and 262, an internal state transmission / reception circuit 370, an output processing circuit 280, and an internal state processing. A circuit 490 is provided. The internal state processing circuit 490 corresponds to the determination unit 13, the control unit 14, and the internal state generation unit 16 in FIG.

  The internal state processing circuit 490 detects that the internal state of the signal processing circuit 230 matches a predetermined condition. Specifically, the internal state processing circuit 490 normally holds a processing information table in which internal state conditions are defined, constantly monitors the internal state of the signal processing circuit 230, and stores the internal state of the signal processing circuit 230. Determines whether the condition of the internal state defined in the processing information table is met. The internal state processing circuit 490 detects that the predetermined state is met when the internal state of the signal processing circuit 230 matches the internal state condition defined in the processing information table. The predetermined condition is an internal state condition. The internal state condition is, for example, a bit string pattern indicating the internal state of the signal processing circuit 230. The processing information table is, for example, as shown in FIG. The processing information table is composed of conditional expressions including the internal state to be determined and the transmission destination of the internal state when the condition is met. In FIG. 4, “internal state 1”, “internal state 2”, and the like mean a part of the internal state stored in each circuit of the internal state storage circuit 240. For example, the internal state 1 means “the first to eighth bits of the internal state stored in each circuit of the internal state storage circuit 240”, and the internal state 2 indicates “the circuits of the internal state storage circuit 240. Means the 9th to 16th bits of the internal state stored in "." In FIG. 4, “LSI 0”, “LSI 1”, and the like mean information for identifying an integrated circuit that is a transmission destination. That is, for example, “LSI0” means an integrated circuit identified by “LSI0”. In FIG. 4, a record whose ID is “1” is stored in the internal state storage circuit 240 including the internal state 1 if the internal state 1 of each internal state storage circuit 240 is greater than “00000000”. This means that the internal state being transmitted is transmitted to “LSI0”. In FIG. 4, a record whose “ID” is “3” is stored in the internal state storage circuit 240 including the internal state 3 if the internal state 3 of each internal state storage circuit 240 is equal to “0000001”. This means that the internal state being transmitted is transmitted to “LSI0”. In FIG. 4, “00000000” and “0000001” in “condition” usually indicate the characteristics of an input signal for which the signal processing circuit 230 performs signal processing.

  If the internal state of the signal processing circuit 230 matches a plurality of conditions defined in the processing information table of FIG. 4, the internal state processing circuit 490 determines that the “ID” is the smallest record. Sends the internal status to the defined destination.

  When the internal state processing circuit 490 detects that the internal state of the signal processing circuit 230 matches a predetermined condition, the internal state processing circuit 490 transmits a condition matching signal to the control circuit 450. The condition matching signal is a control signal indicating that the internal state of the signal processing circuit 230 matches a predetermined condition. The condition match signal includes information indicating one of the internal state storage circuits 240 in which the internal state of the signal processing circuit 230 is stored, and information indicating the transmission destination of the internal state.

  The control circuit 450 receives the condition matching signal from the internal state processing circuit 490. When receiving the condition matching signal, the control circuit 450 transmits a transmission request signal to the internal state transmission / reception circuit 370. The transmission request signal usually includes a condition matching signal received from the internal state processing circuit 490. At this time, the control circuit 450 sends a switching signal to the switching circuit 262 to connect the internal state storage circuit 240 and the internal state transmission / reception circuit 370 corresponding to the divided area where the signal processing circuit 230 performs signal processing. Send. Note that the method for controlling the switching circuit 261 of the control circuit 450 and the method for controlling the internal state transmission / reception circuit 370 are the same as those in the first specific example and the second specific example, and thus description thereof is omitted.

  The internal state determination circuit (not shown) may detect that the internal state of the signal processing circuit 230 matches the predetermined condition by the internal state processing circuit 490. In this case, the internal state determination circuit is normally provided in the internal state processing circuit 490.

  The internal state processing circuit 490 may convert the internal state to be transmitted when it is detected that the internal state of the signal processing circuit 230 matches a predetermined condition using the processing information table. Specifically, the internal state processing circuit 490 normally holds an internal state conversion table in which a conversion method of the internal state is defined, and the internal state of the signal processing circuit 230 matches a predetermined condition. Is detected, the internal state is converted using the internal state conversion table according to the transmission destination corresponding to the internal state condition used at the time of detection. The internal state conversion table is, for example, as shown in FIG. The internal state conversion table includes an internal state transmission destination and an internal state conversion method. In FIG. 5, “internal state 1”, “internal state 2”, “LSI0”, “LSI1”, and the like are the same as those in the processing information table described above, and thus description thereof is omitted. Further, in FIG. 5, a record whose “ID” is “1” indicates that “transmission destination” is “LSI1”, internal state 1 of “LSI1” is its own internal state 1, and “LSI1” "Internal state 2 of the same is set to double its own internal state 3".

  That is, the internal state processing circuit 490 determines whether or not the internal state of the signal processing circuit 230 satisfies a predetermined condition using the processing information table, and if so, the transmission destination indicated by the processing information table The internal state conversion table is used to determine whether or not conversion of the internal state to be transmitted is necessary, and if necessary, the internal state is converted.

(Specific example 4)
In this specific example, an integrated circuit including an internal state processing circuit that generates a new internal state from one or more internal states will be described. The configuration example of the integrated circuit in this specific example is the same as that in FIG. 3, and in FIG. 3, the integrated circuit 3 is the integrated circuit 5, the control circuit 350 is the control circuit 550, and the internal state processing circuit 390 is the internal state processing circuit. It is read as 590. The integrated circuit 5 includes an input processing circuit 210, a memory 220, a signal processing circuit 230, a plurality of internal state storage circuits 240, a control circuit 550, switching circuits 261 and 262, an internal state transmission / reception circuit 370, an output processing circuit 280, and an internal state processing. A circuit 590 is provided. The internal state processing circuit 590 corresponds to the determination unit 13, the control unit 14, and the internal state generation unit 16 in FIG.

  The internal state processing circuit 590 holds an internal state conversion table. The internal state conversion table is, for example, as shown in FIG. The internal state conversion table includes an internal state to be processed, a condition for performing the process, and the content of the process. In FIG. 6, “internal state 1”, “internal state 2”, “LSI 0”, “LSI 1”, and the like are the same as those in the processing information table described above, and thus the description thereof is omitted. In addition, in FIG. 6, the record whose “ID” is “1” is “if the internal state 3 in the internal state storage circuit 240 in which the internal state of the internal state 1 is stored is“ 00000001 ”. It means “overwriting with the internal state 1 in the internal state storage circuit 240 in which the internal state of the LSI 1 is stored”.

  In addition, the internal state processing circuit 590 generates a new internal state from the internal state of the signal processing circuit 230 based on the internal state conversion table. Specifically, the internal state processing circuit 590 constantly monitors the internal state stored in the internal state storage circuit 240 by the signal processing circuit 230, and the internal state stored by the signal processing circuit 230 is defined in the internal state conversion table. It is determined whether or not the conditions are met. Then, when the internal state stored by the signal processing circuit 230 matches the conditions defined in the internal state conversion table, the internal state processing circuit 590 follows the contents of the processing defined in the internal state conversion table, The internal state stored in any of the internal state storage circuits 240 is processed.

  Further, when the internal state stored in the internal state storage circuit 240 by the signal processing circuit 230 matches the conditions of a plurality of records in the internal state processing table, the internal state processing circuit 590 determines all the records defined in the matching records. Perform the process. For example, in the internal state processing table of FIG. 6, if the internal state 3 in the internal state storage circuit 240 in which the internal state of the signal processing circuit 230 is stored is “00000001”, “ID” that matches the condition Performs the process defined in the records “1” to “5”. In the process defined in the record whose “ID” is “1”, the internal state 1 of the signal processing circuit 230 is overwritten with the internal state 1 of the LSI 1. The same processing is performed for the processes defined in the records whose “ID” is “2” to “5”.

  As described above, when the internal state stored in the internal state storage circuit 240 is overwritten with the internal state received from the outside, the internal state processing circuit 590 transmits a processing detection signal to the control circuit 550. The process detection signal is a control signal indicating that the internal state stored in any of the internal state storage circuits 240 is processed. The internal state processing circuit 590 receives the internal state necessary for processing through the internal state transmission / reception circuit 370 by transmitting the processing detection signal to the control circuit 550.

  The internal state processing circuit 590 constantly monitors the internal state of the signal processing circuit 230, and determines whether the internal state of the signal processing circuit 230 matches the conditions defined in the internal state conversion table. Also good. The determination method and the processing content after the determination are the same as described above.

  The control circuit 550 receives the processing detection signal from the internal state processing circuit 590. When receiving the processing detection signal, the control circuit 550 transmits an internal state reception request signal to the internal state transmission / reception circuit 370. The process in which the control circuit 550 transmits the internal state reception request signal to the internal state transmission / reception circuit 370 and the internal state transmission / reception circuit 370 transmits the internal state transmission request signal to the outside is the same as described above. Omitted.

  As described above, the integrated circuit according to the present embodiment includes a circuit that can transmit and receive an internal state. With such a configuration, the internal state can be shared between different integrated circuits, and the input signal can be processed according to the characteristics of the input signal or the characteristics of the integrated circuit. In addition, the integrated circuit can perform processing of an integrated circuit that is slow in processing in another integrated circuit, for example. The integrated circuit can restore, for example, the internal state of the integrated circuit in which an abnormality has occurred using the internal state of another integrated circuit. Also, the integrated circuit can perform internal state transmission / reception while maintaining compatibility, for example, when the internal state is not compatible between integrated circuits that perform internal state transmission / reception. Further, the integrated circuit can generate an internal state with a better result from a plurality of internal states, for example.

  Moreover, in the said embodiment, each component may be comprised by exclusive hardware, or about the component realizable by software, it may implement | achieve by running a program. For example, each component can be realized by a program execution unit such as a CPU reading and executing a software program recorded on a recording medium such as a hard disk or a semiconductor memory.

  The present invention is not limited to the above-described embodiments, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention.

  As described above, the integrated circuit according to the present invention has an effect that the internal state can be shared between the integrated circuits, and is useful as a television apparatus or the like.

1, 2, 3, 4 Integrated circuit 11 Signal processing means 12 Storage means 13 Determination means 14 Control means 15 Transmission / reception means 16 Internal state generation means 17 Internal state processing means 151 Reception means 152 Transmission means 210 Input processing circuit 220 Memory 230 Signal processing Circuit 240 Internal state storage circuit 250, 350, 450, 550 Control circuit 261, 262 Switching circuit 270, 370 Internal state transmission / reception circuit 280 Output processing circuit 390, 490, 590 Internal state processing circuit

Claims (11)

Signal processing means for receiving a signal and processing the signal;
An integrated circuit comprising one or more storage means capable of storing an internal state, which is information relating to signal processing,
Receiving means for receiving an internal state from another integrated circuit, or transmitting means for transmitting an internal state stored in the storing means to another integrated circuit, or receiving an internal state from another integrated circuit and storing the internal state An integrated circuit comprising any of transmitting / receiving means for transmitting an internal state stored in the means to another integrated circuit. The signal processing means includes
2. The integrated circuit according to claim 1, wherein when the receiving unit or the transmitting / receiving unit receives an internal state, the signal is processed using the internal state. A determination means for determining whether or not a predetermined condition is satisfied;
When the determination means determines that a predetermined condition is satisfied, the transmission means or the transmission / reception means is instructed to transmit the internal state stored in the storage means to another integrated circuit, or the internal state Control means for instructing the reception means or the transmission / reception means to receive the signal from another integrated circuit,
The transmitting means or the transmitting / receiving means is
When an instruction is received from the control unit, the internal state stored in the storage unit is transmitted to another integrated circuit,
The receiving means or the transmitting / receiving means is
3. The integrated circuit according to claim 1, wherein the internal state is received from another integrated circuit when an instruction is received from the control means. The transmitting means or the transmitting / receiving means is
4. The integrated circuit according to claim 3, wherein a timing signal is also transmitted to the other integrated circuit when an instruction is received from the control means. The determination means includes
The integrated circuit according to claim 3 or 4, wherein when the signal processing in the signal processing means determines that the time is long enough to satisfy a predetermined condition, the predetermined condition is determined. The determination means includes
5. The integrated circuit according to claim 3, wherein when the internal state stored in the storage unit is inspected and it is determined that the internal state is abnormal, it is determined that a predetermined condition is satisfied. The determination means includes
When a characteristic of a signal to be processed by the signal processing unit is acquired and it is determined that the characteristic is a characteristic of a signal to be processed by another integrated circuit, it is determined that a predetermined condition is satisfied. The integrated circuit according to claim 3 or 4. The receiving means or the transmitting / receiving means is
It also receives timing signals
The signal processing means includes
8. The integrated circuit according to claim 1, wherein the signal is processed when the receiving unit or the transmitting / receiving unit also receives a timing signal. An internal state generating means for generating a new internal state from the internal state received by the receiving means or the transmitting / receiving means and the internal state stored in the storage means;
The signal processing means includes
The integrated circuit according to claim 1, wherein the signal is processed using an internal state generated by the internal state generation unit. 10. The integrated circuit according to claim 1, further comprising an internal state processing unit that stores only information necessary for the signal processing unit to perform processing in the storage unit as an internal state. The internal state, which is information related to signal processing, can be stored in the storage means,
A signal processing method performed using a signal processing means, a receiving means, a transmitting means, and a transmitting / receiving means,
The signal processing means comprises a signal processing step of receiving a signal and processing the signal,
A receiving step in which the receiving unit receives an internal state from another integrated circuit; or a transmitting step in which the transmitting unit transmits an internal state stored in the storing unit to another integrated circuit; or the transmitting and receiving unit. A signal processing method comprising: a transmission / reception step of receiving an internal state from another integrated circuit and transmitting the internal state stored in the storage means to the other integrated circuit.

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