JP2004341595A - Signal transfer method and signal processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing system and the like that enable efficient system operation. <P>SOLUTION: The signal processing system comprises a plurality of processor elements for, according to transfer data 32 included in signals input at constant signal input periods via a bus 200, executing signal processing between the signal input periods, setting the processed transfer data 32 in signals and outputting them to the next processor element via the bus 200. The receiving processor element 11 determines the state of the sending processor element 1 according to transfer completion notification data 33 included in a signal sent from the sending signal processor in the preceding signal input period to thereby determine whether to send transfer information data 31 to the sending processor element 1. The sending processor element 1, when sent a signal including the transfer information data 31 from the receiving processor element 11, sends the signal including the transfer data 32. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, data signal transfer in a multiprocessor system that performs real-time signal processing on an acoustic signal or the like.
[0002]
[Prior art]
Although not specifically described as a technical document, a plurality of arithmetic processing units (hereinafter, referred to as processor elements) are capable of converting data signals (hereinafter, simply referred to as data) obtained in real time by measuring physical quantities such as sound waves. There is a real-time signal processing system in which each processor element processes while transmitting (hereinafter, referred to as output) or receiving (hereinafter, referred to as input). In a certain processor element, a signal including data from the preceding processor element is received via the bus, signal processing is performed, and transmission of the signal including the processed data to the subsequent processor element is repeated at a constant cycle.
[0003]
FIG. 20 is a diagram showing a configuration of a conventional signal processing system. 101 and 110 are processor elements. Reference numeral 101 denotes a processor element at a signal transfer source (data output side), and reference numeral 110 denotes a processor element at a signal transfer destination (data input side). The means and the like denoted by reference numerals 102 to 109 described below are included in the processor element 101, and the means and the like denoted by reference numerals 112 to 119 are included in the processor element 110. is there.
[0004]
Processors 102 and 112 perform signal processing, data transfer processing, and the like. 103 and 113 are memories. The memories 103 and 113 include at least input buffers 106 and 116 as areas for storing transferred (input) data and output buffers 107 and 117 as areas for storing transferred (output) data. include. Numerals 108 and 118 denote bus controllers for controlling data output to the bus 200. 109 and 119 are I / O ports. Reference numeral 200 denotes a bus serving as a data transfer path.
[0005]
FIG. 21 is a diagram showing the flow of data between the processor elements 101 and 110. As shown in FIG. 21, data used for signal processing (hereinafter, referred to as transfer data) is output from the processor element 101 to the processor element 110.
[0006]
FIG. 22 is a flowchart showing the operation of a conventional processor element. FIG. 23 is an operation time chart of a conventional processor element. Next, the operation of the processor element centering on the processor will be described with reference to FIGS. First, initialization is performed (S101). Then, an input activation process (S102) for preparing to input transfer data from a preceding processor element (for example, the processor element 101 when viewed from the processor element 110 side), and a subsequent processor element (for example, a processor (Prepared to output the transfer data subjected to the signal processing to the processor element 110 when viewed from the element 101 side), an output start process (S103) for performing the output, and the transfer data are arithmetically processed, and the processing result is calculated. Signal processing (S104). When the signal processing (S104) ends, an input activation processing (S102) for inputting transfer data in the next cycle is performed. In this way, the input start processing (S102), the output start processing (S103), and the signal processing (S104) are repeatedly performed. Here, when the transfer data is actually input / output between the processor elements, one is set as the master processor element and the other is set as the slave processor element, and the transfer start timing of the master processor element is used. When the transfer is started, the source and destination addresses are transferred with fixed addresses.
[0007]
Then, when the output of the transfer data on the master side and the transfer input on the slave side are completed, a transfer completion interrupt is generated from the processor element on the master side. In response to the generated interrupt, each processor element interrupts the processing being performed, the input-side processor element (here, processor element 110) performs an input interrupt (S105), and the output-side processor element. The output interrupt (S106) is performed in the processor element 101 (here, the processor element 101).
[0008]
Further, in a conventional system, time alignment of data to be processed is not particularly performed, and only time information is checked during signal processing. Thus, when the time alignment is lost due to a transfer failure, the signal processing system is restarted to recover the time.
[0009]
[Problems to be solved by the invention]
The transfer method in such a conventional signal processing system has the following problems (1) to (4).
(1) In the conventional transfer method, the transfer is started at the start timing of the master processor (hereinafter, the master side) regardless of the state of the slave side processor (hereinafter, the slave side), and the slave is started by the interrupt. Transfer control is performed to determine the state of the device. For this reason, normal transfer may not be performed depending on the transfer state. Also, when the transfer cannot be performed, information relating to the transfer is obtained when the status is confirmed by notification by an interrupt after the transfer timeout detection on the master side. That is, it is determined that the transfer has failed after waiting for the timeout period.
(2) Since the transfer source and transfer destination addresses are fixed, failure processing such as temporarily changing the transfer buffer to a different buffer address cannot be performed. Therefore, system reliability decreases.
(3) In the case of a unique transfer mode in which the data of the processing result of the preceding processor is input a plurality of times and the signal processing is performed, if there is a shift in the data input, the combination of the data of the data input a plurality of times may occur. Automatic recovery was not possible because it remained offset. Therefore, in order to recover the system, the system must be restarted, and even if a temporary failure occurs, the system is stopped, and operation efficiency is reduced.
(4) In the case of adopting a transfer mode in which data of a processing result is input from a plurality of processor elements and signal processing is performed, data synchronization is performed between paths of data input from a plurality of paths (processor elements). If there is a shift (data that is not a correct combination), a sync shift can be detected. However, since it has not been determined which path is out of synchronization due to data synchronization error and which path is normal, it has not been possible to identify the synchronization loss failure path. Further, the system operation cannot be continued using only the data of the normal route without using the data of the abnormal route. For this reason, when a synchronization error occurs, the system must be restarted to recover the system. Therefore, the system stops, and the operation efficiency decreases.
[0010]
Therefore, it has been desired to realize a signal processing system capable of solving the above-described problems and operating the system efficiently.
[0011]
[Means for Solving the Problems]
Therefore, the signal transfer method according to the present invention performs signal processing during a signal input cycle based on processing data included in a signal input at a constant signal input cycle via a bus, and performs processing. In a signal processing system including a plurality of signal processing devices that include data obtained as a result in a signal and output the data to another device via a bus, the signal processing device of the transfer destination is configured to transmit the data in the previous signal input cycle. Determining the state of the source signal processing device based on the transfer completion notification data included in the signal transferred from the signal processing device, and transmitting the transfer information to the source signal processing device based on the determined state. The step of deciding whether or not to transfer the data and the transfer source signal processing device, when the signal including the transfer information data is transferred from the transfer destination signal processing device, transfer the signal including the processing data. A step of, and a step of transferring a signal including a transfer completion notification data and a signal including data for processing to complete the transfer.
In the present invention, in order to reliably exchange a signal including data for signal processing among a plurality of signal processing devices via a bus, a signal processing device of a transfer destination transmits a signal from a signal processing device of a transfer source. After determining the state of the transfer source signal processing device based on the transferred transfer completion notification data, the transfer source signal processing device transfers the signal including the transfer information data, and the transfer source signal processing device receives the transfer information data including the transfer information data. Then, after a handshake is performed between the two devices and a state is established in which signals can be exchanged, a signal including data for processing is transferred.
[0012]
Further, the signal processing system according to the present invention performs signal processing during a signal input cycle based on processing data included in a signal input at a constant signal input cycle via a bus, and performs processing. In a signal processing system composed of a plurality of signal processing devices that include data obtained as a result in a signal and output the data to another device via a bus, a signal processing device between a source signal processing device and a destination signal processing device Transfer the signals to each other, confirm each other's state based on the control data included in the signals, and then exchange signals including processing data.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a signal processing system according to a first embodiment of the present invention. 1 and 11 are processor elements which are signal processing devices. In this embodiment, reference numeral 1 denotes a signal transfer source (data output side, master side) processor element, and 11 denotes a signal transfer destination (data input side, slave side) processor element. is there. Each processor element is a signal processing node. The means and the like denoted by reference numerals 2 to 9 described below are included in the processor element 1, and the means and the like denoted by reference numerals 12 to 19 are included in the processor element 11. is there.
[0014]
Reference numerals 2 and 12 denote signal processing for calculating processing data included in the data signal (hereinafter, this data signal or data is referred to as transfer data 32) and calculating a processing result to be transferred to a subsequent processor element. It is a processor that controls means and performs various data transfer processing and the like. 3 and 13 are memories. The memories 3 and 13 include transfer completion areas 4 and 14 which are areas for storing the transfer completion notification data 33, transfer information areas 5 and 15 which are areas for storing the transfer information data 31, and transferred (input) signals. And the output buffers 7 and 17, which are areas for storing the transfer data 32 to be transferred (output) as signals. In this embodiment, the input buffer 6 is not used, but is used for inputting the transfer data 32 from the preceding stage of the processor element 1. Although the output buffer 17 is not used in this embodiment, it is used for outputting the transfer data 32 to the subsequent stage of the processor element 11. 8 and 18 are bus control units for controlling data output to the bus 200. 9 and 19 are I / O ports. Reference numeral 200 denotes a bus serving as a data transfer path.
[0015]
In this embodiment, the processor element 11 on the data input side outputs the transfer information data 31, while the processor element 1 on the data output side outputs the transfer completion notification data 33, so that the control information data Is output to perform a handshake, and after confirming that normal transfer is possible, transfer of transfer data (signal) is performed. Here, it is assumed that data can be transferred from a memory via a bus without using a processor by data transfer by DMA (Direct Memory Access). Therefore, data input / output and signal processing can be performed in parallel.
[0016]
FIG. 2 is a diagram showing a flow of data between the processor elements 1 and 11. As shown in FIG. 2, the transfer information data 31 is output from the processor element 11 on the data input side to the processor element 1 on the data output side. The processor element 1 that has received the transfer information data 31 outputs the transfer data 32. When the output of the transfer data 32 is completed, the processor 2 performs an interrupt process by an output interrupt and outputs the transfer completion notification data 33 to the processor element 11 side.
[0017]
FIG. 3 is a flowchart showing the flow of the processing of the processor. Here, the processor 12 will be described as an example, but other processors perform the same processing operation. First, the main flow will be described. The processor 12 initializes data processing before starting signal processing (S1). Then, input start processing including confirmation of the transfer completion notification data 33 stored in the transfer completion area 14 and output of the transfer information data 31 to a subsequent processor element (not shown) is performed. The transfer data 32 output from the processor element 1 is received (S2). Further, an output start-up process is performed which includes checking the transfer information data 31 stored in the transfer information area 15 and outputting the transfer data 32 stored in the output buffer 17 (S3). Further, signal processing (S4) for performing arithmetic processing on the transfer data 32 and storing the calculated processing result in the output buffer 17 is performed. When the signal processing (S4) is completed, an input activation processing (S2) for inputting the transfer data 32 in the next cycle is performed. In this way, each processor repeatedly performs the input start processing (S2), the output start processing (S3), and the signal processing (S4).
[0018]
Here, an output interrupt may be input while the processor 12 is performing the above processing (in most cases, during signal processing). In this case, the processor 12 performs an output interrupt process, and outputs the transfer completion notification data 33 via the bus control unit 18 as a part of the process (S5).
[0019]
FIG. 4 is a diagram showing a time chart of the processor element 11, particularly the processor 12 and the bus control means 18. Here, the processor 12 and the bus control means 18 of the processor element 11 will be described, but the same applies to other processor elements. The bus control means 18 has a DMA channel, and can input and output data between the memory 13 and the input / output destination without the intervention of the processor 12. Therefore, although it is necessary for the processor 12 to give an instruction to the bus control means 18, it can perform data processing (signal processing) without occupying time for data input / output. Although the cycle as the processor element 11 is started by input activation, the processor 12 performs signal processing on the basis of the time from when data is input. Therefore, in FIG. This is the data input cycle.
[0020]
Next, a transfer process according to the present embodiment will be described with reference to FIG. First, the processor 12 of the processor element 11 on the data input side performs an input activation process to prepare for data input. At this time, it is confirmed whether or not the transfer completion notification data from the processor element 1 exists in the transfer completion area 14. When the input buffer 16 is ready, the transfer information data 31 is output to the processor element 1.
[0021]
FIG. 5 is a diagram showing the format of the transfer information data 31. In the present embodiment, it is assumed that the transfer information data 31 is composed of two words. a is a node ID, which is composed of one word. This is an ID code uniquely given to each processor element in the system. b is ready for input and is composed of one word. The input ready b is code data for determining whether or not the system is ready to accept data input. If input preparation is completed, a code indicating this is set at this position and output.
[0022]
FIG. 6 is a diagram illustrating a format of the transfer completion notification data 33. In the present embodiment, it is assumed that the transfer completion notification data 33 is also composed of two words. The node IDc is the same as the transfer information data 31. d is transfer completion, which is code data for notifying the completion of data transfer. Upon completion of the input activation process, the processor 12 performs an output activation process and prepares for data output. At this time, although not shown in FIG. 1, it is confirmed whether or not the transfer information data 31 from the processor element at the subsequent stage of the processor element 11 exists in the transfer information area 15.
[0023]
The processor 12 performs signal processing, and stores the calculated processing result in the output buffer 17. Even during the signal processing, an instruction is issued to other means of the processor element 11 such as the bus control means 18 as necessary. In the next data input cycle, it is necessary to input / output the transfer data 32 to be processed next, and perform signal processing on the new transfer data 32. Therefore, the signal processing needs to be completed within that cycle. This is the same for other processor elements including the processor element 1.
[0024]
On the other hand, the processor element 11 inputs data from the processor element 1 via the bus control means 18 and stores the data in the input buffer 16. When the data input is completed, the transfer data 32 of the processing result stored in the output buffer 17 is output to the subsequent processor element (not shown) via the bus 200.
[0025]
After terminating the data output, the bus control means 18 gives an output interrupt to the processor 12. At the time of the output interrupt processing, the processor 12 causes the bus control means 18 to output the transfer completion notification data 33 to the subsequent processor element. Further, the transfer information data 31 held in the transfer information area 15 is cleared to prepare for the next input of the transfer information data 31.
[0026]
As described above, according to the first embodiment, between the transfer source processor element 1 and the transfer destination processor element 11, the transfer information data 31 and the transfer completion notification data which are control information of each other. After exchanging data 33 with each other and performing a handshake to determine each other's state, each processor element can transfer and accept the transfer data 32. Therefore, if the transfer information data 31 is not input, the transfer data 32 is not output from the processor element 1, so that a situation where transfer cannot be performed normally can be avoided. As a result, it is not necessary to perform useless bus transfer, and the use of the bus is refrained and the bus is used for another bus use request, so that the bus use efficiency is improved. Further, the state of the transfer destination processor element 11 can be detected before data transfer.
[0027]
Embodiment 2 FIG.
FIG. 7 is a diagram illustrating a configuration of a signal processing system according to the second embodiment of the present invention. 7, the processor element 11A differs from the processor element 1 in having a memory 13A having two input buffer areas of input buffers 16A and 16B. Here, the input buffer 16B is a spare input buffer. In the present embodiment, only the memory 13A of the processor element 11A has two input buffer areas. However, the processor element 1 may have the same configuration. Further, the input buffer is not limited to two areas, and may have three or more areas.
[0028]
FIG. 8 is a diagram illustrating a format of transfer information data 31 according to the second embodiment. The first embodiment is different from the first embodiment in that the transfer information data 31 is composed of three words and has an input buffer address e that indicates to which input buffer data can be input. Is different from the transfer information data 31.
[0029]
Next, the operation will be described. The processor element 11A outputs the transfer information data 31 at the time of the input activation processing. At this time, the processor element 11A selects one input buffer ready to store the transfer data 32. Here, as this selection method, a spare input buffer 16B may be selected only when there is a failure, or two input buffers may be treated equally and switched and selected each time. You may. The address of the memory space allocated to the input buffer area is included in the transfer information data 31 and output to the processor element 1.
[0030]
On the other hand, the processor element 1 determines the address specified by the processor element 11A based on the transfer information data 31 stored in the transfer information area 5, and the transfer data 32 is stored in the input buffer 16A or 16B of that address. An address is designated and the transfer data 32 is output so as to be stored.
[0031]
As described above, according to the second embodiment, since the data transfer is performed based on the address of the input buffer designated by the processor element 11A on the data input side (transfer destination), a failure occurs. Even when one input buffer cannot be used, by specifying another input buffer, it is possible to flexibly cope with the transfer and reception of the transfer data 32 between the processor elements. Further, by using the transfer information data 31 as the input buffer switching notification, the transfer source processor element can store the fixed address of the transfer destination input buffer, or can store the transfer destination input buffer to be transferred next. No need to manage. Further, since the processor element 11A on the data input side (transfer destination) manages the input buffer, it is possible to control not to use the input buffer which has become unusable due to some failure. As described above, even if a failure occurs in a part of the input buffer in the failure related to the buffer control, it is possible to avoid the failure, so that the system reliability can be improved.
[0032]
Embodiment 3 FIG.
FIG. 9 is a diagram showing a data flow between the processor elements 1 and 11A according to the third embodiment of the present invention. The configuration of the system is the same as that described in the second embodiment. In FIG. 9, while the processor element 11A serving as the transfer destination performs one signal processing and outputs the transfer data 32, the processor element 1 outputs the transfer data 32 a plurality of times (in the present embodiment, the transfer data 32 is used twice. A special transfer operation (hereinafter, referred to as a rate down, and a case of inputting twice as in the present embodiment is referred to as a rate reduction by 2) in which each transfer data 32 is referred to as 32A and 32B. In the present embodiment, the divide-by-2 rate reduction is used as a management unit of the output of the transfer data 32. In the case of the divide-by-2 rate, the period is twice as long as the data input period of the preceding processor element, and the input of the transfer data 32 is performed twice while the input activation process is performed once.
[0033]
FIG. 10 is a diagram showing a time chart of the processor element 11A, particularly the processor 12.
[0034]
FIG. 11 is a diagram illustrating a format of transfer information data 31 according to the third embodiment. The format is changed so that a transfer parameter f is added to the transfer information data 31 of the second embodiment. The transfer parameter f is, for example, code data indicating a transfer mode such as a normal transfer or a rate-down transfer. Here, if the transfer data 32 that is input a plurality of times can be input to the input buffer having a continuous structure, the first input buffer address e may be specified, and therefore the transfer information data in the format of FIG. 31 may be output. On the other hand, when the transfer data 32 that is input a plurality of times is input to the input buffer that is not continuous, a plurality of input buffer addresses e for inputting the respective transfer data 32 are specified as in the format of FIG. Then, the transfer information data 31 is output. Whether to configure the transfer information data 31 in the format of FIG. 11A or the format of FIG. 11B may be arbitrarily determined according to the transfer mode.
[0035]
On the other hand, the processor 2 of the processor element 1 serving as the data output side (transfer source) confirms whether or not the transfer information data 31 from the processor element 11A exists in the transfer information area 5. At this time, the transfer is performed. Based on the code data of the parameter f, it is determined that the transfer data 32 to the processor element 11A is to be output at a frequency-divided-by-2 rate. Further, the input buffer that outputs the transfer data 32 is also determined based on the input buffer address e.
[0036]
Thereafter, the processor element 1 outputs the first transfer data 32A via the bus 200 and is stored in the input buffer 16A or 16B of the processor element 11A. When the output of the transfer data 32A is completed, the bus control means 8 gives an output interrupt to the processor 2, and when the processor 2 receives the output interrupt, it performs an output interrupt process. After the transfer data is output, the transfer completion notification data is normally output to the processor element 11A in the output interrupt processing after the transfer of the transfer data 32A is completed. , The transfer completion notification data 33 is output for each data output management unit. In the divide-by-2 rate, the transfer data 32A is output for the first time, and the transfer completion notification data 33 is output by an output interrupt process performed after the output of the transfer data 32B, which is the second output.
[0037]
FIG. 12 is a time chart for explaining the operation when a data shift occurs. This is an operation in the case where data transfer is performed from the processor element 1 to the processor element 11A at a rate reduced by two based on FIG. As described with reference to FIG. 9 showing the data flow, a combination of the transfer data 32A and the transfer data 32B is input to the processor element 11A as input data within the data input cycle of the processor element 11A.
[0038]
In the processor operation time chart in FIG. 12, the transfer information data 31 is output from the processor element 11A to the processor element 1 during the first data input cycle of the processor element 1, and the processor element 1 receives the transfer information data 31. , Reads that the transfer mode of the input ready b and the transfer parameter f of the transfer destination processor element 11A is the divide-by-2 rate, and outputs the transfer data 32A to the processor element 11A. This transfer is completed normally and input to the processor element 11A.
[0039]
In the second cycle of the data input cycle of the processor element 1, the transfer data 32B is abnormal in the transfer data output, and a data shift occurs, and the data combination of the transfer data output to the processor element 11A is broken. I have. At this time, the output interrupt from the processor element 1 indicates a transfer error, and the transfer error notification data 33 output to the processor element 11A is output with the data transfer completion code of the transfer completion d set to the output error. . The processor element 11A recognizes from the transfer completion notification data 33 that the data input in the current data input cycle is abnormal. In other words, the processor element 1 of the transmission source performs data management for each output twice for the transfer mode of the divide-by-2 rate, and outputs the transfer completion notification data 33. For this reason, the processor element 11A is notified of the data input result for each data input cycle of the processor element 11A, and the fact that a data shift has occurred and the transfer data combination has been destroyed indicates that the transfer data of the current data input cycle is abnormal. In the form. The processor element 11A determines whether the transfer data is normal or abnormal for each data input cycle based on the transfer completion notification data 33 without being aware of the data combination. In this way, by checking the data input state for each data input cycle and handling the transfer data, even if a data shift occurs, only the data input cycle becomes an input error and does not affect other cycles. Works.
[0040]
The third and fourth cycles of the data input cycle of the processor element 1 indicate that the data transfer was normally performed, the transfer data 32A and the transfer data 32B were respectively transferred, and were transferred in a correct combination of the transfer data. As described above, the processor element 11A checks the data input for each input cycle, so that the data is normally input without dragging the data shift.
[0041]
As described above, according to the third embodiment, the output of the transfer information data 31 from the processor element 11A to the processor element 1 is included in the transfer information data 31 including the transfer parameter f indicating the transfer mode. (In the case of the third embodiment, every time the transfer data 32 is transferred twice), so that when the transfer is performed at a reduced rate, the input data combination of the transfer data 32 is shifted. Occurs, only the combination of the transfer data 32 in the cycle becomes erroneous data, and the transfer data 32 in the next cycle is automatically restored to the correct combination. For this reason, it is not necessary to restart the system for recovery, and it is possible to prevent a decrease in system operation efficiency.
[0042]
Embodiment 4 FIG.
FIG. 13 is a diagram illustrating a configuration of a signal processing system according to the fourth embodiment of the present invention. In FIG. 13, the components having the same reference numerals as those in FIG. 7 perform the same operations as those described in the first and second embodiments, and thus the description is omitted. 21 is a processor element. The configuration of the processor element 21 is the same as that of the processor element 1. However, since the bus 200 cannot be occupied at the same time, the timing at which the bus control means 28 outputs the transfer data 32 is different from that of the bus control means 8. Further, the processor element 1 and the processor element 21 count the time of the transfer data 32, which is a material for determining data synchronization. Here, the time is constituted by, for example, an integer value of 0 to n (0 to 7 in the present embodiment; hereinafter, referred to as a time value), and circulates (the value of 7 returns to 0 after 7). Shall be. Then, the time is made to correspond to the order of the transfer data 32 to be processed and output. This time is included in the transfer completion notification data 33 and output as time data g.
[0043]
FIG. 14 is a diagram illustrating a format of the transfer completion notification data 33 according to the fourth embodiment. It is assumed that the transfer completion notification data 33 of the present embodiment is composed of three words to which time data g is added. The time data g is assumed to be composed of values of 0 to 7 as described above.
[0044]
When the transfer data 32 is output from a plurality of processor elements in one data input cycle, and the transfer data 32 is processed (hereinafter, this transfer form is referred to as "merging"), the transfer data 32 must be processed in a correct combination with time synchronization. For example, the signal processing of the subsequent processor element and the processing result are greatly affected. Therefore, in the present embodiment, the transfer completion notification data 33 that is control information includes time data, and the transfer destination processor element determines whether or not the transfer destination processor element is in the processor element or path based on the time data from each processor element. It is determined whether or not an abnormality due to a synchronization shift has occurred due to a failure, and whether or not the combination of the transfer data 32 is correct.
[0045]
FIG. 15 is a diagram illustrating the flow of data among the processor elements 1, 11A and 21 according to the fourth embodiment. The processor element 11A outputs the transfer information data 31 to the processor element 1 and the processor element 21, respectively. Then, the transfer data 32 and the transfer completion notification data 33 are output from the processor element 1 and the processor element 21, respectively.
[0046]
FIG. 16 is a diagram illustrating a flowchart of a process of confirming the transfer completion notification data 33 at the time of input activation of the processor 12. Here, the main processing performed by the processor 12 is as shown in the flowchart of FIG. At the time of the input activation processing, the transfer completion notification data 33 is checked, but the processor 12 starts the processing of generating the expected value. The expected value is the value of the time data g to be written when confirming the completion notification data. Here, the time value is a cyclic integer value that is an integer from 0 to n and is incremented by a constant value every time data is transferred, and is counted by the difference when the increased value becomes n or more because it is for synchronization purposes. Therefore, the expected value is also a circulating integer value. Previous expected value (time data) X _m-1 And the sum of the increment value ΔX (which is 1 in the present embodiment) is n or less (X _m-1 + ΔX ≦ n) (S11), current expected value X _m To X _m-1 + ΔX (S12). If not less than n (if greater than n, (X _m-1 + ΔX> n)), the current expected value X _m Is X _m-1 + ΔX−n−1 (S13). After generating the expected value, the processor 12 compares the expected value with the time value and determines whether they match (S14). If normal, the time value should match the expected value. Here, if the values are not the same, it is determined that the synchronization has been lost. If it is determined that a synchronization shift has occurred, the node IDa of the processor element is stored in the storage unit 13A (S15).
[0047]
It is determined whether or not the above operation has been performed for all output-source processor elements (transfer paths) of the transfer data 32 input to the processor 11A (S16). It is determined whether or not a synchronization shift has occurred with respect to the transfer path. When the determination as to whether or not synchronization has occurred in all transfer paths is completed, and it is determined that synchronization has occurred in a certain transfer path (S17), error processing is performed (S18).
[0048]
FIG. 17 is a diagram illustrating a flowchart of the error processing. First, the processor 12 counts up the number of times of occurrence of an abnormality (the number of occurrences of synchronization deviation) for each node ID (for each processor element) based on the node ID stored in the storage unit 13A (S18A). Then, an abnormality of the transfer data 32 for each node ID is recognized (S18B). Actually, the application program for performing the signal processing is made to recognize (notify) that the processing is performed by the transfer data 32 in which the synchronization shift has occurred. Then, it is determined whether or not the number of occurrences of the abnormality is a predetermined threshold value k (or more). If the number of occurrences of the abnormality is smaller than the threshold value k, the error processing ends. If it is determined that the number of times of occurrence of the abnormality is equal to or larger than the threshold value k (S18C), the disconnection process is performed (S18D), and the transfer information data 31 is not output to the processor having the corresponding node ID, so that the error processing is performed. To end. As a result, the transfer information data 31 is not stored in the transfer information area of the processor element subjected to the disconnection processing, and the handshake is not performed, so that the transfer data 32 cannot be output. In this way, separation is attempted.
[0049]
Further, in FIG. 16, it is determined that no synchronization shift has occurred, and the transfer information data 31 is output to the processor element for which the disconnection processing by the error processing has not been performed (S19), and the processing ends.
[0050]
FIG. 18 is a diagram illustrating a flowchart of the transfer completion notification data output. On the other hand, in the transfer-source processor element 1 or 21, the processor 2 or 22 performs the output interruption processing, and the bus control means 8 or 28 outputs the transfer completion notification data 33. The time data g is set (S21). Further, it determines which one of the code data indicating whether the data transfer is completed normally, the transfer is abnormal, or the transfer data 32 is abnormal, and sets the transfer completion d from the code data (S22). Then, the ID code inherent to the processor is set as the node IDc (S23), the transfer completion notification data 33 is output to the processor element 11A (S24), and the process ends. Here, if the bus 200 is occupied by another processor, the output of the transfer completion notification data 33 is in a waiting state.
[0051]
FIG. 19 is a diagram showing a time chart of the processor elements 11A, 1 and 21. Here, the output process of the processor element 1 and the accompanying input process of the processor element 11A will be described. FIG. 19 shows a state in which the transfer data 32 output from the processor element 1 is out of synchronization in the second and third cycles. The circled numbers described in FIG. 19 are the same as those shown in FIG. Based on the flowcharts of FIG. 19 and FIGS. 15 to 18, the processing in a case where a synchronization error has occurred will be described more specifically. Here, it is assumed that the threshold value k of the number of times of occurrence of abnormality is k = 2.
[0052]
In the transfer source processor element 1, an output activation process is performed. It is determined whether the transfer information data 31 from the processor element 11A exists in the transfer information area 15. Then, based on the code data of the input ready b, it is confirmed that the processor element 11A is ready to accept. Further, based on the code data of the transfer parameter f, it is determined that the transfer mode is the merge. A similar output activation process is performed for the processor element 21.
[0053]
Then, the transfer data 32 is output by the bus control means 8 of the processor element 1 based on the input buffer address e. When the output of the transfer data 32 is completed, the processor 2 performs an output interrupt process, and performs a transfer completion notification data 33 output process as a part of the process. By this processing, the transfer completion notification data 33 to which the time data g and the transfer completion d indicating the transfer state are added is output to the processor element 11A and stored in the transfer completion area 14. If the state is normal, the output processing of the transfer data 32 as described above is periodically performed for the processor elements 1 and 21.
[0054]
On the other hand, the processor element 11A serving as the transfer destination outputs the transfer information data 31 to the processor elements 1 and 21 during the input activation processing. At this time, code data indicating the merge is added to the transfer parameter f. After performing the output activation process for the subsequent processor element, the transfer data 32 is input from the processor elements 1 and 21, respectively. Here, the transfer data 32 transferred from the processor element 1 is stored in the input buffer 16A, and the transfer data 32 transferred from the processor element 21 is stored in the input buffer 16. When the input of the transfer data 32 is completed, the transfer completion notification data 33 is output from the processor elements 1 and 21, respectively.
[0055]
The processor 12 of the processor element 11A checks the transfer completion data at the time of the next input activation processing, and at this time, creates an expected value as shown in FIG. In the first cycle, the expected values are each “0”. Since the time data g included in the transfer completion notification data 33 output from the processor elements 1 and 21 is also “0”, the expected value and the time value of the time data g are compared and coincide with each other. Therefore, it is determined that there is no out-of-sync.
[0056]
For the second cycle, the expected values are “1”, respectively. On the other hand, the value of the time data g included in the transfer completion notification data 33 from the processor element 1 is “2”. The processor 12 performs error processing, and stores the number of times of occurrence of abnormality as 1 in association with the node ID of the processor element 1. In this case, since the number of occurrences of the abnormality is 1 <k (= 2), the processor 2 determines (determines) it, and returns to the normal processing as it is.
[0057]
For the third cycle, the expected values are each “2”. On the other hand, the value of the time data g included in the transfer completion notification data 33 from the processor element 1 is “3”. The processor 12 performs the same processing as in the second cycle. However, since the number of times of occurrence of the abnormality becomes 2 and becomes the same value as the threshold value k, the output of the transfer information data 31 to the processor element 1 is performed. It stops and performs the disconnection processing of the processor element 1. Thus, the output of the transfer information data 31 is performed only to the processor element 21.
[0058]
Further, in the processor 12, in the second cycle, the signal processing is performed using the transfer data 32 in which the synchronization shift has occurred, so that the transfer data 32 output to the subsequent processor element becomes abnormal. Therefore, regarding the transfer completion notification data 33 output to the subsequent processor element at the time of the output interrupt, the time data g is normally added, but the transfer completion d is output by code data indicating that the transfer data 32 is abnormal. I do.
[0059]
In the third period, the processor element 1 whose transfer information data 31 does not exist in the transfer information area cannot output the transfer data 32 due to the separation processing.
[0060]
As described above, according to the fourth embodiment, the time data g is added to the transfer completion notification data 33 in the case of merging to process signals from a plurality of processor elements within one cycle, and The processor element 11A determines the expected value, compares the expected value with the value of the time data g, determines the synchronization deviation, and notifies the subsequent processor element of the occurrence of the synchronization deviation. Since the disconnection process is performed when the number of occurrences exceeds a certain number of times, in the case of a temporary failure that recovers before the disconnection process is executed even if a synchronization loss occurs, the system will be The system can be operated as it is without resetting, and a decrease in the operation efficiency of the system can be prevented. Further, even when a failure such as the disconnection process continues, the load on the bus can be reduced without causing useless transfer by the disconnection operation.
[0061]
Embodiment 5 FIG.
Although the above embodiments have been described on the assumption that signal processing is performed in real time, the present invention can be applied even to signal processing not in real time.
[0062]
【The invention's effect】
As described above, according to the present invention, the transfer destination signal processing device determines the state of the transfer source signal processing device based on the transfer completion notification data, and based on the determination, the transfer source signal processing device The transfer information data is transferred, and when the signal containing the transfer information data is transferred, the transfer source signal processing device transfers the signal containing the data for processing. After confirming that a signal can be exchanged, a normal signal can be exchanged. For this reason, it is not necessary to generate a useless bus cycle, so that useless use of the bus can be prevented, and the bus use efficiency is improved. Further, the transfer source processor element can detect the state of the transfer destination processor element before data transfer.
[0063]
Further, according to the present invention, after confirming each other's state based on control data between the transfer source signal processing device and the transfer destination signal processing device, exchange of signals including processing data is performed. So that handshake is performed with each other to confirm that signals can be exchanged reliably before normal signals can be exchanged, unnecessary signal transfer due to abnormal signals is prevented, and bus use efficiency is reduced. Can be raised.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a signal processing system according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a flow of data between processor elements 1 and 11;
FIG. 3 is a diagram illustrating a flowchart illustrating a flow of a process of a processor 2.
FIG. 4 is a diagram showing a time chart of the processor element 11, in particular, the processor 12 and the bus control means 18.
FIG. 5 is a diagram illustrating a format of transfer information data 31.
FIG. 6 is a diagram illustrating a format of transfer completion notification data 33.
FIG. 7 is a diagram illustrating a configuration of a signal processing system according to a second embodiment of the present invention.
FIG. 8 is a diagram illustrating a format of transfer information data 31 according to the second embodiment.
FIG. 9 is a diagram showing a data flow between processor elements 1 and 11A according to a third embodiment of the present invention.
FIG. 10 is a diagram showing a time chart of the processor element 11A, particularly the processor 12 and the bus control means 18.
FIG. 11 is a diagram illustrating a format of transfer information data 31 according to the third embodiment.
FIG. 12 is a time chart illustrating an operation when a data shift occurs.
FIG. 13 is a diagram illustrating a configuration of a signal processing system according to a fourth embodiment of the present invention.
FIG. 14 is a diagram illustrating a format of transfer completion notification data 33 according to the fourth embodiment.
FIG. 15 is a diagram showing a data flow between processor elements 1, 11A and 21 according to a fourth embodiment.
16 is a diagram illustrating a flowchart of a process of confirming transfer completion notification data 33 at the time of input activation of the processor 12. FIG.
FIG. 17 is a diagram illustrating a flowchart of an error process.
FIG. 18 is a diagram illustrating a flowchart of output of transfer completion notification data.
FIG. 19 is a diagram showing a time chart of the processor elements 11A, 1, 21;
FIG. 20 is a diagram showing a configuration of a conventional signal processing system.
FIG. 21 is a diagram showing a flow of data between processor elements 101 and 110.
FIG. 22 is a flowchart showing the operation of a conventional processor element.
FIG. 23 is an operation time chart of a conventional processor element.
[Explanation of symbols]
1, 11, 11A, 21, 101, 110 processor elements
2, 12, 22, 102, 112 processors
3, 13, 13A, 23, 103, 113 Memory
4, 14, 24 Transfer complete area
5, 15, 25 Transfer information area
6, 16, 16A, 16B, 26, 106, 116 input buffer
7, 17, 27, 107, 117 output buffer
8, 18, 28, 108, 118 Bus control unit
9, 19, 29, 109, 119 I / O ports
200 bus

Claims (6)

The signal processing is performed during the signal input cycle based on the processing data included in the signal input at a constant signal input cycle via the bus, and the data resulting from the processing is included in the signal. In a system composed of a plurality of signal processing devices that output to a device via a bus,
A step in which the transfer destination signal processing device determines the state of the transfer source signal processing device based on transfer completion notification data included in a signal transferred from the transfer source signal processing device in the previous signal input cycle. ,
A step of determining whether to transfer transfer information data to the transfer source signal processing device based on the determined state,
The signal processing device of the transfer source, when a signal including transfer information data is transferred from the signal processing device of the transfer destination, a step of transferring a signal including the data for processing,
Transferring the signal including the transfer completion notification data when the transfer of the signal including the processing data is completed. The signal processing is performed during the signal input cycle based on the processing data included in the signal input at a constant signal input cycle via the bus, and the data resulting from the processing is included in the signal. In a signal processing system composed of a plurality of signal processing devices that output to a device via a bus,
A signal is transferred between the signal processing device of the transfer source and the signal processing device of the transfer destination, and after confirming each other's state based on the control data included in the signal, the data for processing is processed. A signal processing system for exchanging signals including: The signal processing is performed during the signal input cycle based on the processing data included in the signal input at a constant signal input cycle via the bus, and the data resulting from the processing is included in the signal. In a signal processing system composed of a plurality of signal processing devices that output to a device via a bus,
The destination signal processing device determines the state of the source signal processing device based on the transfer completion notification data included in the signal transferred from the source signal processing device in the previous signal input cycle, Determine whether to transfer the transfer information data to the transfer source signal processing device,
The transfer source signal processing device, when a signal including transfer information data is transferred from the transfer destination signal processing device, transfers the signal including the processing data, and after the transfer is completed, the transfer completion notification A signal processing system for transferring a signal including data. When the signal processing device has a plurality of areas for temporarily storing the transferred data for processing,
4. The signal processing system according to claim 3, wherein the transfer destination signal processing device includes data for designating an area for storing the data for processing included in the transfer information data and transfers the data. 4. The signal processing apparatus according to claim 3, wherein the transfer destination signal processing device includes data for designating a transfer mode for transferring the signal including the processing data, included in the transfer information data, and transfers the signal. system. In a transfer mode in which the signal processing device of the transfer destination receives a signal including the plurality of data for processing transferred from the plurality of transfer source processing devices and performs signal processing,
The plurality of transfer-source processing devices transfer a signal including the data for processing to be transferred in each cycle with a number indicating a time, and transfer the signal.
The transfer destination signal processing device determines whether the combination of the data for each processing is correct based on the number, and if the combination is not correct, specifies the signal path that has caused the synchronization shift, and determines the predetermined number of times. 4. The signal processing system according to claim 3, wherein the signal transfer including the processing data from the signal path is stopped when the synchronization deviation from the signal path is determined.

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