JP5082147B2 - Multi-node system, inter-node switch, and data relay method - Google Patents

Description

  The present invention relates to a multi-node system, an inter-node switch, and a data relay method, and more particularly to a multi-node system, an inter-node switch, and a data relay method when a failure occurs in a node.

  There is known a multi-node system in which a plurality of computers (nodes) configured to include a processor and a shared memory are connected via an inter-node switch. The multi-node system improves the performance of the entire system by distributing processing using a plurality of nodes. In a multi-node system that operates a plurality of nodes, it is desired to solve the failure processing operation in a short time when a failure occurs in any of the nodes.

  A general operation when a failure occurs in a node constituting the multi-node system will be described with reference to FIGS. A configuration example of a multi-node system having a local node, a remote node, and an inter-node switch will be described with reference to FIG.

  The local node issues command processing information (request information). In addition, the remote node acquires command processing information issued in the local node. Furthermore, the remote node executes command processing based on the acquired command processing information.

  The core 110 of the local node 100 issues request information. The request information is decomposed for each block in the instruction decomposition unit 121 of the RCU (inter-node control unit) 120. The decomposed block is output to the memory 130. When the instruction decomposition unit 121 completes the decomposition of the request information, information regarding the block decomposition number is stored in the block decomposition number holding unit 123. The instruction processing information broken down into blocks is loaded with data from the memory 130 to become load data. The load data is output from the data transfer unit 122 to the inter-node switch 200 in units of blocks. The inter-node switch 200 transfers the acquired load data to the remote node 300. The load data is stored in the memory 320 of the remote node 300. When the load data is stored in the memory 320, the RCU 310 outputs a block reply that is a load data storage completion report to the local node 100 via the inter-node switch 200.

  The local node 100 counts the number of acquired block replies in the block reply number counter 124, and the comparison unit 125 compares this value with the value held in the block decomposition number holding unit 123. When the value of the block reply number counter 124 matches the value of the block decomposition number holding unit 123, the end status generation unit 126 issues an end status. Further, the end status generation unit 126 writes the end status in the memory 130. Thereby, the process regarding the request information ends.

  In the case of normal processing, it moves as described above. Further, FIG. 8 shows a processing sequence among the local node, the inter-node switch, and the remote node in normal processing. An arrow indicated by a solid line is a block, and an arrow indicated by a broken line is a block reply. However, when a failure occurs in the remote node 300, all block replies are not returned from the remote node 300 to the local node 100. FIG. 9 shows a processing sequence when a failure occurs. Therefore, the values of the block reply number counter 124 and the block decomposition number holding circuit 123 do not match, and the end status generation circuit 126 cannot issue an end status. In preparation for such a case, the local node 100 starts a timer from the point in time when block decomposition starts in the instruction decomposition unit 121. If the request processing does not end even if the timer elapses for a predetermined time or more, the timeout detection circuit 16 detects a timeout, and the end status generation unit 126 forcibly issues an end status and ends the request processing.

  In such a case, the local node 100 cannot end the instruction processing information until it detects a timeout. Therefore, it takes a lot of time for failure processing, and the core 110 cannot process subsequent instruction information.

  In order to cope with such a problem, Patent Document 1 discloses a bus failure processing system. The bus failure processing system in Patent Document 1 includes a system bus, an input / output control device, and a bus controller connected to the two. In the bus failure processing system, a request for processing to be executed from the system bus to the input / output control device is output via the bus controller. At this time, if the bus controller detects a failure related to the input / output control device, the bus controller outputs pseudo response data in response to the processing request to the system bus to notify that the failure has occurred in the input / output control device. To do. Thereby, the bus system can detect at an early stage that a failure has occurred in the input / output control device.

  Patent Document 2 discloses that in a multi-node system, when a failure in another node is notified, the data transferred to the other node is discarded in the own node.

Japanese Patent No. 2663896 JP 2006-178786 A

  However, the following problems arise when the techniques disclosed in Patent Documents 1 and 2 are used. The technology disclosed in Patent Document 1 notifies a failure related to an input / output device by outputting pseudo response data from a bus controller to a system bus. Therefore, when the processor connected to the system bus obtains the response signal output when the data transfer is normally performed from the input / output device and the pseudo response data output from the bus controller, It is necessary to execute different processing depending on the signal or data to be acquired. Thus, when a plurality of circuits that operate different processes are provided, there arises a problem that the circuit scale increases. Similar problems occur in a configuration in which data is discarded when a failure notification is made as in Patent Document 2.

  The present invention has been made to solve such a problem, and provides a multi-node system, an inter-node switch, and a data relay method capable of ending failure processing at an early stage without increasing the circuit scale. For the purpose.

  A multi-node system according to a first aspect of the present invention includes: a first node that transmits instruction processing information; an inter-node switch that transfers instruction processing information transmitted by the first node to a second node; The first node comprises: an instruction decomposition unit that decomposes the instruction processing information into a plurality of blocks; a transmission unit that transmits the plurality of blocks to the inter-node switch; and a block decomposed by the instruction decomposition unit And a determination unit that determines whether or not transmission processing of the plurality of blocks has been normally completed based on the number of blocks and the number of response signals for the plurality of blocks transmitted from the second node. The inter-node switch generates the response signal instead of the second node and transmits it to the first node when a failure occurs in the second node. A.

  An inter-node switch according to a second aspect of the present invention includes a data transmitting / receiving unit that receives command processing information transmitted by a first node and transfers the command processing information to a second node; A response signal generator for generating, instead of the second node, response signals for a plurality of blocks generated and transmitted by disassembling instruction processing information in the first node when a failure occurs in the node Are provided.

  A data relay method according to a third aspect of the present invention includes receiving a command processing information transmitted by a first node and transferring the command processing information to a second node; and the second node A step of detecting a failure occurrence in step, a step of receiving a block generated by decomposing instruction processing information in the first node after detecting the occurrence of the failure, and a response signal to the block. And generating the response signal in place of the first node, and transmitting the response signal to the first node.

  According to the present invention, it is possible to provide a multi-node system, an inter-node switch, and a data relay method capable of ending failure processing at an early stage without increasing the circuit scale.

1 is a configuration diagram of a multi-node system according to a first exemplary embodiment; 1 is a detailed configuration diagram of a multi-node system according to a first exemplary embodiment; FIG. 3 is a sequence diagram of a multi-node system when a failure occurs according to the first embodiment. 6 is a flowchart of an inter-node switch when a failure occurs according to the first exemplary embodiment. FIG. 3 is a detailed configuration diagram of a multi-node system according to a second exemplary embodiment. FIG. 6 is a sequence diagram of a multi-node system when a failure occurs according to a second embodiment. It is a block diagram of a multi-node system that performs timeout control when a failure occurs. It is a sequence diagram of a multi-node system at the normal time. FIG. 6 is a sequence diagram of a multi-node system that performs timeout control when a failure occurs.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the multi-node system according to the first exemplary embodiment of the present invention will be described with reference to FIG. The multi-node system in this embodiment includes a node 10, an inter-node switch 20, and a node 30.

  First, a configuration example of the node 10 will be described. The node 10 is a node that transmits instruction processing information. The node 30 is a node that receives the instruction processing information and executes the instruction processing. The inter-node switch 20 is disposed between the node 10 and the inter-node switch 20, and is connected to both nodes. Here, although the nodes 10 and 30 are shown as nodes connected to the inter-node switch 20 in this figure, a plurality of two or more nodes may be connected to the inter-node switch 20. The command processing information is processing contents executed in the node 30. For example, the command processing information is information instructing execution of data copying, data calculation, and the like in the node 30. Further, the command processing information may include a plurality of processing contents executed in the node 30.

  The node 10 includes an instruction decomposition unit 11, a transmission unit 12, and a determination unit 13. The instruction decomposition unit 11 decomposes instruction processing information output from a processor or the like in the node 10 into a plurality of blocks. The instruction decomposing unit 11 may decompose the instruction processing information into blocks for each predetermined number of bits, or may be decomposed into blocks according to the processing content included in the instruction processing information. The instruction decomposing unit 11 outputs the decomposed blocks to the transmitting unit 12. Further, the instruction decomposing unit 11 outputs information regarding the number of decomposed blocks to the determining unit 13.

  The transmission unit 12 transmits the plurality of blocks acquired from the instruction decomposition unit 11 to the inter-node switch 20 in units of blocks. The plurality of blocks transmitted to the internode switch 20 are transferred to the node 30. When the node 30 normally receives a plurality of blocks transferred from the inter-node switch 20, the node 30 outputs a response signal to the node 10 for each received block. Alternatively, the node 30 outputs a response signal to the node 10 every time a certain number of blocks are acquired.

  The determination unit 13 counts the number of response signals output from the node 30. Further, the determination unit 13 includes information on the number of decomposed blocks notified from the instruction decomposition unit 11 (hereinafter referred to as decomposition block number) and the number of response signals output from the node 30 (hereinafter referred to as response signal number, And). Thereby, the determination unit 13 determines whether or not the transmission processing of the plurality of blocks transmitted from the transmission unit 12 has ended normally. For example, the determination unit 13 determines that the transmission processing of the plurality of blocks transmitted from the transmission unit 12 has been normally completed when the number of decomposed blocks and the number of response signals match. It may be determined that the process is in progress. Alternatively, when the node 10 acquires one response signal for a predetermined number of blocks, the determination unit 13 performs transmission processing even when the number of decomposed blocks does not match the number of response signals. It can be determined that the process has been completed normally.

  For example, a case will be described in which one instruction processing information is decomposed into 10 blocks by the instruction disassembling unit 11 and one response signal is acquired for every five blocks. In this case, the instruction decomposition unit 11 notifies the determination unit 13 that the number of decomposition blocks is two. The node 30 is set in advance to output one response signal for every five blocks. In this case, the determination unit 13 can determine that the transmission process is normally completed when the number of response signals is two. Here, the instruction decomposition unit 11 may notify the determination unit 13 that the number of decomposition blocks is 10, and the determination unit 13 may convert that the number of response signals to be acquired is two. The number of response signals that need to be shared between the node 10 and the node 30 may be preset in the instruction decomposition unit 11 and the node 30, and the response signal is sent to the block output from the transmission unit 12. The number may be set and output to the node 30.

  Subsequently, a configuration example of the inter-node switch 20 will be described. The inter-node switch 20 includes a response signal generation unit 21 and a data transmission / reception unit 22. When no failure has occurred in the node 30, the data transmission / reception unit 22 transfers the plurality of blocks output from the transmission unit 12 to the node 30. In addition, the response signal transmitted from the node 30 is transferred to the node 10. When a failure occurs in the node 30, the response signal generation unit 21 receives failure information from the node 30. The inter-node switch 20 may recognize the occurrence of a failure in the node 30 by receiving failure information from the node 30 or a device (not shown) that monitors each node. Alternatively, the inter-node switch 20 may periodically monitor the node 30 such as a health check to detect a failure in the node 30. The response signal generation unit 21 stops the transfer of the block transmitted from the transmission unit 12 to the node 30 after receiving the failure information. Further, the response signal generation unit 21 generates a response signal for the acquired block instead of the node 30. The response signal generated by the response signal generation unit 21 is the same as the response signal generated by the node 30 for the block output from the transmission unit 12. The response signal generation unit 21 outputs the generated response signal to the determination unit 13.

  The determination unit 13 compares the number of response signals transmitted from the inter-node switch 20 with the number of block decompositions notified from the instruction decomposition unit 11, and determines whether or not the transmission process has ended normally.

  As described above, even when a failure occurs in the node 30 by using the multi-node system according to FIG. 1, the node 10 uses the number of response signals notified from the inter-node switch 20 to 12 can determine whether or not the transmission processing of a plurality of blocks transmitted from 12 has been normally completed. Therefore, it is not necessary to start a timer when no response signal is output from the node 30, and the transmission process in the transmission unit 12 can be terminated early. By detecting the end of the transmission process in the transmission unit 12, the instruction decomposing unit 11 can start processing the stored instruction processing information.

  In addition, since the node 10 does not need to add a different function when a failure occurs in the node 30, an increase in circuit scale can be prevented.

  Next, a detailed configuration example of the multi-node system according to the first exemplary embodiment of the present invention will be described with reference to FIG. The multi-node system includes a local node 10_1, an inter-node switch 20, and a remote node 30_1. The local node 10_1 corresponds to the node 10 in FIG. The remote node 30_1 corresponds to the node 30 in FIG.

  First, the configuration of the local node 10_1 will be described. The local node 10_1 includes an instruction decomposition unit 11, a transmission unit 12, a determination unit 13, a core 18, and a memory 19. The instruction decomposing unit 11, the transmitting unit 12, and the determining unit 13 are the same as those described in FIG. Further, the determination unit 13 includes a block decomposition number holding unit 14, a comparison unit 15, a block reply number counter 16, and an end status generation unit 17.

  The core 18 is configured by a processor such as a CPU or MPU. The core 18 outputs instruction processing information (request information) to the instruction decomposing unit 11. The instruction decomposition unit 11 decomposes instruction processing information into a plurality of blocks. Each block decomposed by the instruction decomposition unit 11 loads data from the memory 19 and outputs the data to the transmission unit 12. The transmission unit 12 outputs a plurality of blocks to the remote node 30_1 via the inter-node switch 20.

  The block decomposition number holding unit 14 holds information on the number of decomposed blocks decomposed by the instruction decomposition unit 11. The comparison unit 15 compares the number of decomposed blocks held in the block decomposition number holding unit 14 with the number of block replies acquired from the block reply number counter 16. The block reply is a response signal to which the remote node 30_1 that acquired the block responds for each block. The number of block replies corresponds to the number of response signals described in FIG. The comparison unit 15 determines that the transmission processing of the plurality of blocks in the transmission unit 12 has been normally completed when the number of decomposed blocks and the number of block replies match. Alternatively, it is determined that the command processing output from the core 18 has been normally completed in the remote node 30_1. The comparison unit 15 outputs the determination result to the end status generation unit 17 when the number of decomposed blocks and the number of block replies match.

  When the completion status generation unit 17 receives a notification from the comparison unit 15 that the processing has been completed normally, it issues an end status and outputs it to the memory 19. Thereby, the instruction processing issued in the core 18 is completed.

  Next, a configuration example of the internode switch 20 will be described. The inter-node switch 20 includes a data transmission / reception unit 22 and a pseudo block reply generation unit 23. The pseudo block reply generation unit 23 corresponds to the response signal generation unit 21 in FIG.

  The data transmitter / receiver 22 receives a plurality of blocks from the transmitter 12 and transfers the plurality of blocks to the node 30. Further, the data transmitting / receiving unit 22 transfers the block reply transmitted for each block from the remote node 30_1 to the block reply number counter 16. Furthermore, when receiving failure information indicating that a failure has occurred in the remote node 30_1 from the remote node 30_1, the data transmission / reception unit 22 outputs the failure information to the pseudo block reply generation unit 23. The data transmitter / receiver 22 stops transferring the block acquired from the transmitter 12 to the remote node 30_1 after acquiring the failure information.

  When the pseudo block reply generation unit 23 acquires failure information of the remote node 30_1 from the data transmission / reception unit 22, the pseudo block reply generation unit 23 generates a pseudo block reply. The pseudo block reply is generated for each block received from the transmission unit 12 after receiving the failure information. The pseudo block reply generated by the pseudo block reply generation unit 23 is output to the block reply number counter 16.

  Next, a configuration example of the remote node 30_1 will be described. The remote node 30_1 includes a failure processing detection unit 31 and a memory 32. The memory 32 records the block received from the data transmitting / receiving unit 22. When a block is recorded in the memory 32, a block reply is output to the data transmitting / receiving unit 22 for each block. The block reply may be generated by a processor or the like (not shown) included in the remote node 30_1.

  The failure processing detection unit 31 outputs failure information to the data transmission / reception unit 22 when a failure occurs in the remote node 30_1. Alternatively, when a monitoring device that monitors each node is connected to the inter-node switch 20, the failure that has occurred in the remote node 30_1 may be detected by the monitoring device and output to the data transmission / reception unit 22. Thereby, even when a serious failure that cannot output the failure information occurs in the remote node 30_1, the failure of the node 30 can be detected.

  Subsequently, a processing sequence in the multi-node system according to the first exemplary embodiment of the present invention will be described with reference to FIG. In FIG. 3, a processing sequence when a failure occurs in the remote node 30_1 will be described.

  The solid arrows output from the local node 10_1 to the inter-node switch 20 and from the inter-node switch 20 to the remote node 30_1 indicate that the block is output (blocks 1 to 6). The dashed arrows output from the remote node 30_1 to the inter-node switch 20 and from the inter-node switch 20 to the local node 10_1 indicate that a block reply is output (replies 1 to 3). For the blocks 4 to 6, the broken-line arrows output from the inter-node switch 20 to the local node 10_1 indicate that pseudo block replies are output (pseudo block replies 1 to 3). A solid line arrow output from the remote node 30_1 to the inter-node switch 20 after the block reply 3 indicates that failure information is output.

  The inter-node switch 20 transfers the blocks 1 to 3 received from the local node 10_1 to the remote node 30_1 before acquiring the failure information. Further, block replies 1 to 3 for the blocks 1 to 3 are received from the remote node 30_1 and transferred to the local node 10_1.

  After acquiring the failure information, the internode switch 20 stops the transfer of the blocks 4 to 6 transmitted from the local node 10_1 to the remote node 30_1. Further, the inter-node switch 20 generates pseudo block replies 1 to 3 for the blocks 4 to 6 and transmits them to the local node 10_1.

  Next, a flow of processing for generating a pseudo block reply in the internode switch 20 according to Embodiment 1 of the present invention will be described using FIG.

  First, the data transmitter / receiver 22 acquires a block from the transmitter 12. Next, if the failure report is received before acquiring the block from the transmission unit 12 (S12), the transmission unit 12 stops the transfer of the acquired block to the remote node 30_1 (S13). Next, the pseudo block reply generation unit 23 generates a pseudo block reply for the block acquired after receiving the failure report (S14). Next, the data transmitting / receiving unit 22 outputs the pseudo block reply generated by the pseudo block reply generating unit 23 to the determining unit 13.

  As described above, by using the multi-node system according to the first embodiment of the present invention, when a failure occurs in the remote node 30_1, a pseudo block reply is output from the inter-node switch 20 to the local node 10_1. To do. As a result, the local node 10_1 can end the command processing and execute the next command processing, assuming that the block is normally acquired in the remote node 30_1. Therefore, the local node 10_1 does not need to start a timer, and can finish the instruction processing at an early stage. Further, the local node 10_1 can process the pseudo block reply in the same manner as the block reply generated by the remote node 30_1. Therefore, it is not necessary to add a new function to the local node 10_1, and an increase in circuit can be prevented.

(Embodiment 2)
Subsequently, a configuration example of the multi-node system according to the second exemplary embodiment of the present invention will be described with reference to FIG. The multi-node system according to this figure is different from FIG. 2 in that the data transmission / reception unit 22 notifies the instruction decomposition unit 11 of the failure information notified from the failure processing detection unit 31. Other configurations are the same as those in FIG.

  When the failure information is notified from the failure processing detection unit 31, the data transmission / reception unit 22 outputs the failure information to the instruction decomposition unit 11. If the instruction disassembly unit 11 acquires the failure information while disassembling the instruction processing information output from the core 18 into blocks, the instruction disassembly unit 11 stops disassembling into blocks.

  Subsequently, a processing sequence in the multi-node system according to the second exemplary embodiment of the present invention will be described with reference to FIG. In FIG. 6, a processing sequence when a failure occurs in the remote node 30_1 will be described. The operation in which the block replies 1 to 3 are responded to the blocks 1 to 3 is the same as in FIG.

  The inter-node switch 20 transfers the failure information transmitted from the remote node 30_1 to the local node 10_1. After obtaining the failure information, the instruction disassembling unit 11 of the local node 10_1 stops the block disassembly. For this reason, the instruction decomposition unit 11 transmits only the already decomposed block (block 5) to the inter-node switch 20 before receiving the failure information. Further, the inter-node switch 20 generates pseudo block replies 1 and 2 for the blocks 4 and 5 transmitted after acquiring the failure information, and outputs them to the local node 10_1.

  As described above, the number of blocks transmitted from the local node can be reduced by using the multi-node system according to the second exemplary embodiment of the present invention. Therefore, when a failure occurs in the remote node, the local node can finish the command processing early. Therefore, the local node can quickly process the stored instruction processing information.

  In addition, the local node can detect that the instruction processing output to the remote node has not ended normally by acquiring the failure information. Therefore, the local node can also resend the command processing that did not end normally after the failure of the remote node is recovered.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 Node 10_1 Local node 11 Instruction decomposition part 12 Transmission part 13 Determination part 14 Block decomposition number holding part 15 Comparison part 16 Block reply number counter 17 End status generation part 18 Core 19 Memory 20 Inter-node switch 21 Response signal generation part 22 Data transmission / reception Unit 23 pseudo block reply generation unit 30 node 30_1 remote node 31 fault processing detection unit 32 memory

Claims (7)

A first node that transmits command processing information; and an inter-node switch that transfers the command processing information transmitted by the first node to the second node.
An instruction disassembling unit for disassembling the instruction processing information into a plurality of blocks;
Whether or not the transmission processing of the plurality of blocks has been normally completed based on the number of blocks decomposed by the command decomposition unit and the number of response signals to the plurality of blocks transmitted from the second node And a determination unit for determining
The inter-node switch is
When a failure occurs in the second node, a response signal that is the same as the response signal generated in the second node is transmitted to the block after the failure occurs among the plurality of blocks. A multi-node system that generates and transmits to the first node instead. The inter-node switch is
The multi-node system according to claim 1, wherein when a failure occurs in the second node, transfer of the plurality of blocks received from the first node to the second node is stopped. The instruction decomposition unit
3. The multi-node system according to claim 1, wherein when a failure occurs in the second node, discontinuing the instruction processing information into a plurality of blocks is stopped. A data transmission / reception unit that receives the instruction processing information transmitted by the first node and transfers the instruction processing information to the second node;
When a failure occurs in the second node, the second node is compared with the block after the failure among the plurality of blocks generated and transmitted by decomposing instruction processing information in the first node. An inter-node switch comprising: a response signal generating unit that generates a response signal that is the same as the response signal generated at the node instead of the second node. The data transmitter / receiver
The inter-node switch according to claim 4, wherein when a failure occurs in the second node, transfer of the plurality of blocks received from the first node to the second node is stopped. Receiving the instruction processing information transmitted by the first node and transferring the instruction processing information to the second node;
Detecting the occurrence of a failure in the second node;
Receiving a block generated by decomposing instruction processing information at the first node after detecting the occurrence of the failure;
Generating, instead of the second node, a response signal that is the same as a response signal generated at the second node for a block received after detecting the occurrence of the failure ;
Transmitting the response signal to the first node.   The data relay method according to claim 6, wherein when the block is received after detecting the occurrence of the failure, transfer of the block to the second node is stopped.

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