JPH05257685A - Program access device - Google Patents

Abstract

PURPOSE:To reduce a load on a programmer, and also, to decrease size of a program memory. CONSTITUTION:In a program memory 1, program data is read out successively, based on an address. An address generating circuit 2 contains a program counter 3 for holding the next address data synchronously with a clock signal, and accesses the program memory 1. An adding circuit 4 inputs the program data of the program memory 1, outputs it as it is unless it is a branch instruction, outputs a branch instruction until the clock signal inputted, if it is the branch instruction and outputs a non-operation instruction synchronously with the clock signal, and also, stops an operation of the program counter 3 until the clock signal is inputted. A pipeline register 5 holds successively the program data of the adding circuit 4 synchronously with the clock signal and outputs it to an address generating circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal program, that is, a program access device capable of accessing a 1-word program consisting of an operation code section and an operand section with one address.

In the case of processing a horizontal program using a pipeline register, a program is created in a program access device in which the timing at which a program counter generates a new address by a branch instruction is synchronized with a clock signal. At this time, it is necessary to define a non-operation instruction immediately after the branch instruction, which leads to a complicated program and a reduction in the program memory size. Therefore, it is desired to reduce the complexity of the program and reduce the program memory size.

[0003]

2. Description of the Related Art A conventional program access device 40 is shown in FIG. The program access device 40 includes an address generation circuit 41 including a program counter 42, a program memory 43, and a pipeline register 44. The address generation circuit 41 receives the program data DE44 output from the pipeline register 44, calculates an address to be accessed next based on the program data DE44, and calculates the program counter 42.
Output to. The program counter 42 holds the calculated address data in synchronization with the clock signal CLK and outputs it to the program memory 43 as the address data AD42.

The program memory 43 stores a program having a large number of program data, each word of which is composed of an operation code part and an operand part. Address data AD4 from the program memory 43
Each time 2 is input, the program data DR43 corresponding to the address is sequentially read and output to the pipeline register 44.

The pipeline register 44 is provided for operating the program access device 40 at a high speed, and is synchronized with the clock signal CLK.
The program data DR43 input from 3 is sequentially held and output as the program data DE44 to the address generation circuit 41.

In the program access device 40 configured as described above, when the program counter 42 outputs the address data AD42 of the address N at time t0, the contents of the program memory 43 are delayed by a predetermined access time from time t0. Program data D of N
R43 is read. Then, at time t1, the program counter 42 is incremented in synchronization with the rising edge of the clock signal CLK, the address data AD42 becomes the address (N + 1), and the pipeline register 44 latches the program data DR43 having the content N and the program data DR43 is latched. The data DE44 is output to the address generation circuit 41.

When a predetermined access time elapses from the time t1, the contents (N
The program data DR43 of +1) is read, and the program data DR43 of content (N + 1) is latched in the pipeline register 44 at the time t2 in synchronization with the rising edge of the clock signal CLK and is stored in the address generation circuit 41 as the program data DE44. Is output. That is, the address data A of the program counter 42
The program data having the content corresponding to the address data AD42 is latched in the pipeline register 44 with a delay of one cycle of the clock signal CLK after the change of D42.

[0008]

However, in the program access device 40 configured as described above, for example, the content N of the program data DE44 is a branch instruction for adding "19" to the address and the content of the program data DE44 ( N + 1) sets the address to "10"
It is a branch instruction to be added. Actually time t2
At the time t3, the program counter 42 is made to latch (N + 20) at (N + 20).
21), but in this case, (N + 30) is latched in the program counter 42 based on the contents (N + 1) of the (N + 1) address at time t3.

Thus, if branch instructions are defined at consecutive addresses, program data at unintended addresses will be accessed. Therefore, when a program is created, a non-operation instruction must be defined immediately after the branch instruction. did not become. Therefore, two branch steps are required for one branch instruction, the program becomes complicated, the load on the programmer increases, and the size of the program memory increases.

The present invention has been made in order to solve the above-mentioned problems. It is possible to automatically generate a non-operation instruction immediately after a branch instruction to reduce the complexity of the program and the load on the programmer. The purpose is to reduce the size of the program memory.

[0011]

FIG. 1 illustrates the principle of the present invention. The program memory 1 sequentially reads 1-word program data including an operation code portion and an operand portion each time address data is input. The address generation circuit 2 includes a program counter 3 that holds the next address data based on the input program data in synchronization with a clock signal, and accesses the program memory 1 based on the address data held by the program counter 3.

The additional circuit 4 receives the program data read from the program memory 1, outputs it as it is when the program data is an instruction other than a branch instruction, and outputs the clock signal when the program data is a branch instruction. The program data is output until the input signal is input, the non-operation instruction is output in synchronization with the clock signal, and the operation of the program counter 3 is stopped until the clock signal is input.

The pipeline register 5 sequentially holds the program data output from the additional circuit 4 in synchronization with the clock signal and outputs the program data to the address generation circuit 2.

[0014]

Therefore, since it is not necessary to make the program step after the branch instruction a non-operation instruction when creating the program, the number of program steps can be reduced, the program memory size can be reduced, and the program complexity can be reduced. This alleviates the load on the programmer in programming.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. As shown in FIG. 2, the program access device 10 of this embodiment includes an address generation circuit 11,
The program memory 12, the additional circuit 13, the pipeline register 14, the clock generator 15 and the like are provided. The clock generator 15 supplies the clock signal CLK shown in FIG. 5 to the address generation circuit 11, the additional circuit 13 and the pipeline register 14.

As shown in FIG. 6, the program memory 12 stores program data 30 having a one-word structure including an operation code section 31 and an operand section 32. In the program data 30 of this embodiment, the operation code section 31 is composed of 4 bits B15 to B12, and the bit B15 is set as a branch instruction bit. In addition, the operand part 32 is bit B1
It is composed of 12 bits 1 to B0. The program memory 12 is accessed each time the address data AD17 is input from the address generation circuit 11, and the program data corresponding to the address is sequentially read. The read program data DR12 is output to the addition circuit 13.

The address generation circuit 11 stores the address data AD17 in the program memory 12 based on the program data DE14 input from the pipeline register 14.
Is to be output. That is, the address generation circuit 11 includes an adder 16 and a program counter 17, as shown in FIG. The adder 16 has the address data A of the program counter 17 at one input portion.
D17 is input and the bit B1 of the operand part 32 in the program data 30 is input to the other input part.
You have entered 1-B0. Then, the adder 16 adds the address data AD17 and the bits B11 to B0 and outputs the addition result to the program counter 17.

The program counter 17 has a branch instruction bit B15 of the operation code section 31, a clock signal CLK of the clock generator 15, a reset signal XRES from a control section (not shown), and a stop control signal bar STOP output from the additional circuit 13. You are typing. When the branch instruction bit B15 is not valid (= “0”), that is, when the rising edge of the clock signal CLK is input, the program counter 17 holds the address data held at that time. AD17 is incremented and held and output as the next address data. In the program counter 17, the branch instruction bit B15 is valid (=
"1"), that is, when the rising edge of the clock signal CLK is input in the case of a branch instruction,
At that time, the addition result output from the adder 16 is held and output as the next address data. Further, the program counter 17 is an L level stop control signal bar STO.
When P is input, the address update operation based on the clock signal CLK is stopped.

The additional circuit 13 connected to the program memory 12 comprises a mask circuit 18 and a stop control circuit 19, and receives the program data DR12 output from the program memory 12 and outputs the program data DE18. ing.

As shown in FIG. 4, the mask circuit 18 is an AN.
It is composed of a D circuit 20 and a data flip-flop (hereinafter, simply referred to as data FF) 21, and the bits B14 to B0 of the input program data DR12 are directly output to the pipeline register 14 as the bits B14 to B0 of the program data DE18. The AND circuit 20 outputs a logical product signal of the branch instruction bit B15 of the program data DR12 and the inverted output XQ of the data FF21 as the branch instruction bit B15 of the program data DE18.

The AND signal of the AND circuit 20 is input to the data terminal of the data FF 21, and the data FF 21 latches the AND signal of the AND circuit 20 in synchronization with the clock signal CLK output from the clock generator 15. An inverted signal of the logical product signal is output as the inverted output XQ. The data FF 21 is reset when the L level reset signal XRES is input, and the inverted output XQ
"1" is output as.

Therefore, when the branch instruction bit B15 of the program data DR12 is not valid (= "0"), "0" is output as it is as the branch instruction bit B15 of the program data DE18. When the branch instruction bit B15 of the program data DR12 is "0", "0" is latched in the data FF21 in synchronization with the rising edge of the clock signal CLK, and the inverted output XQ is "1".

When the branch instruction bit B15 of the program data DR12 becomes valid (= "1") while the inverted output XQ of the data FF21 is "1", the AND signal of the AND circuit 20 becomes "1", and the program “1” is output as the branch instruction bit B15 of the data DE18. After the branch instruction bit B15 of the program data DR12 becomes "1", the next clock signal CL
When K is input to the data FF 21, "1" is latched in the data FF 21 and the inverted output XQ becomes "0".
The AND signal of the AND circuit 20 becomes "0", and "0" is output as the branch instruction bit B15 of the program data DE18. That is, the program data DR12
The branch instruction bit B15 (= “1”) is masked to be a non-operation (NOP) instruction.

The stop control circuit 19 comprises an inverter,
The AND signal of the AND circuit 20 is inverted and the stop control signal bar STOP is output. For example, when the logical product signal of the AND circuit 20 is "0", the stop control signal bar STOP becomes H level, and when the logical product signal is "1", the stop control signal bar STOP becomes L level. That is, the inverter 19 outputs the L-level stop control signal STOP until the next rising edge of the clock signal CLK is input after the branch instruction bit B15 of the program data DR12 becomes valid.

The pipeline register 14 is an additional circuit 13
The program data DE18 output from the address generator circuit 11 is sequentially held in synchronization with the clock signal CLK.
Output to.

Next, the operation of the program access device 10 configured as described above will be described with reference to FIG. Now
When the program counter 17 outputs the address data AD17 at the address (N-1) and the program memory 12 outputs the program data DR12 having the content (N-1) which is an instruction other than the branch instruction, the branch instruction bit B15. Is invalid (= "0"), the content (N-1) is output from the additional circuit 13 as it is as the program data DE18.

At time t0, the program counter 17 is incremented in synchronization with the rising edge of the clock signal CLK and the address data AD17 becomes the address N. At this time, the data FF 21 of the additional circuit 13 AND's in synchronization with the rising edge of the clock signal CLK.
The logical product signal “0” of the circuit 20 is latched and the inverted output X
Q becomes "1".

Program data DR12 having a content N from the program memory 12 based on the address data AD17 at address N after a predetermined access time from time t0.
Is read. Program data DR1 with this content N
If 2 is a branch instruction that jumps to address M, the branch instruction bit B15 is valid (= “1”),
Since the inverted output XQ of the data FF 21 is “1”, A
The logical product signal of the ND circuit 20 becomes "1", and the additional circuit 1
From 3, the content N is directly output as the program data DE18. Further, since the AND signal of the AND circuit 20 becomes "1", the stop control signal bar STOP of the inverter 19 becomes L level.

Then, at time t1, the clock signal C
The program data DE18 having the content N is latched in the pipeline register 14 in synchronization with the rising edge of LK and output to the address generation circuit 11 as the program data DE14. In the address generation circuit 11, the jump destination address is calculated by the adder 16 based on the program data DE14 having the content N, and the calculation result is output to the program counter 17.

At the time t1, the data FF 21 synchronizes with A in synchronization with the rising edge of the clock signal CLK.
The logical product signal "1" of the ND circuit 20 is latched and the inverted output XQ becomes "0". Therefore, the AND signal of the AND circuit 20 becomes "0", and the program data D of the content N
The branch instruction bit B15 (= “1”) of R12 is masked to become a NOP instruction, and the N
The OP instruction is output as the program data DE18. Further, since the AND signal of the AND circuit 20 becomes “0”, the stop control signal bar STOP of the inverter 19 becomes H.
It becomes a level.

On the other hand, since the stop control signal bar STOP is at the L level at the time t1, the program counter 1 is input even if the rising edge of the clock signal CLK is input.
The address updating operation of No. 7 is not executed, and the address data AD17 of the program counter 17 is held at the address N. Based on the address data AD17 at the address N, the program memory 12 outputs the program data DR12 having the content N which is a branch instruction.

However, the inverted output XQ of the data FF 21
Is "0", the AND signal of the AND circuit 20 is "0", and the program data DR12 of the content N is
Are masked and the NOP instruction is continuously output from the additional circuit 13 as the program data DE18.

Then, at time t2, the branch counter bit B15 of the program data DE14 having the content N from the pipeline register 14 is stored in the program counter 17.
(= “1”) is input, clock signal CL
Program counter 1 in synchronization with the rising edge of K
The jump destination address output from the adder 16 is latched to 7 and the address data AD17 becomes the address M.

Further, at time t2, the clock signal CL
In synchronization with the rising edge of K, the pipeline register 14 latches the program data DE18, which is a NOP instruction, and outputs it as the program data DE14 to the address generation circuit 11. Since the input program data DE14 is the NOP instruction in the address generation circuit 11, nothing is executed.

After a lapse of a predetermined access time from time t2, the program data D having the content M is read from the program memory 12 based on the address data AD17 at the address M.
R12 is read. If the program data DR12 of this content M is an instruction other than a branch instruction, the branch instruction bit B15 is not effective (= "0"), so the AND signal of the AND circuit 20 becomes "0", and the additional circuit From 13 the content M is the same as the program data D
It is output as E18.

At the next time t3, the clock signal CLK
Pipeline register 1 in synchronization with the rising edge of
7 is incremented and the address data AD17 becomes the address (M + 1), and the pipeline register 14 latches the program data DE18 having the content M to generate the program data DE14 as the address generation circuit 1
It is output to 1.

Thereafter, in the same manner as described above, after the address data AD17 of the program counter 17 in the address generation circuit 11 has changed, the pipeline register 14 is delayed by one cycle of the clock signal CLK and the contents corresponding to the address data AD17 are stored. The program data is latched, and the address generating circuit 11 outputs the next address data based on the program data.

As described above, in this embodiment, when the program data DR12 read from the program memory 12 is a branch instruction, the address update operation of the program counter 17 is stopped by the inverter 19 of the additional circuit 13 and the mask circuit 18 is executed. Thus, the branch instruction is once output to the pipeline register 14, and then the branch instruction bit B15 of the branch instruction is masked and output to the pipeline register 14 as a non-operation instruction in synchronization with the clock signal CLK.

Therefore, it is not necessary to make the program step after the branch instruction a non-operation instruction when creating the program, and it is sufficient to make the program step one step for one branch instruction. The complexity can be reduced and the load on the programmer can be reduced.

Since the number of program steps can be reduced, the size of the program memory 12 can be reduced.

[0041]

As described in detail above, according to the present invention,
The non-operation instruction immediately after the branch instruction is automatically generated, the complexity of the program can be reduced, the load on the programmer can be reduced, and the size of the program memory can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a program access device according to an embodiment.

FIG. 3 is a block diagram showing an address generation circuit according to an embodiment.

FIG. 4 is a circuit diagram showing an additional circuit according to an embodiment.

FIG. 5 is a timing chart showing the operation of the embodiment.

FIG. 6 is a diagram showing a data format of a program.

FIG. 7 is a block diagram showing a conventional program access device.

FIG. 8 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 1 Program Memory 2 Address Generation Circuit 3 Program Counter 4 Additional Circuit 5 Pipeline Register

Claims (1)

[Claims] 1. A program memory (1) in which 1-word program data composed of an operation code section and an operand section is sequentially read every time address data is input, and a next address based on the input program data. An address generation circuit (2) including a program counter (3) for holding data in synchronization with a clock signal, and accessing the program memory (1) based on address data held in the program counter (3); When the program data read from the memory (1) is input, and the program data is an instruction other than a branch instruction, the program data is output as it is. When the program data is a branch instruction, the program data is output until a clock signal is input. Outputs program data and clock signal Outputs the non-op in synchronization, additional circuit for stopping the operation of said program counter (3) until the clock signal is inputted (4)
And a pipeline register (5) which sequentially holds the program data output from the additional circuit (4) in synchronization with a clock signal and outputs the program data to the address generation circuit (2). Access device.