JP2530873B2 - Instruction prefetch address update circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems Action Example Effect of the invention [Overview] The present invention relates to a circuit that updates an instruction prefetch address in a CPU that performs prefetch, and aims to provide a circuit that can simplify the circuit configuration while maintaining sufficient performance. An address bus connecting the address input side of the register and the address output side of the memory access second register in which the output address of the first register is set at the time of instruction prefetch, and the output address of the second register inserted in the bus and incremented Address incrementer and incrementer during the access of instruction prefetch Has an address set circuit for setting the force address in the first register, the first register is constituted by flip-flop of the level trigger, the address increment the ripple carry adder to incrementer is used, it is characterized.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for updating an instruction prefetch address in a CPU that prefetches instructions.

A general CPU is provided with a MAR (memory address register) for holding an address for memory access by an operand address.

A CPU (prefetch address register) that holds an instruction prefetch address is provided in a CPU that prefetches instructions. In such a type of CPU, instruction prefetching is performed for consecutive addresses in the memory, so that the output address of PAR is sequentially updated by this type of circuit for each instruction prefetch.

[Prior Art] In the CPU 40 of FIG. 4, the output of the register group 42 is given to the ALU 44, and the operand address output by the ALU 44 is transmitted via the multiplexer 46 to the SAR (storage access register) 4
Set to 8.

Then, the address output from the SAR 48 is given to the memory 52 via the address bus 50, whereby the operand access of the memory 52 is performed.

When the prefetch control circuit 54 confirms that this operand access is not being performed, the prefetch address output by the PAR 56 is set to the SA via the multiplexer 46.
The prefetch address output from the SAR 48 is set in the R48 and is given to the memory 52 via the address bus 50.

As a result, the instruction is prefetched when the CPU 40 is not performing the operand access, and the prefetch address output from the PAR 56 is updated every time the prefetch is performed.

Therefore, the PAR 56 is composed of a counter, and the prefetch address is updated for each prefetch by the up count.

[Problems to be Solved by the Invention] Here, along with the expansion of the address space, there is a demand for a reduction in the amount of hardware of the CPU. Therefore, simplification of this type of circuit is required.

However, since the counter is composed of edge-triggered flip-flops, high-speed operation is possible, but PAR requires a large number of gates, which makes it difficult to simplify the circuit.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object thereof is to provide an instruction prefetch address update circuit that can simplify the circuit configuration while maintaining sufficient performance.

[Means for Solving Problems] In order to achieve the above object, the device according to the present invention is a first device.
It is configured as shown.

In the figure, the address input side of the first register 10 (PAR56) in which the instruction prefetch address is set and the address output of the second register 12 (SAR48) for memory access in which the output address of the first register 10 is set during instruction prefetch An address bus 14 that connects to the side, an address incrementer 16 that is inserted into the bus 14 and that increments the output address of the second register 12, and an output address of the incrementer 16 during the access of the instruction prefetch to the first register 10. The first register 10 is composed of a level-triggered flip-flop, and the address incrementer 16 is composed of a ripple carry adder.

[Operation] In the present invention, the incrementer 16 increments the output address of the second register 12 and sets it in the register 10 repeatedly, whereby the prefetch address is sequentially updated.

Since the first register 10 is composed of a level-triggered flip-flop and the ripple carry adder is used for the address incrementer 16, it is possible to simplify the circuit structure without lowering the performance.

[Embodiment] A preferred embodiment of a circuit according to the present invention will be described below with reference to the drawings.

In FIG. 2, an address bus 14 extending from the output side of the SAR 48 to the input side of the PAR 56 is provided, and the PAR 56 is composed of a level-triggered flip prop (latch).

An incrementer 16 is provided in the address bus 14, and the incrementer 16 is composed of a normal ripple carry adder.

Therefore, the address output by SAR48 is incrementer 1
The address incremented by 6 and output by the incrementer 16 is input to the PAR 56 via the multiplexer 58.

The address output from the ALU 44 is input to the PAR 56 via the multiplexer 58, and the input address is set at the time of initial setting or branching.

Further, the prefetch control circuit 54 can output the prefetch request signal PFRQ when it is confirmed that the operand access is not performed and the instruction buffer is bad, and the signal PFRQ is given to the multiplexer 46.

As a result, the multiplexer 46 can select the address output from the PAR 56, and the selected address is input to the SAR 48.

The system clock CLK is given to the SAR 48 via the gate 60, and the gate 60 is opened by the PFRQ of the prefetch control circuit 54 given via the gate 62.

Therefore, when it is confirmed that the operand access is not performed and the instruction buffer is empty,
The prefetch address held by PAR56 is set in SAR48, which prefetches instructions during that time. The prefetch request signal PFRQ of the prefetch control circuit 54 is given to the prep flop 64, and the flip flop 64 has the system clock CLK.
Each pulse is set.

Further, the output signal pfrq of the flip prop 64 is given to the multiplexer 58, and the multiplexer 58 selects the address output by the incrementer 16 by the signal pfrq. Further, the output signal pfrq of the flip prop 64 opens the gate 66, and the system clock is given to the PAR 56 via the gate 66.

The system clock sets the address output from the multiplexer 58 in PAR56, resulting in SAR4
8 holding addresses are updated.

The present embodiment is configured as described above, and its operation will be described below in the third aspect.
It will be described with reference to the drawings.

When it is confirmed that the operand access is not performed and the instruction buffer has a space, the prefetch request signal PFRQ which becomes the H level for one cycle of the clock CLK as shown in FIG. It is output from 54. This signal PFRQ selects the prefetch address n of the PAR output by the multiplexer / multiplexer 46 as shown in FIG. 3 (D), and the address n is SAR48.
Is input to

As shown in FIGS. 3A and 3B, the second system clock CL is generated when the gate 60 is opened by the signal PFRQ.
When K occurs, the prefetch address n of PAR output is set in SAR48 as shown in FIG.

The set address n is output to the address bus 50 as shown in (I) of the figure, whereby instruction prefetching is performed.

And the prefetch address n of the SAR output is the signal pfrq
Is incremented by the incrementer 16 as shown in FIG. 3 (H). At that time, the output signal of the flip prop 64 is output.
Since the incrementer side is selected by the multiplexer 58 by pfrq, the output address n + of the incrementer 16
1 is input to PAR56 as shown in FIG.

When the next system clock CLK is generated, the signal p
its system clock C through gate 66 opened in frq
Since LK is input to PAR56, the address n + 1 on the incrementer side selected by the multiplexer 58 is taken into PAR56 as shown in FIG.

As described above, the prefetch address n is output at the first system clock CLK to prefetch the instruction, and the prefetch address n is incremented at the next system clock CLK.

Therefore, the update of the flip-prop address has two machine cycles, but since this speed is allowed for memory access, it does not affect the operation of the CPU 40.

Here, since the ripple carry adder is used as the incrementer 16 and the PAR56 is composed of a level-triggered flip prop (latch), the counter composed of the edge-triggered flip prop is set to the PAR56 as in the past. The number of gates can be reduced to 1/2 to 1/3 compared to when it is used.

Therefore, according to the present embodiment, it is possible to simplify the circuit configuration while maintaining sufficient performance, which makes it possible to deal with the expansion of the address space of the CPU 40.

As described above, according to the present invention, the address output of the memory access second register in which the instruction prefetch address of the first register is set is incremented by the incrementer and set in the first register. Therefore, it is not necessary to use a counter that requires the use of edge-triggered flip-props to update the flip-address, and instead, a ripple carry adder or level-triggered flip-prop can be used. The number of gates required for can be significantly reduced.

Since high speed is not required for memory access, even if a ripple carrier is used for the address incrementer and a latch or the like is used for the first register, it does not affect the operation of the CPU. While maintaining sufficient performance, it becomes possible to simplify the circuit configuration and cope with the expansion of the address space.

[Brief description of drawings]

 FIG. 1 is a diagram for explaining the principle of the invention, FIG. 2 is a diagram for explaining the configuration of the embodiment, FIG. 3 is a time chart of signals in each part of the example, and FIG. 4 is a diagram for explaining the conventional configuration. 14 …… Address bus, 16 …… Address incrementer, 40 …… CPU, 44 …… ALU, 46 …… Multiplexer, 48 …… SAR, 50 …… Address bus, 52 …… Memory, 54 …… Prefetch control circuit , 56 …… PAR, 58 …… Multiplexer, 60,62 …… Gate, 64 …… Flipprop, 66 …… Gate.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasutoshi Sakurai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Takumi Maruyama 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Takeno 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP-A-52-5231 (JP, A)

Claims (1)

(57) [Claims] 1. An address input side of a first register (10) to which an instruction prefetch address is set and an address of a memory access second register (12) to which an output address of the first register (10) is set at the time of instruction prefetch. An address bus (14) connecting to the output side, an address incrementer (16) which is inserted into the bus (14) and increments the output address of the second register (12), and an address incrementer during the access of the instruction prefetch. An address set circuit (18) for setting the output address of (16) in the first register (10), and the first register (10) is composed of a level-triggered flip-flop, and an address incrementer (16) Ripple carry adder is used for the instruction prefetch address update circuit.