JPH07262002A - Logic circuit - Google Patents

Abstract

PURPOSE:To provide a logic circuit which achieves the reduction of power consumption by stopping the operation of a storage circuit by applying no synchronizing circuit to its storage circuit when the stored information in the storage circuit is not changed. CONSTITUTION:This logic circuit is composed of a register 1 for storing information according to the synchronizing signal, buffer circuit for buffering the synchronizing signal, latch circuit 3 and AND gate 4 for executing mask control to the supply of a clock signal so that the supply of the clock signal to the register for storing the information not to change its contents can be stopped but the clock signal can be supplied to the register 1 for storing the information to change its contents based on an enable signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit such as a combinational circuit or sequential circuit for inputting and outputting information such as instructions and data in synchronization with a clock signal, and to a logic circuit for reducing power consumption. .

[0002]

2. Description of the Related Art In recent years, in the design of microprocessors,
Since synchronization is achieved in the power consumption of the entire chip, the power consumption related to the synchronization signal (clock signal) may reach 50% or more. Of these, the power consumption of memory circuits accounts for a large proportion.

As such a memory circuit, a flip-flop circuit (hereinafter referred to as a circuit structure as shown in FIG. 16 using a clocked inverter 160 and an inverter 161 whose circuit structure is shown in FIG. 14 and symbols are shown in FIG. F / F
Abbreviated) is known. This F / F operates in synchronization with the clock signal (CK) and its inverted signal (CKN),
The symbol is represented, for example, as shown in FIG. 17, and the truth value is as shown in FIG.

As another memory circuit, for example, FIG.
A latch circuit configured as shown in 9 is known,
The symbol of this latch circuit is represented as shown in FIG. 20, for example, and its truth value is as shown in FIG.

For example, 32 using such a memory circuit
In order to temporarily store data in a bit microprocessor, a register or 32 in which the F / F shown in FIG. 16 is cascade-connected for 32 bits as shown in FIG.
The latch circuit shown in FIG. 19 for bits is required.

Since the latch circuit opens the data intake port while the clock signal is at the high level, if the data changes during that time, the output also changes accordingly. Then, the data input port is closed at the fall of the clock signal, and the data at that moment is held during the low level period of the clock signal. Therefore, the input data changed while the clock signal is low level is not output until the clock signal becomes high level.

When such latch circuits are connected in series, a master-slave type D type F / F is constructed. This F
/ F is composed of a master circuit for taking in data and a slave circuit for holding data, and both the confirmation of the input data and the change of the output data are performed in synchronization with the edge of the clock signal.

In a register using such an F / F, for example, the register shown in FIG. 22, the clock signal is a data value F
The timing at which the captured value is captured in / F220 and the captured value is output is controlled. Such a clock signal is buffered by the inverter 221 to drive the F / F 220 for 32 bits. The inverter 221 must drive the 32-bit F / F 220 each time the clock signal changes, even when the data is not valid. Further, at the same time, the internal circuit of the F / F 220 also operates and power is consumed.

Therefore, as shown in FIG. 23, there is a register constructed so that the clock signal is not supplied to the F / F as needed.

In FIG. 23, when the data is valid, the register masks the clock signal by the latch circuit 230 that holds the enable (Enable) signal and the AND (logical sum) gate 231, and controls the driving of the F / F 232. I am trying. As a result, unnecessary data acquisition is prevented and power consumption is reduced. on the other hand. In such a method, when the data is valid and the clock signal is not masked, the data is always updated regardless of the value of the data.

[0011]

As described above,
In the conventional power saving type register shown in FIG. 23, if the clock signal is not masked and the input data is valid, the data stored in the register is always updated. Therefore, even when only a part of the 32-bit input data changes, the inverter 233 that buffers all 32-bit F / Fs and clock signals has been driven. That is, F that captures data that does not change
It was driven even at / F.

Therefore, in the conventional configuration, power is consumed even in the F / F in which the stored contents do not change and the operation is substantially unnecessary, which causes an increase in power consumption of the entire circuit.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a memory circuit for storing information whose contents do not change when the memory information does not change in the memory circuit. An object of the present invention is to provide a logic circuit that can reduce the power consumption by stopping the operation of the memory circuit without giving a synchronization signal.

[0014]

In order to achieve the above object, the invention according to claim 1 provides a memory circuit for inputting / outputting and storing information according to a synchronizing signal and a memory circuit for buffering the synchronizing signal. Of the information given to the buffer circuit and the memory circuit to be stored, a change signal indicating whether or not the content changes with respect to the information given immediately before is received, and the content is changed based on this change signal. The control circuit controls the supply of the synchronization signal so that the supply of the synchronization signal to the storage circuit that stores the unchanged information is stopped and the supply of the synchronization signal is supplied to the storage circuit that stores the information whose content changes. .

According to a second aspect of the present invention, a storage circuit including a plurality of storage areas for storing information in accordance with a synchronization signal, and a storage circuit provided corresponding to each storage area, buffers the synchronization signal and provides the storage area with the synchronization signal. A buffer circuit and a change signal indicating whether or not the contents given to the respective storage areas and stored are changed with respect to the information given immediately before are received, and the contents are changed based on the change signal. The control circuit controls the supply of the synchronization signal so that the supply of the synchronization signal is stopped to the storage area for storing the information whose value does not change and the synchronization signal is supplied to the storage area for storing the information whose content changes.

According to a third aspect of the present invention, in the logic circuit according to the first or second aspect, the memory circuits are cascade-connected to sequentially transfer information, and the control circuit is given a change. It is configured by holding a signal and applying the held change signal to a transfer destination storage circuit when information is transferred.

According to a fourth aspect of the present invention, in the logic circuit according to the third aspect, the address stored in the first-stage storage circuit of the plurality of storage circuits and a fixed value given from the outside are calculated to update the address. However, it is provided with an arithmetic unit that gives a carry signal as a change signal to the first-stage storage circuit, and a selection circuit that selects an address updated by the arithmetic unit or a branch address given from the outside and gives it to the first-stage storage circuit. It constitutes a program counter.

According to a fifth aspect of the present invention, in the logic circuit according to the fourth aspect, the arithmetic unit comprises an adder or a subtractor, and a correction circuit for correcting a carry signal output from the adder or the subtractor. A comparison circuit that compares the branch address selected by the selection circuit with an address output from the first-stage storage circuit, and if the comparison results of the comparison circuit indicate that the two match, the correction output from the correction circuit is performed. And a logic gate that does not apply a carry signal to the memory circuit in the first stage.

According to a sixth aspect of the present invention, in the logic circuit according to the first or second aspect, the information input to the first-stage storage circuit is compared with the information stored and output up to that point in the first-stage storage circuit. And a comparison circuit that gives the comparison result as a second change signal to the first-stage storage circuit, and a first change signal corresponding to each storage circuit, and the control according to the held first change signal. A holding control circuit for controlling the supply of a synchronization signal to the circuit, wherein the storage circuit is cascade-connected and information is sequentially transferred to the storage circuit, and the control circuit is configured in accordance with a synchronization signal given from the holding control circuit. The second change signal, which holds the second change signal, is applied to the circuit of the transfer destination when the information is transferred
The shift register is configured by controlling the supply of the synchronization signal to the storage circuit in accordance with the change signal of.

The invention according to claim 7 is the same as claim 1,
In the logic circuit described in 3, 4, 5 or 6, the memory circuit is composed of flip-flop circuits connected in parallel. According to an eighth aspect of the present invention, in the logic circuit according to the first, second or third aspect, the change signal is a carry signal output to a higher-order adder in a plurality of adders connected in parallel, or the storage circuit. It consists of the comparison result of the information before and after being given to.

The invention according to claim 9 is the invention as claimed in claim 1,
In the logic circuit of 3, 4, 5, 6, 7 or 8, the control circuit includes a first latch circuit that latches a change signal in synchronization with a synchronization signal and a first latch circuit that synchronizes with the synchronization signal. A second latch circuit that latches the change signal output from the circuit and outputs the latched change signal to the transfer destination of the stored information; and a change signal and a synchronization signal held in the first latch circuit, And a gate circuit that controls the supply of the synchronization signal to the storage circuit.

[0022]

According to the present invention, when the stored information does not change in the memory circuit, the operation of the memory circuit is stopped without applying a synchronizing signal to the memory circuit.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a logic circuit according to an embodiment of the invention described in claim 1 or 2.

In this embodiment, when the logic circuit is considered as a register for holding the output result of the program counter using an adder (32-bit + 3-bit adder) or an incrementer, the value of the higher-order bits is higher. In that case, paying attention to the characteristic of data that the probability of change decreases, the F / F of the upper bit and the lower bit forming the register are divided and controlled, and the F / F of the upper bit is used when necessary. Other than the above, the stored data of the F / F is not updated.

Therefore, the logic circuit of the embodiment shown in FIG.
Registers 1U and 1L each serving as a storage circuit that inputs and outputs information according to a synchronization signal and stores the information, or a storage circuit that includes a plurality of storage areas that stores information according to the synchronization signal,
A buffer circuit that buffers a synchronization signal and supplies it to a storage circuit, or clock buffers 2U and 2L that are provided corresponding to respective storage areas and serve as a buffer circuit that buffers a synchronization signal and supplies it to a storage area, and supplies it to the storage circuit. A storage circuit that receives a change signal indicating whether or not the information given immediately before is changed among the stored and stored information, and stores the information whose content does not change based on the change signal Information supplied to and stored in a control circuit that controls the supply of the synchronization signal so that the synchronization signal is supplied to the storage circuit that stores the information whose content is changed when the supply of the synchronization signal is stopped In the memory area that receives a change signal indicating whether or not the content changes with respect to the information given immediately before, and stores the information whose content does not change based on the change signal. The latch circuit 3, 5 and the AND gate 4 are provided as a control circuit for controlling the supply of the synchronization signal so that the supply of the synchronization signal is stopped and the synchronization signal is supplied to the storage area for storing the information whose contents change. Is configured.

Specifically, the 32-bit register shown in FIG. 22 is used for the upper 24 bits (input A0 to A23, output Z).
0 to Z23) register 1U and lower 8 bits (input A)
24 to A31, outputs Z24 to Z31) to form a 32-bit register 1, and the lower register 1L includes a buffer circuit 2L including an inverter.
A synchronizing signal (clock signal, CLOCK) is supplied via the AND gate 4 and the output of the latch circuit 3 holding an enable signal (Enable) for mask control of the clock signal and the AND gate 4 produce a logical product. The taken clock signal is supplied via the buffer circuit 2U.

The latch circuit 3 latches the enable signal in synchronization with the clock signal and supplies the latched enable signal to one input of the AND gate 4.

The AND gate 4 receives the enable signal and the clock signal latched by the latch circuit 3 and controls the supply of the clock signal to the upper register 1U.

The latch circuit 5 latches the output of the latch circuit 4 in synchronization with the clock signal, and uses the latched enable signal as the output signal CLX to cascade-connect the registers 1 shown in FIG. 1 to form a shift register. To the register in the latter stage.

In such a configuration, when all of the input data A0 to A23 given to the upper register 1U does not change, the enable signal which is a change signal indicating whether or not the data changes is set to low level, and The signal is latched by the latch circuit 4 and given to the AND gate 4. Thus, even if the clock signal is given to the AND gate 4, the clock signal is not output from the AND gate 4 and is masked. Therefore, the clock signal is not supplied to the upper register 1U, the F / F configuring the upper register 1U does not operate, and the stored data is not updated. Further, the buffer circuit 2U that buffers the clock signal in the upper register 1U does not operate.

As a result, there is no power consumption in the higher-level configuration, and the power consumption of the circuit as a whole can be greatly reduced compared to the conventional one. Further, since the power consumption is reduced, it is possible to suppress heat generation.

FIG. 2 is a diagram showing the configuration of a logic circuit according to another embodiment of the invention described in claim 1 or 2.

The feature of the embodiment shown in FIG. 2 is that
Register 1U on the upper side of register 1 shown in FIG.
Independently of the above, the clock signal is mask-controlled also in the lower register 1L. That is, when the enable signal EA for mask controlling the lower clock signal is at the low level, this signal is latched by the latch circuit 21 and given to the AND gate 22 to supply the clock signal (CKX) to the lower register 1L. Be stopped.

When the enable signal EB for mask controlling the upper clock signal is at the low level, the supply of the clock signal (CKZ) to the upper register 1U is stopped.

Also in such an embodiment, the same effect as the above-mentioned embodiment can be obtained.

In the above embodiment, the register 1 is divided into the upper 24 bits and the lower 8 bits. However, the register 1 is divided according to the characteristic of the change of the data given to the register 1, the characteristic of the architecture and the design policy. The number of divisions and the position of division are set appropriately.

The enable signal supplied to the register 1 shown in FIG. 1 or 2 is, for example, as shown in FIGS.
A carry signal (carry, CL) such as an adder or an incrementer as shown in FIG.

FIG. 3 shows an example of a (32 bits + 8 bits) adder. The carry signal CL output from the lower 8 bits is supplied as the enable signal EB. When no carry occurs, the enable signal EB becomes low level and the upper bit data is not updated.

FIG. 4 shows an example of a (32 bits + 3 bits) adder, which is a carry signal C at the position where the register is divided.
L is used.

Similarly, in the incrementer shown in FIG. 5, the carry signal CL of the 8th bit is used.

FIG. 6 is a diagram showing the configuration of a logic circuit according to an embodiment of the invention described in claim 3 or 4.

The logic circuit of the embodiment shown in FIG. 6 is a model of a register that holds the value of the program counter when pipeline processing is performed.

In the architecture for pipeline processing, the value of the program counter must be held at each stage of the pipeline, so the IFP register 61 for storing the instruction fetch address (hereinafter abbreviated as IFP).
In addition, a DPC register 6 for storing the value of a decode stage program counter (hereinafter abbreviated as DPC)
2 and execution stage program counter (hereafter EPC
EPC register 63 for storing the value of (abbreviated) is required.

Here, in order to simplify the explanation, the above 3
An embodiment using only one register will be described.

FIG. 7 is a timing chart showing the contents of the registers in each of the above stages.

In FIG. 7, the instruction length is fixed at 4 bytes and the branch operation is not shown for simplicity of description.

The value of the program counter (PC) is IFP61 → DPC62 → EPC6 each time the stage advances.
Move in the order of 3. IFP61 and DPC at this time
The contents of 62 and EPC 63 change only 4 bytes between the clocks before and after. Therefore, it can be seen that the upper bits of the PC in each stage have very little change unless a branch operation occurs.

A carry (CL) signal from an adder or the like is transmitted to the IFP 61 to control the upper bit F / F.
That is, if no carry occurs, the upper bit data is not updated. Data of IFP61 is DP
When the signal is transferred to C62, the IFP 61 holds the CL signal and the signal is transmitted to the DPC 62.
It is possible to control the F / F of the upper bits of the. Similarly, the F / F of the EPC 63 is controlled using the signal held by the DPC 62.

A concrete circuit configuration of the modeled logic circuit shown in FIG. 6 is shown in FIG.

In FIG. 8, the logic circuit includes a latch circuit and a logic gate, which serve as a control circuit which holds a given change signal and gives the held change signal to a transfer destination memory circuit when information is transferred, Registers 61 and 6 that are cascade-connected and serve as storage circuits to which information is sequentially transferred through the storage circuits
2, 63, an address stored in the first-stage storage circuit of the plurality of storage circuits and a fixed value given from the outside to update the address, and a carry signal as a change signal to the first-stage storage circuit And a selector 83, which serves as a selection circuit for selecting the address updated by the arithmetic unit or the branch address given from the outside and giving it to the memory circuit at the first stage, thereby forming a program counter. Become.

In this program counter, the IFP register 61, the DPC register 62, and the EPC register 63 are
It is composed of the circuit shown in FIG. The adder 81 is composed of adders as shown in FIGS. The CL signals of these adders are transferred to the IFP via the OR gate 82.
It is input as the enable signal EB of the register 61.

Further, in order to perform the branch operation, the adder 81
A selector 83 for selecting the output or the branch address is provided. When a branch operation is performed (when the selector signal is at the high level and the branch address is selected and output),
The OR gate 82 so that the upper bits are forcibly controlled.
Is provided. When each enable signal given to the IFP register 61, the DPC register 62, and the EPC register 63 becomes a low level by the pipeline control signal, the operation of each register and the latch circuit holding the CL signal can be stopped.

The PC is incremented by the IFP register 6
This is performed in the order of 1 → adder 81 → selector 83 → IFP register 61. PC transfer at each stage is IFP
Update address of register 61, IFP register 61 → D
The PC register 62, the DPC register 62 and the EPC register 63 are simultaneously performed.

F / F of upper bit of IFP register 61
The CL signal from the adder 81 is used as the signal for controlling the. The CL signal is held inside the IFP register 61, and when the PC is transferred from the IFP register 61 to the DPC register 62, the latched enable signal (CL
X signal) is input as the enable signal EB of the DPC register 62. Similarly, the CLX signal output from the DPC register 62 is input as the enable signal EB of the EPC register 63 and transmitted as the upper bit control signal of the F / F.

FIG. 9 is a diagram showing a timing chart of the register shown in FIG.

In FIG. 9, input data A and B are added, a carry signal (CL) is generated, and the carry signal (CL) is input as an enable signal EB of the IFP register 61, and a clock signal (CKZ signal) for controlling upper bits. Is generated. The CKZ signal does not become high level unless the selector signal or the carry signal is generated. As a result, the power for the upper bit F / F is not consumed.

FIG. 10 is a diagram showing the structure of a logic circuit according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 10 is that, compared with the embodiment shown in FIG. 8, a subtractor circuit 101 is provided and a comparator 102 is further provided to strictly control the F / F of the upper bit. I tried to let them do it.

In FIG. 10, the logic circuit calculates the address stored in the first-stage storage circuit of the plurality of storage circuits and a fixed value given from the outside to update the address, and the carry signal is used as a change signal in the first stage. Adder / subtractor 101, which is an arithmetic unit to be given to the memory circuit of FIG.
And a comparator 102, which serves as a comparison circuit for comparing the branch address selected by the selection circuit with the address output from the first-stage storage circuit, and the comparison result of the comparison circuit,
When the two match, the program counter is configured by including a logic gate group 104 that serves as a logic gate that suppresses the supply of the corrected carry signal output from the correction circuit to the first-stage storage circuit. .

In the above configuration, since the carry signal needs to be corrected in the subtraction operation, it can be realized by adding the correction circuit 103 in the same manner as the addition.

Further, by comparing the upper side of the output of the IFP register 61 and the output of the selector 83, if the branch address selected by the selector 83 and the output of the IFP register 61 match, the comparison result Is given to the IFP register 61 as an enable signal EB,
The upper bit F / F data in each register is not updated.

Thus, the more stages the PC has to hold, the more comparator 10
When 2 is provided and the comparison result is used as the enable signal, it becomes possible to perform more strict control and further reduce power consumption.

FIG. 11 is a diagram showing the structure of a logic circuit according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 11 is that a shift register is constructed by using a register which is an embodiment of the logic circuit of the present invention.

In FIG. 11, the logic circuit compares the information input to the register 111 serving as the first-stage storage circuit with the information stored and output in the first-stage storage circuit,
Comparator 11 serving as a comparison circuit for providing the comparison result as the enable signal EB serving as the second change signal to the memory circuit in the first stage.
2 and the enable signal EA which is the first change signal corresponding to each storage circuit, and the synchronizing signal (ECK) is supplied to the latch circuit which is the control circuit of the register in accordance with the held first change signal. A storage circuit is provided with a latch circuit 113 which serves as a holding control circuit, and the storage circuits are connected in cascade so that information is sequentially transferred to the storage circuits. The control circuit receives a second change signal in accordance with a synchronization signal given from the holding control circuit. A shift register configured to hold the second change signal, to supply the second change signal to the storage circuit of the transfer destination when the information is transferred, and to control the supply of the synchronization signal to the storage circuit according to the held second change signal. I will do it.

Specifically, the logic circuit shown in FIG. 11 is divided into four by using the register 111 having the configuration shown in FIG. 12 and the enable signal latch circuit 113 shown in FIG.
A bit shift register is configured, and a comparator 112 having the same function as the comparator 102 shown in FIG. 10 is provided, and the data input to the shift register of each 16-bit portion and the output of the first stage register are compared. Then, if the contents are the same, the clock signal is masked to stop the operation of the F / F to reduce the power consumption.

The present invention is not limited to the above embodiment, and the enable signal as the change signal is not limited to the carry signal of the arithmetic unit and the data before and after being stored in the register to be compared by the comparator. It may be the output of a circuit that detects a specific value that is input to or output from a register, and may be any signal as long as it is a signal that indicates whether or not the information before and after being stored in the storage circuit changes. Is also good.

In addition to the register, the logic circuit of the present invention can obtain the same effect even if it is a latch circuit or a RAM (random access memory) whose stored information is updated based on a synchronizing signal. Become.

[0070]

As described above, according to the present invention, when the stored information does not change in the storage circuit, the operation of the storage circuit is stopped without giving a synchronization signal to the storage circuit. Therefore, the power consumption of the logic circuit as a whole can be significantly reduced as compared with the conventional one, and heat generation due to the power consumption can be further suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a logic circuit according to an embodiment of the invention as defined in claim 1 or 2.

FIG. 2 is a diagram showing a configuration of a logic circuit according to another embodiment of the invention as set forth in claim 1 or 2.

FIG. 3 is a diagram showing a configuration of an adder that outputs an enable signal.

FIG. 4 is a diagram showing another configuration of an adder that outputs an enable signal.

FIG. 5 is a diagram showing a configuration of an incrementer that outputs an enable signal.

FIG. 6 is a diagram showing a configuration of a logic circuit according to an embodiment of the invention described in claim 3 or 4;

FIG. 7 is a timing chart of the circuit shown in FIG.

8 is a diagram showing the configuration of a specific example of the circuit shown in FIG.

9 is a timing chart of the circuit shown in FIG.

FIG. 10 is a diagram showing a configuration of a logic circuit according to an embodiment of the invention as set forth in claim 5;

FIG. 11 is a diagram showing a configuration of a logic circuit according to an embodiment of the invention as set forth in claim 6;

FIG. 12 is a diagram showing a partial configuration of the circuit shown in FIG. 11.

FIG. 13 is a diagram showing a partial configuration of the circuit shown in FIG. 11.

FIG. 14 is a diagram showing a circuit configuration of a clocked inverter.

FIG. 15 is a diagram showing a symbol of a clocked inverter.

FIG. 16 is a diagram showing a circuit configuration of a flip-flop circuit.

FIG. 17 is a diagram showing symbols of a flip-flop circuit.

FIG. 18 is a diagram showing a truth value of the flip-flop circuit shown in FIG. 16;

FIG. 19 is a diagram showing a circuit configuration of a latch circuit.

FIG. 20 is a diagram showing a symbol of a latch circuit.

21 is a diagram showing a truth value of the latch circuit shown in FIG.

FIG. 22 is a diagram showing one configuration of a conventional register.

FIG. 23 is a diagram showing another configuration of a conventional register.

[Explanation of symbols]

 1, 61, 62, 63 register 2 buffer circuit 3, 5, 21 latch circuit 4, 22, 82 logic gate 81, 101 adder 83 selector 102, 111 comparator 103 correction circuit

Claims (9)

[Claims] 1. A storage circuit that inputs and outputs information according to a synchronization signal and stores the same; a buffer circuit that buffers the synchronization signal and applies the storage circuit to the storage circuit; Upon receiving a change signal indicating whether the content changes with respect to the given information, the supply of the synchronization signal to the storage circuit that stores the information whose content does not change based on the change signal is stopped,
And a control circuit that controls the supply of the synchronization signal so that the synchronization signal is supplied to a storage circuit that stores information whose contents change. 2. A storage circuit comprising a plurality of storage areas for storing information in accordance with a synchronization signal, a buffer circuit provided corresponding to each storage area, for buffering the synchronization signal and giving the storage area to the storage area, respectively. Of the information given and stored in the storage area,
Upon receiving a change signal indicating whether the content changes with respect to the information given immediately before, based on this change signal, the supply of the synchronization signal is stopped to the storage area for storing the information whose content does not change. And a control circuit that controls the supply of the synchronization signal so that the synchronization signal is supplied to a storage area that stores information that changes. 3. The storage circuits are cascade-connected and information is sequentially transferred to the storage circuits, and the control circuit holds a change signal applied thereto and transfers the held change signal when the information is transferred. 3. The logic circuit according to claim 1 or 2, wherein the logic circuit is provided to a transfer destination memory circuit. 4. The address stored in the first-stage storage circuit of the plurality of storage circuits and a fixed value given from the outside are calculated to update the address, and a carry signal is given to the first-stage storage circuit as a change signal. 4. A program counter is provided, comprising a computing unit and a selection circuit for selecting an address updated by the computing unit or a branch address given from the outside and giving it to a first-stage storage circuit, thereby forming a program counter. The described logic circuit. 5. The arithmetic unit comprises an adder or a subtractor, a correction circuit for correcting a carry signal output from the adder or the subtractor, a branch address selected by the selection circuit, and a first-stage storage. A comparison circuit that compares the address output from the circuit and a logic gate that does not give the corrected carry signal output from the correction circuit to the first-stage storage circuit if the comparison results of the comparison circuit match. 5. The logic circuit according to claim 4, further comprising: 6. The information input to the storage circuit of the first stage and the information stored and output in the storage circuit of the first stage are compared, and a comparison result is given to the storage circuit of the first stage as a second change signal. A storage circuit that holds a first change signal corresponding to each storage circuit and controls the supply of a synchronization signal to the control circuit according to the held first change signal; The circuits are cascade-connected and information is sequentially transferred to the storage circuits, and the control circuit holds the second change signal according to the synchronization signal given from the hold control circuit, and holds the held second change signal. When the information is transferred, it is given to the transfer destination circuit,
3. The logic circuit according to claim 1, wherein the shift circuit is configured to control the supply of the synchronization signal to the storage circuit in accordance with the held second change signal. 7. The memory circuit comprises flip-flop circuits connected in parallel.
The logic circuit of 2, 3, 4, 5 or 6. 8. The change signal comprises a carry signal output to a higher-order adder in a plurality of parallel-added adders, or a comparison result of information before and after being given to the storage circuit. The logic circuit according to claim 1, 2, or 3. 9. The control circuit latches a change signal output from the first latch circuit in synchronization with a synchronization signal, and a first latch circuit that latches the change signal in synchronization with the synchronization signal. A second latch circuit that outputs the latched change signal to the storage information transfer destination, and a gate that receives the change signal and the synchronization signal held in the first latch circuit and controls the supply of the synchronization signal to the storage circuit And a circuit.
The logic circuit according to 4, 5, 6, 7 or 8.