CN112003603A - Message expansion circuit, method, chip, household appliance and storage medium - Google Patents
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Abstract
The application discloses a message expansion circuit, a method, a chip, a household appliance and a storage medium, wherein the message expansion circuit comprises a message storage circuit, a multi-way selection circuit and an arithmetic logic circuit, wherein the message storage circuit comprises a first number of storage units and is configured to store an input initial message to one of the first number of storage units; the multiplexing circuit is connected with the first number of storage units and is configured to select a second number of messages in the first number of messages stored in the first number of storage units; the arithmetic logic circuit is connected with the multi-path selection circuit and the message storage circuit and is configured to logically calculate the second number of messages to obtain output messages and input the output messages to the message storage circuit. By the mode, the dynamic power consumption of the circuit can be reduced.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a message expansion circuit, a message expansion method, a message expansion chip, a home appliance, and a storage medium.
Background
The Secure Hash Algorithm (SHA) is a National Security Agency (NSA) design, a series of cryptographic Hash functions issued by the National Institute of Standards and Technology (NIST), including variations of SHA1, SHA224, SHA256, SHA384, and SHA 512. The SHA algorithm is characterized in that it is not possible to recover a message from a message digest, and two different messages do not produce the same message digest.
Taking SHA256 as an example, SHA256 is a more common type of secure hash algorithm. For messages with a length of less than 2^64 bits, the SHA256 will generate a 256-bit message digest, which should typically be configured for file verification, cryptographic encryption, workload certification, etc. In general, a shift register is used to register a message, and during the shifting process, although a new message is input, all registers move in sequence, so that data of each register needs to be updated in each clock cycle, which results in excessive dynamic power consumption.
Disclosure of Invention
In order to solve the above problems, the present application provides a message expansion circuit, a message expansion method, a chip, a home appliance, and a storage medium, which can reduce dynamic power consumption of a circuit.
The technical scheme adopted by the application is as follows: there is provided a secure hash algorithm based message expansion circuit, the message expansion circuit comprising: a message storage circuit comprising a first number of storage cells configured to store an input message to one of the first number of storage cells; a multiplexing circuit, coupled to the first number of memory cells, configured to select a second number of messages of the first number of messages stored by the first number of memory cells; and the operation logic circuit is connected with the multi-path selection circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages and input and output the output messages to the message storage circuit.
The message storage circuit further comprises a first number of clock turn-off units, the enable ends of the clock turn-off units are configured to input corresponding enable signals, the input ends of the clock turn-off units are configured to input clock signals, and the output ends of the clock turn-off units are connected with the corresponding storage units.
Wherein the message storage circuit further comprises a counter; the enabling ends of the first number of clock turn-off units are connected with the counter, the counter is configured to enable one of the first number of clock turn-off units according to the counting value, the enabled clock turn-off unit drives the corresponding storage unit by using the clock signal, and one message input at the current time sequence is stored in the storage unit corresponding to the enabled clock turn-off unit.
Wherein the first number is 16, the counter is a 6-bit counter, the counter is configured to enable one of the first number of clock gating off units according to a lower 4-bit count value.
The multi-path selection circuit comprises a second number of selection units, each selection unit comprises a first number of input ends, the first number of input ends are correspondingly connected with the first number of storage units, and the selection units are configured to select and output messages stored in one of the first number of storage units.
Wherein, the multi-path selection circuit also comprises a counter; the second number of selection units are connected with the counter, and the selection units are configured to select the message input by the corresponding input end in the first number of input ends according to the count value of the counter.
The first number is 16, the second number is 4, the counter is a 6-bit counter, and the selection unit is configured to select the message input by one of the first number of input terminals according to the lower 4 bits of the count value.
The serial numbers of the first number of storage units are 0 to 15 in sequence, and the serial numbers of the first number of input ends of the selection unit are 0 to 15 in sequence from a low order to a high order; the multiplexing circuit includes: the input end behind the 0 th bit input end of the first selection unit is sequentially connected with the storage units behind the 0 th storage unit in a one-to-one correspondence manner, and the output end of the first selection unit outputs a first selection message; the 0 th bit input end of the second selection unit is connected with the 1 st storage unit in the N storage units, the input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 1 st storage unit in a one-to-one correspondence mode, and the output end of the second selection unit outputs a second selection message; a 0 th bit input end of the second selection unit is connected with a 9 th storage unit in the N storage units, input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 9 th storage unit in a one-to-one correspondence mode, and an output end of the third selection unit outputs a third selection message; and a 0 th bit input end of the second selection unit is connected with a 14 th storage unit in the N storage units, input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 14 th storage unit in a one-to-one correspondence manner, and an output end of the fourth selection unit outputs a fourth selection message.
Wherein, the arithmetic logic circuit includes: the first operation unit is connected with the output end of the second selection unit, is configured to operate the second selection message and output a first operation message; a first adder, connected to the first selection unit and the first operation unit, configured to add the first selection message and the first operation message; the second operation unit is connected with the output end of the fourth selection unit, and is configured to operate the fourth selection message and output a second operation message; a second adder, connected to the third selection unit and the second operation unit, configured to add the third selection message and the second operation message; and the third adder is connected with the first adder and the second adder and is configured to add the message output by the first adder and the message output by the second adder and output the added messages.
Wherein, the arithmetic logic circuit further comprises: the first temporary storage device is connected with the first adder and the third adder and is configured to temporarily store the message output by the first adder; and the second temporary memory is connected with the second adder and the third adder and is configured to temporarily store the message output by the second adder.
Another technical scheme adopted by the application is as follows: there is provided a chip comprising a message spreading circuit as described above.
Another technical scheme adopted by the application is as follows: there is provided a household appliance comprising an integrated circuit as described above.
Another technical scheme adopted by the application is as follows: a message expansion method based on a secure hash algorithm is provided, and the method comprises the following steps: acquiring an initial message; storing the initial message to one of a first number of storage units; selecting a second number of messages of the first number of messages stored by the first number of storage units; and logically operating the second number of messages to obtain output messages, and storing the output messages to one of the first number of storage units.
Wherein storing the initial message to one of the first number of storage units comprises: acquiring a count value of a counter; enabling one clock turn-off unit in the first number of clock turn-off units according to the counting value, and storing a message input at the current time sequence to a storage unit corresponding to the enabled clock turn-off unit.
Another technical scheme adopted by the application is as follows: a computer-readable storage medium is provided, in which program data are stored which, when being executed by a processor, are adapted to carry out the steps of the method as described above.
Another technical scheme adopted by the application is as follows: there is provided a domestic appliance comprising a processor and a memory, the memory having stored therein program data, the processor being configured to execute the program data to carry out the steps of the method as described above.
The application provides a message expansion circuit comprising: a message storage circuit comprising a first number of storage cells configured to store an input message to one of the first number of storage cells; a multiplexing circuit, coupled to the first number of memory cells, configured to select a second number of messages of the first number of messages stored by the first number of memory cells; and the operation logic circuit is connected with the multi-path selection circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages and input and output the output messages to the message storage circuit. Through the mode, the messages are stored and selected through the matching of the N storage units and the multi-path selection circuit, each message is output through the selector after being stored in one storage unit, the shift storage in a plurality of storage units is not needed, the problem that each message needs to be stored in the N storage units once is solved, the enabling times of one storage unit in one rotation period based on a safe hash algorithm are reduced, and the dynamic power consumption of the circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of an embodiment of a message expansion circuit provided in the present application;
FIG. 2 is a circuit schematic diagram of a message storage circuit in one embodiment of a message expansion circuit provided herein;
FIG. 3 is a circuit schematic diagram of a multiplexing circuit in one embodiment of a message expansion circuit provided herein;
FIG. 4 is a circuit diagram of an arithmetic logic circuit in one embodiment of the message expansion circuit provided herein;
FIG. 5 is a circuit schematic of an arithmetic logic circuit in another embodiment of the message expansion circuit provided herein;
FIG. 6 is a schematic diagram of a chip according to an embodiment of the present disclosure;
FIG. 7 is a schematic structural diagram of an embodiment of a household appliance provided herein;
FIG. 8 is a flowchart illustrating an embodiment of a message expansion method provided in the present application;
FIG. 9 is a schematic diagram of an embodiment of a computer-readable storage medium provided herein;
fig. 10 is a schematic structural diagram of another embodiment of a household appliance provided by the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a message expansion circuit provided in the present application, where the message expansion circuit 100 includes a message storage circuit 10, a multiplexing circuit 20, and an arithmetic logic circuit 30.
Wherein the message storage circuit 10 includes N storage units configured to store an input message to one of the N storage units; the multiplexing circuit 20 is connected to N storage units in the message storage circuit 10, and configured to select M messages from the stored messages; the arithmetic logic circuit 30 is connected with the multiplexing circuit 10 and the message storage circuit 20, and is configured to perform a logic operation on the M messages to obtain an output message, and input the output message to the message storage circuit 10; wherein N, M is a positive integer, and N is more than or equal to M.
Where N may be determined according to the particular type of secure hash algorithm, typically an integer power of 2, e.g., 4, 8, 16, 32 … …. Taking SHA256 algorithm as an example, since there are 64 extended messages of SHA256 algorithm, W is used1、W2……W63Is shown byThe calculation process is as follows:
for j ═ 0, 1, 2 … … 15:
Wj＝Mj(Mj512 bits in total for the initial input message);
for j-16, 17, … 63:
Wj＝C1(Wj-2)+(Wj-7)+C0(Wj-15)+(Wj-16) (1)
wherein:
C0(x)＝S7(x)^S18(x)^R3(x) (2)
C1(x)＝S17(x)^S19(x)^R10(x) (3)
wherein x is the input message, S is the cyclic right shift, R is the right shift, ^ is the XOR operation, and the superscript of S and R is the right shift number. Such as S7(x) Indicating that the 32-bit x-cycle is shifted to the right by 7 bits.
For 64 messages of the SHA256 algorithm, 64 storage units, 32 storage units, and 16 storage units may be used. It is understood that, if 64 memory cells are used, each memory cell only needs to store a message once in a round of operation, if 32 memory cells are used, each memory cell only needs to store a message twice in a round of operation, and in the embodiment, 16 memory cells are taken as an example, and each memory cell only needs to store a message four times in a round of operation.
Wherein the 16 storage units are configured to store incoming messages in sequence, e.g. for an initial message M0、M1……M15Can be respectively stored in A0、A1……A15A storage unit for storing the output message A when the output message is input0-A15The order of (a) is stored. Alternatively, the input message may be stored in a serial or parallel manner, such as, but not limited to, the initial message M0、M1……M15Can be input in series or in parallel, and the subsequent output message is input in one clock cycleAnd (4) respectively.
Through the mode, the messages are stored and selected through the matching of the N storage units and the multi-path selection circuit, each message is output through the selector after being stored in one storage unit, the shift storage in a plurality of storage units is not needed, the problem that each message needs to be stored in the N storage units once is solved, the enabling times of one storage unit in one rotation period based on a safe hash algorithm are reduced, and the dynamic power consumption of the circuit is reduced.
Wherein the multiplexing circuit 20 is configured to select messages output from the 16 memory cells, and the arithmetic logic circuit 30 is configured to perform a logic operation according to signals output from the multiplexing circuit 20 to obtain output messages. Alternatively, the multiplexer circuit 20 and the arithmetic logic circuit 30 may be arranged according to the formula (1), and the following embodiments will be described in detail.
The message storage circuit 10, the multiplexing circuit 20, and the arithmetic logic circuit 30 will be specifically described below in conjunction with the principles of the SHA256 algorithm described above. It is understood that, except for the SHA256 algorithm, other variations of SHA1, SHA224, SHA384, and SHA512 are similar and will not be described again.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a message storage circuit in an embodiment of a message spreading circuit provided in the present application, where the message storage circuit 10 includes 16 storage units a and 16 Clock Gating units ICG (integrated Clock switches), and the 16 storage units a correspond to the 16 Clock Gating units ICG one to one.
The enable terminal of each clock gating off unit ICG is controlled by an enable signal loaden, the input terminal inputs a clock signal gclk, and the output terminal is connected to the control terminal of the corresponding memory cell a. The input end of the memory cell A is configured to input and output messages, and the output end of the memory cell A is connected with the multiplexer circuit 20.
Understandably, A0、A1……A15The initial messages in the memory cells are M respectively0、M1……M15The output is W0、W1……W15。
In an embodiment, the generation of each loaden is controlled by a counter, the enabling terminals of the N clock gating units ICG are connected to the counter, and the counter is configured to enable one clock gating unit of the N clock gating units ICG according to the count value of the counter, and further store a message input at the current timing to the storage unit corresponding to the enabled clock gating unit. In this embodiment, taking 16 memory cells as an example, since there are 64 messages in a round of operation, the counter uses a 6-bit timer, and the lower 4 bits of the counter are configured to enable one clock gating cell ICG of the N clock gating cells. For example, the counter has a count value of "010011" and its lower 4 bits are "0011", and then, for A0-A15A1 th3The clock gating unit ICG of each memory cell is enabled.
As follows, where counter increments by one per clock:
……
In the manner described above, each loaden is enabled only 4 times in 64 rounds (64 cycles) of the SHA256 algorithm, with gclk flipped only 4 times. Thus, for each memory location a, the message is updated only 3 times in 64 cycles of the SHA256 algorithm, plus the initial message, the message is updated only 4 times in 64 cycles of the SHA256 algorithm,
in this embodiment, the storage unit a may be a register, but of course, other memories may be used, for example, a latch may be used instead to further reduce the memory occupation area.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a multiplexing circuit in an embodiment of the message spreading circuit provided in the present application, where the multiplexing circuit 20 includes M selecting units, each selecting unit includes N input terminals, and the N input terminals are respectively connected to the N storage units to select a message stored in one of the N storage units for output.
In this embodiment, still taking the SHA256 algorithm as an example, therefore, the multiplexer circuit 20 may include 4 selection units, each of which includes 16 input terminals respectively connected to 16 storage units.
The serial numbers of the first number of storage units are 0 to 15 in sequence, and the serial numbers of the first number of input ends of the selection unit are 0 to 15 in sequence from a low order to a high order.
Specifically, the 16 memory cells include W in order0Memory cell, W1Memory cell, W2Memory cell, W3Memory cell, W4Memory cell, W5Memory cell, W6Memory cell, W7Memory cell, W8Memory cell, W9Memory cell, W10Memory cell, W11Memory cell, W12Memory cell, W13Memory cell, W14Memory cell, W15And a memory unit. The 4 selection units MUX are 16-to-1 selection units, which are the first selection unit MUX16_0, the second selection unit MUX16_1, the third selection unit MUX16_ 2and the fourth selection unit MUX16_3, respectively.
In one embodiment, according to the above formula (1), the following connection method can be adopted:
the 0 th bit input end of the first selection unit is connected with the 0 th storage unit in the N storage units, the input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 0 th storage unit in a one-to-one correspondence mode, and the output end of the first selection unit outputs first selection information.
Specifically, 16 input terminals of the first selection unit MUX16_0 are sequentially connected W from low to high0Memory cell, W1Memory cell, W2Memory cell, W3Memory cell, W4Memory cell, W5Memory sheetYuan, W6Memory cell, W7Memory cell, W8Memory cell, W9Memory cell, W10Memory cell, W11Memory cell, W12Memory cell, W13Memory cell, W14Memory cell, W15And the output end of the first selection unit outputs the first selection message.
The 0 th bit input end of the second selection unit is connected with the 1 st storage unit in the N storage units, the input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 1 st storage unit in a one-to-one correspondence mode, and the output end of the second selection unit outputs second selection information.
Specifically, the 16 inputs of the second selection unit MUX16_1 are sequentially connected W from low to high1Memory cell, W2Memory cell, W3Memory cell, W4Memory cell, W5Memory cell, W6Memory cell, W7Memory cell, W8Memory cell, W9Memory cell, W10Memory cell, W11Memory cell, W12Memory cell, W13Memory cell, W14Memory cell, W15Memory cell, W0And the output end of the second selection unit outputs a second selection message.
The 0 th bit input end of the second selection unit is connected with the 9 th storage unit in the N storage units, the input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 9 th storage unit in a one-to-one correspondence mode, and the output end of the third selection unit outputs a third selection message.
Specifically, 16 input terminals of the third selection unit MUX16_2 are sequentially connected with W from low to high9Memory cell, W10Memory cell, W11Memory cell, W12Memory cell, W13Memory cell, W14Memory cell, W15Memory cell, W0Memory cell, W1Memory cell, W2Memory cell, W3Memory cell, W4Memory cell, W5A memory cell,W6Memory cell, W7Memory cell, W8And the output end of the third selection unit outputs a third selection message.
The 0 th bit input end of the second selection unit is connected with the 14 th storage unit in the N storage units, the input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 14 th storage unit in a one-to-one correspondence mode, and the output end of the fourth selection unit outputs a fourth selection message.
Specifically, 16 input terminals of the fourth selection unit MUX16_3 are sequentially connected with W from low to high14Memory cell, W15Memory cell, W0Memory cell, W1Memory cell, W2Memory cell, W3Memory cell, W4Memory cell, W5Memory cell, W6Memory cell, W7Memory cell, W8Memory cell, W9Memory cell, W10Memory cell, W11Memory cell, W12Memory cell, W13And the output end of the fourth selection unit outputs a fourth selection message.
The first selection unit MUX16_0, the second selection unit MUX16_1, the third selection unit MUX16_2, and the fourth selection unit MUX16_3 are also selected by the calculator. The selection units are connected with the counters, and each selection unit is configured to select the message input by one input end of the N input ends according to the count value of the counter. Here, taking 4 selection units and 16 input terminals of each selection unit as an example, the selection can be performed by using the lower 4 bits of 6 bits or directly using a counter [3:0] of 4 bits in the same manner as 16 storage units, and details are not described here. It will be appreciated that the counters of the message storage circuit 10 and the multiplexing circuit 20 need to be synchronised, and that if a 6bit counter is used, the same counter may be shared.
It can be understood that the connection between the 16 input terminals of the 4 selection units and the 16 storage units is formed by the above formula (1) and the 4 selection units driving the 4 selection units by using the same counter. In other embodiments, if each selection unit is driven by a separate counter, the connection manner between the 16 input terminals and the 16 storage units may be changed, for example, the storage unit order and the input terminal order are correspondingly connected, and the counting order of the 4 counters needs to be designed according to the above formula (1).
Further, referring to fig. 4, fig. 4 is a schematic circuit diagram of an arithmetic logic circuit in an embodiment of the message expansion circuit provided in the present application, where the arithmetic logic circuit 30 includes a first arithmetic unit C0, a second arithmetic unit C1, a first adder0, a second adder1, and a third adder 2.
The first operation unit C0 performs the operation according to the following formula:
C0(x)＝S7(x)^S18(x)^R3(x) (2)
the second operation unit C1 operates according to the following formula:
C1(x)＝S17(x)^S19(x)^R10(x) (3)
wherein x is the input message, S is the cyclic right shift, R is the right shift, ^ is the XOR operation, and the superscript of S and R is the right shift number.
Optionally, referring to fig. 5, fig. 5 is a circuit schematic diagram of an operation logic circuit in another embodiment of the message expansion circuit provided in the present application, where the operation logic circuit 30 includes a first operation unit C0, a second operation unit C1, a first adder0, a second adder1, and a third adder 2.
In this embodiment, the arithmetic logic circuit 30 further includes a first register B0 and a second register B1, and the first register B0 is connected between the first adder 0and the third adder 2and configured to temporarily store the message output by the first adder 0. The second temporary storage B1 is connected between the second adder 1and the third adder2, and is configured to temporarily store the message output by the second adder1, so as to improve the operation efficiency of the message.
Alternatively, the first and second registers B0 and B1 may be registers or latches, and controlled by a clock signal.
Optionally, in other embodiments, the arithmetic logic circuit 30 may further include a 1-out-of-2 selector MUX2_0, one input of which is connected to the output of the third adder2, and the other input of which is configured to input the initial message, i.e., the selector MUX2_0 selects to output the initial message in the first 16 clock cycles, and the selector MUX2_0 selects to output the message output by the third adder2 from the 17 th clock cycle.
Unlike the prior art, the message expansion circuit provided in this embodiment includes: a message storage circuit comprising a first number of storage cells configured to store an input message to one of the first number of storage cells; a multiplexing circuit, coupled to the first number of memory cells, configured to select a second number of messages of the first number of messages stored by the first number of memory cells; and the operation logic circuit is connected with the multi-path selection circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages and input and output the output messages to the message storage circuit. Through the mode, the messages are stored and selected through the matching of the N storage units and the multi-path selection circuit, each message is output through the selector after being stored in one storage unit, the shift storage in a plurality of storage units is not needed, the problem that each message needs to be stored in the N storage units once is solved, the enabling times of one storage unit in one rotation period based on a safe hash algorithm are reduced, and the dynamic power consumption of the circuit is reduced.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a chip provided in the present application, where the chip 60 includes a message spreading circuit 100, and a circuit structure and an operating principle of the message spreading circuit 100 are as described in the above embodiments, and are not described herein again.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of the household appliance provided in the present application, where the household appliance 70 includes a chip 60, and the chip 60 is an integrated circuit as in the above embodiments.
Wherein, the chip 60 is disposed in the household appliance to perform message expansion of the secure hash algorithm.
Referring to fig. 8, fig. 8 is a flowchart illustrating an embodiment of a message expansion method provided in the present application, where the method includes:
step 81: an initial message is obtained.
In the embodiment of fig. 1and fig. 2, taking the SHA256 algorithm as an example, the SHA256 algorithm has 16 initial messages.
Step 82: the initial message is stored to one of a first number of storage locations.
Wherein, 16 initial messages can be input into 16 storage units in a serial or parallel mode for storage.
Optionally, in an embodiment, step 82 may specifically be: acquiring a count value of a counter; enabling one clock turn-off unit in the first number of clock turn-off units according to the counting value, and storing a message input at the current time sequence to a storage unit corresponding to the enabled clock turn-off unit.
Step 83: a second number of messages of the first number of messages stored by the first number of storage units is selected.
The selection manner of the M (second number) messages may be determined according to a specific algorithm type, and taking SHA256 algorithm as an example, the selection may be performed according to formula (1), which may specifically refer to the above embodiments, and details are not described here.
Optionally, M (first number) of 1-out-of-N selection units are used to select one message from the N messages, respectively.
Step 84: and logically operating the second number of messages to obtain output messages, and storing the output messages to one of the first number of storage units.
Wherein N, M is a positive integer, and N is more than or equal to M.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a computer-readable storage medium 90 provided in the present application, in which program data 91 is stored, and when the program data 91 is executed by a processor, the following method is implemented:
acquiring an initial message; storing the initial message to one of a first number of storage units; selecting a second number of messages of the first number of messages stored by the first number of storage units; and logically operating the second number of messages to obtain output messages, and storing the output messages to one of the first number of storage units.
Referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the household appliance provided in the present application, the household appliance 70 includes a processor 71 and a memory 72, the memory 72 stores program data, and the processor 71 is configured to execute the program data to implement the following method:
acquiring an initial message; storing the initial message to one of a first number of storage units; selecting a second number of messages of the first number of messages stored by the first number of storage units; and logically operating the second number of messages to obtain output messages, and storing the output messages to one of the first number of storage units.
It will be appreciated that in the various embodiments described above, the integrated circuit and computer readable storage medium, on which the software is executable, may be configured as a computer, a mobile phone or other device with data processing capabilities, in addition to being configured as a household appliance, and may also be configured as a server or as a network node in a network, for example, a network node in a blockchain network.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (16)
1. A message expansion circuit, the message expansion circuit comprising:
a message storage circuit comprising a first number of storage cells configured to store an incoming message to one of the first number of storage cells;
a multiplexing circuit, coupled to the first number of memory cells, configured to select a second number of messages of the first number of messages stored by the first number of memory cells;
and the operation logic circuit is connected with the multi-way selection circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages and input the output messages to the message storage circuit.
2. The message expansion circuit of claim 1,
the message storage circuit further comprises a first number of clock gating units, wherein enable ends of the clock gating units are configured to input corresponding enable signals, input ends of the clock gating units are configured to input clock signals, and output ends of the clock gating units are connected with the corresponding storage units.
3. The message expansion circuit of claim 2,
the message storage circuit further comprises a counter;
the enabling terminals of the first number of clock gating units are connected with the counter, the counter is configured to enable one of the first number of clock gating units according to a count value, the enabled clock gating unit drives the corresponding storage unit by using the clock signal, and stores a message input at the current time sequence to the storage unit corresponding to the enabled clock gating unit.
4. The message expansion circuit of claim 3,
the first number is 16, the counter is a 6-bit counter, and the counter is configured to enable one of the first number of clock gating off units according to a lower 4-bit count value.
5. The message expansion circuit of claim 1,
the multi-path selection circuit comprises a second number of selection units, each selection unit comprises a first number of input ends, the first number of input ends are correspondingly connected with the first number of storage units, and the selection units are configured to select and output messages stored in one of the first number of storage units.
6. The message expansion circuit of claim 5,
the multiplexing circuit further comprises a counter;
the second number of selection units are connected with the counter, and the selection units are configured to select the message input by the corresponding input end of the first number of input ends according to the count value of the counter.
7. The message expansion circuit of claim 6,
the first number is 16, the second number is 4, the counter is a 6-bit counter, and the selection unit is configured to select the message input by one of the first number of input terminals according to a lower 4-bit count value.
8. The message expansion circuit of claim 7,
the serial numbers of the first number of storage units are 0 to 15 in sequence, and the serial numbers of the first number of input ends of the selection unit are 0 to 15 in sequence from a low order to a high order;
the multiplexing circuit includes:
a 0 th bit input end of the first selection unit is connected with a 0 th storage unit in the N storage units, input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 0 th storage unit in a one-to-one correspondence manner, and an output end of the first selection unit outputs a first selection message;
a 0 th bit input end of the second selection unit is connected with a1 st storage unit in the N storage units, input ends behind the 0 th bit input end are sequentially connected with storage units behind the 1 st storage unit in a one-to-one correspondence manner, and an output end of the second selection unit outputs a second selection message;
a 0 th bit input end of the second selection unit is connected with a 9 th storage unit of the N storage units, input ends behind the 0 th bit input end are sequentially connected with the storage units behind the 9 th storage unit in a one-to-one correspondence manner, and an output end of the third selection unit outputs a third selection message;
and a 0 th bit input end of the second selection unit is connected with a 14 th storage unit of the N storage units, input ends behind the 0 th bit input end are sequentially connected with storage units behind the 14 th storage unit in a one-to-one correspondence manner, and an output end of the fourth selection unit outputs a fourth selection message.
9. The message expansion circuit of claim 8,
the arithmetic logic circuit includes:
the first operation unit is connected with the output end of the second selection unit, and is configured to operate the second selection message and output a first operation message;
a first adder, connected to the first selection unit and the first operation unit, configured to add the first selection message and the first operation message;
the second operation unit is connected with the output end of the fourth selection unit, and is configured to operate the fourth selection message and output a second operation message;
a second adder, connected to the third selection unit and the second operation unit, configured to add the third selection message and the second operation message;
and a third adder, connected to the first adder and the second adder, configured to add the message output by the first adder and the message output by the second adder, and output the added message.
10. The message expansion circuit of claim 9,
the arithmetic logic circuit further comprises:
a first scratchpad connecting the first adder and the third adder, the first scratchpad being configured to temporarily store a message output by the first adder;
a second scratchpad connecting the second adder and the third adder, the second scratchpad configured to temporarily store messages output by the second adder.
11. A chip, characterized in that it comprises a message expansion circuit according to any of claims 1-10.
12. A household appliance, characterized in that it comprises an integrated circuit as claimed in claim 11.
13. A method of message expansion, the method comprising:
acquiring an initial message;
storing the initial message to one of a first number of storage units;
selecting a second number of messages of the first number of messages stored by the first number of storage units;
and logically operating the second number of messages to obtain output messages, and storing the output messages to one of the first number of storage units.
14. The method of claim 13,
the storing the initial message to one of a first number of storage units, comprising:
acquiring a count value of a counter;
enabling one clock turn-off unit in the first number of clock turn-off units according to the counting value, and storing a message input at the current time sequence to the storage unit corresponding to the enabled clock turn-off unit.
15. A computer-readable storage medium, in which program data are stored which, when being executed by a processor, are adapted to carry out the steps of the method according to claim 13 or 14.
16. A domestic appliance comprising a processor and a memory, said memory having stored therein program data, said processor being configured to execute said program data to carry out the steps of the method according to claim 13 or 14.
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