CN112003603B - Message expansion circuit, method, chip, household appliance and storage medium - Google Patents
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Abstract
The application discloses a message expansion circuit, a method, a chip, a household appliance and a storage medium, wherein the message expansion circuit comprises a message storage circuit, a multiplexing circuit and an operation logic circuit, wherein the message storage circuit comprises a first number of storage units and is configured to store an input initial message into one of the first number of storage units; the multiplexing circuit is connected with the first number of storage units and is configured to select a second number of messages in the first number of messages stored in the first number of storage units; the operation logic circuit is connected with the multiplexing circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages, and input and output the messages to the message storage circuit. By the mode, the dynamic power consumption of the circuit can be reduced.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a message expansion circuit, a method, a chip, a home appliance, and a storage medium.
Background
The secure hash algorithm (Secure Hash Algorithm, SHA) is a series of cryptographic hash functions issued by the National Security Agency (NSA) design, the National Institute of Standards and Technology (NIST), including variants of SHA1, SHA224, SHA256, SHA384, SHA512, and the like. The SHA algorithm is characterized by the inability to recover a message from a message digest, two different messages not producing the same message digest.
Taking SHA256 as an example, SHA256 is one of the more common types of secure hash algorithms. SHA256 for messages less than 2-64 bits in length, SHA256 generates a 256-bit message digest that is typically configured for file verification, cryptographic encryption, workload certification, etc. In general, a shift register is used to register a message, and during the shift process, although a new message is input, all registers are moved in sequence, so that data of each register needs to be updated in each clock period, which results in excessive dynamic power consumption.
Disclosure of Invention
In order to solve the problems, the application provides a message expansion circuit, a message expansion method, a message expansion chip, a household appliance and a storage medium, which can reduce the dynamic power consumption of the circuit.
The application adopts a technical scheme that: there is provided a message expansion circuit based on a secure hash algorithm, the message expansion circuit comprising: a message storage circuit including a first number of storage units configured to store an input message to one of the first number of storage units; a multiplexing circuit connected to the first number of memory cells and configured to select a second number of messages among the first number of messages stored in the first number of memory cells; and the operation logic circuit is connected with the multiplexing circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages, and input and output the messages to the message storage circuit.
The message storage circuit further comprises a first number of clock shut-off units, the enabling ends of the clock shut-off units are configured to input corresponding enabling signals, the input ends of the clock shut-off units are configured to input clock signals, and the output ends of the clock shut-off units are connected with corresponding storage units.
Wherein the message storage circuit further comprises a counter; the enabling end of the first number of clock shut-off units is connected with a counter, the counter is configured to enable one of the first number of clock shut-off units according to the count value, the enabled clock shut-off unit drives the corresponding storage unit by using a clock signal, and one message input in the current time sequence is stored in the storage unit corresponding to the enabled clock shut-off unit.
Wherein the first number is 16 and the counter is a 6bit counter configured to enable one of the first number of clock-off units based on a lower 4 bits of the count value.
The multi-path selection circuit comprises a second number of selection units, the selection units comprise a first number of input ends, the first number of input ends are correspondingly connected with the first number of storage units, and the selection units are configured to select one of the first number of storage units to store information to output.
Wherein the multiplexing circuit further comprises a counter; the second number of selecting units is connected with the counter, and the selecting units are configured to select messages input by corresponding one of the first number of input terminals according to the count value of the counter.
Wherein the first number is 16 and the second number is 4, the counter is a 6bit counter, and the selection unit is configured to select the message input by one of the first number of inputs based on the lower 4 bits of the count value.
The serial numbers of the first number of storage units are 0 to 15 in sequence, and the serial numbers of the first number of input ends of the selection units from low order to high order are 0 to 15 in sequence; the multiplexing circuit includes: the first selecting unit, the 0 th bit input end of the first selecting unit is connected with the 0 th memory unit in the N memory units, the input end after the 0 th bit input end is sequentially connected with the memory units after the 0 th memory unit in a one-to-one correspondence manner, and the output end of the first selecting unit outputs a first selecting message; the 0 th bit input end of the second selection unit is connected with the 1 st storage unit in the N storage units, the input end after the 0 th bit input end is sequentially and correspondingly connected with the storage units after the 1 st storage unit one by one, and the output end of the second selection unit outputs a second selection message; the 0 th bit input end of the second selection unit is connected with the 9 th storage unit in the N storage units, the input end after the 0 th bit input end is sequentially and correspondingly connected with the storage units after the 9 th storage unit one by one, and the output end of the third selection unit outputs a third selection message; and the 0 th bit input end of the second selection unit is connected with the 14 th storage unit in the N storage units, the input end after the 0 th bit input end is sequentially and correspondingly connected with the storage units after the 14 th storage unit one by one, and the output end of the fourth selection unit outputs a fourth selection message.
Wherein the arithmetic logic circuit includes: the first operation unit is connected with the output end of the second selection unit and is configured to operate the second selection message and output a first operation message; a first adder connecting the first selection unit and the first operation unit and configured to add the first selection message and the first operation message; the second operation unit is connected with the output end of the fourth selection unit and is configured to operate the fourth selection message and output a second operation message; a second adder connecting the third selection unit and the second operation unit and configured to add the third selection message and the second operation message; and the third adder is connected with the first adder and the second adder and is configured to add the message output by the first adder and the message output by the second adder, and output the obtained output message.
Wherein the arithmetic logic circuit further comprises: a first register connected to the first adder and the third adder, the first register configured to register a message output from the first adder; and the second register is connected with the second adder and the third adder and is configured to temporarily store the message output by the second adder.
The application adopts another technical scheme that: there is provided a chip comprising a message expansion circuit as described above.
The application adopts another technical scheme that: there is provided a household appliance comprising a chip as described above.
The application adopts another technical scheme that: there is provided a message extension method based on a secure hash algorithm, the method comprising: acquiring an initial message; storing the initial message to one of the first number of storage units; selecting a second number of messages from the first number of messages stored in the first number of storage units; and logically calculating the second number of messages to obtain an output message, and storing the output message in one of the first number of storage units.
Wherein storing the initial message to one of the first number of memory locations comprises: acquiring a count value of a counter; one of the first number of clock-off units is enabled according to the count value, and one message of the current time sequence input is stored in a storage unit corresponding to the enabled clock-off unit.
The application adopts another technical scheme that: there is provided a computer readable storage medium having stored therein program data which, when executed by a processor, is adapted to carry out the steps of a method as described above.
The application adopts another technical scheme that: there is provided a household appliance comprising a processor and a memory, the memory having stored therein program data, the processor being configured to execute the program data to implement the steps of the method as described above.
The message expansion circuit provided by the application comprises: a message storage circuit including a first number of storage units configured to store an input message to one of the first number of storage units; a multiplexing circuit connected to the first number of memory cells and configured to select a second number of messages among the first number of messages stored in the first number of memory cells; and the operation logic circuit is connected with the multiplexing circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages, and input and output the messages to the message storage circuit. Through the mode, the N storage units and the multi-path selection circuit are matched to store and select the messages, each message is output through the selector after being stored in one storage unit, and the messages are not required to be shifted and stored in a plurality of storage units, so that the problem that each message is stored once in the N storage units is avoided, the enabling times of one storage unit in one rotation period based on a secure hash algorithm is reduced, and the dynamic power consumption of the circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of an embodiment of a message expansion circuit according to the present application;
FIG. 2 is a schematic diagram of a message storage circuit in an embodiment of a message expansion circuit according to the present application;
FIG. 3 is a schematic diagram of a multiplexing circuit according to an embodiment of the message expansion circuit of the present application;
FIG. 4 is a schematic diagram of an arithmetic logic circuit in an embodiment of a message expansion circuit according to the present application;
FIG. 5 is a schematic diagram of an arithmetic logic circuit in another embodiment of a message expansion circuit according to the present application;
FIG. 6 is a schematic diagram of an embodiment of a chip according to the present application;
fig. 7 is a schematic view of a structure of an embodiment of a home appliance provided by the present application;
FIG. 8 is a flow chart of an embodiment of a message expansion method provided by the present application;
FIG. 9 is a schematic diagram illustrating the structure of an embodiment of a computer-readable storage medium provided by the present application;
fig. 10 is a schematic structural view of another embodiment of the home appliance provided by the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram of a message expansion circuit according to an embodiment of the present application, and the message expansion circuit 100 includes a message storage circuit 10, a multiplexing circuit 20 and an arithmetic logic circuit 30.
Wherein the message storage circuit 10 includes N storage units configured to store an input message to one of the N storage units; the multiplexing circuit 20 is connected to N storage units in the message storage circuit 10 and configured to select M messages from the stored messages; the arithmetic logic circuit 30 is connected to the multiplexing circuit 10 and the message storage circuit 20, and is configured to perform logic operation on the M messages to obtain an output message, and input the output message to the message storage circuit 10; wherein N, M is a positive integer, and N is not less than M.
Where N may be determined according to the specific type of secure hash algorithm, typically an integer power of 2, e.g. 4, 8, 16, 32 … …. Taking the SHA256 algorithm as an example, since there are 64 extended messages of the SHA256 algorithm, denoted by W 1、W2……W63, the calculation process is as follows:
for j=0, 1,2 … …:
W j＝Mj(Mj is the initial input message, 512 bits total);
for j=16, 17, … 63:
Wj＝C1(Wj-2)+(Wj-7)+C0(Wj-15)+(Wj-16) (1)
Wherein:
C0(x)＝S7(x)^S18(x)^R3(x) (2)
C1(x)＝S17(x)^S19(x)^R10(x) (3)
Where x is the input message, S is the cyclic right shift, R is the right shift, the XOR operation, and the superscript of S and R is the right shift number. For example, S 7 (x) represents right shifting a 32-bit x-cycle by 7 bits.
For 64 messages of the SHA256 algorithm, 64 memory locations, 32 memory locations and 16 memory locations may be employed. It will be appreciated that, if 64 storage units are used, each storage unit needs to store only one message in one operation, for example, 32 storage units are used, each storage unit needs to store only two messages in one operation, and in this embodiment, 16 storage units are used as an example, and each storage unit needs to store only four messages in one operation.
The 16 storage units are configured to sequentially store the input messages, for example, the initial message M 0、M1……M15 may be stored in the a 0、A1……A15 storage unit, and when an output message is input, the input messages may be stored again in the order of a 0-A15. Alternatively, the input message may be in a serial or parallel manner during the storage process, which is not limited herein, for example, the initial message M 0、M1……M15 may be input in serial or in parallel, and the subsequent output message is input one clock cycle.
Through the mode, the N storage units and the multi-path selection circuit are matched to store and select the messages, each message is output through the selector after being stored in one storage unit, and the messages are not required to be shifted and stored in a plurality of storage units, so that the problem that each message is stored once in the N storage units is avoided, the enabling times of one storage unit in one rotation period based on a secure hash algorithm is reduced, and the dynamic power consumption of the circuit is reduced.
Wherein the multiplexing circuit 20 is configured to select the messages output by the 16 memory cells, and the arithmetic logic circuit 30 is configured to perform a logic operation according to the signals output by the multiplexing circuit 20 to obtain the output messages. Alternatively, the multiplexing circuit 20 and the arithmetic logic circuit 30 may be configured according to the formula (1), and the following embodiments will be described in detail.
Next, the message storage circuit 10, the multiplexing circuit 20, and the arithmetic logic circuit 30 will be specifically described in conjunction with the principle of the SHA256 algorithm described above. It will be appreciated that other SHA1, SHA224, SHA384, SHA512, etc. variants are similar except for SHA256 algorithm and will not be described again.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a message storage circuit in an embodiment of a message expansion circuit provided by the present application, where the message storage circuit 10 includes 16 storage units a and 16 clock-off units ICG (INTERGRATED CLOCK GATING, integrated clock switch), and the 16 storage units a and the 16 clock-off units ICG are in one-to-one correspondence.
The enable end of each clock shutdown unit ICG is controlled by an enable signal loaden, the input end inputs a clock signal gclk, and the output end is connected with the control end of the corresponding memory unit a. The input terminal arithmetic logic circuit 30 of the memory cell a is configured to input and output a message, and the output terminal of the memory cell a is connected to the multiplexing circuit 20.
It will be appreciated that the initial messages in the a 0、A1……A15 memory units are M 0、M1……M15 respectively, and the output is W 0、W1……W15.
In an embodiment, the generation of each loaden is controlled by a counter, the enable ends of the N clock-off units ICG are connected to the counter, and the enable ends are configured to enable one of the N clock-off units ICG according to the count value of the counter, so as to store a message of the current time sequence input into a storage unit corresponding to the enabled clock-off unit. In this embodiment, taking 16 memory cells as an example, since there are 64 messages in a round of operation, the counter uses a 6-bit timer, and the lower 4 bits of the counter are configured to enable one of the N clock-off cells ICG. For example, the counter has a count value of "010011" and its lower 4 bits are "0011", and thus the clock-off unit ICG of a 0-A15 a 3 th memory cell is enabled.
As follows, wherein counter self-increments one per clock:
loaden0 =initializer (counter [3:0] = 1andcounter < = 48)
Loaden =initializer (counter [3:0] = 2andcounter < = 48)
……
Loaden14 =initializer (counter [3:0] = 15andcounter < = 48)
Loaden15 =initializer (counter [3:0] = 0andcounter < = 48)
In the manner described above, each loaden is enabled only 4 times in the 64 rounds of operations (64 cycles) of the SHA256 algorithm, with gclk flipped only 4 times. Thus, for each memory location A, the message is updated only 3 times in 64 cycles of the SHA256 algorithm, plus the initial message, and only 4 times in 64 cycles of the SHA256 algorithm,
In this embodiment, the memory unit a may be a register, and of course, other memories may be used, for example, a latch may be used instead to further reduce the memory footprint.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a multiplexing circuit in an embodiment of a message expansion circuit provided by the present application, where the multiplexing circuit 20 includes M selection units, each of the selection units includes N input terminals, and the N input terminals are respectively connected to N storage units, so as to select a message stored in one of the N storage units for outputting.
In this embodiment, the SHA256 algorithm is still taken as an example, and thus the multiplexing circuit 20 may include 4 selection units, each of which includes 16 input terminals connected to 16 storage units, respectively.
The serial numbers of the first number of the storage units are 0 to 15 in sequence, and the serial numbers of the first number of the selection units from the lower position to the higher position are 0 to 15 in sequence.
Specifically, the 16 memory cells include, in order, a W 0 memory cell, a W 1 memory cell, a W 2 memory cell, a W 3 memory cell, a W 4 memory cell, a W 5 memory cell, a W 6 memory cell, a W 7 memory cell, a W 8 memory cell, a W 9 memory cell, a W 10 memory cell, a W 11 memory cell, a W 12 memory cell, a W 13 memory cell, a W 14 memory cell, and a W 15 memory cell. The 4 selection units MUX are 16 selection units of 1, namely a first selection unit MUX16_0, a second selection unit MUX16_1, a third selection unit MUX16_2 and a fourth selection unit MUX16_3.
In one embodiment, according to the above formula (1), the following connection method may be adopted:
The 0 th bit input end of the first selection unit is connected with the 0 th memory unit in the N memory units, the input end after the 0 th bit input end is sequentially connected with the memory units after the 0 th memory unit in a one-to-one correspondence manner, and the output end of the first selection unit outputs a first selection message.
Specifically, the 16 input terminals of the first selection unit MUX16_0 are sequentially connected from the low order to the high order to the W 0 storage unit, the W 1 storage unit, the W 2 storage unit, the W 3 storage unit, the W 4 storage unit, the W 5 storage unit, the W 6 storage unit, the W 7 storage unit, the W 8 storage unit, the W 9 storage unit, the W 10 storage unit, the W 11 storage unit, the W 12 storage unit, the W 13 storage unit, the W 14 storage unit, the W 15 storage unit, and the output terminal of the first selection unit outputs the first selection message.
The 0 th bit input end of the second selection unit is connected with the 1 st memory unit in the N memory units, the input end behind the 0 th bit input end is sequentially and correspondingly connected with the memory units behind the 1 st memory unit one by one, and the output end of the second selection unit outputs a second selection message.
Specifically, the 16 input terminals of the second selection unit MUX16_1 are sequentially connected from the low order to the high order to the W 1 storage unit, the W 2 storage unit, the W 3 storage unit, the W 4 storage unit, the W 5 storage unit, the W 6 storage unit, the W 7 storage unit, the W 8 storage unit, the W 9 storage unit, the W 10 storage unit, the W 11 storage unit, the W 12 storage unit, the W 13 storage unit, the W 14 storage unit, the W 15 storage unit, the W 0 storage unit, and the output terminal of the second selection unit outputs the second selection message.
The 0 th bit input end of the second selection unit is connected with the 9 th storage unit in the N storage units, the input end after the 0 th bit input end is sequentially connected with the storage units after the 9 th storage unit in a one-to-one correspondence manner, and the output end of the third selection unit outputs a third selection message.
Specifically, the 16 input terminals of the third selection unit MUX16_2 are sequentially connected from the low order to the high order to the W 9 storage unit, the W 10 storage unit, the W 11 storage unit, the W 12 storage unit, the W 13 storage unit, the W 14 storage unit, the W 15 storage unit, the W 0 storage unit, the W 1 storage unit, the W 2 storage unit, the W 3 storage unit, the W 4 storage unit, the W 5 storage unit, the W 6 storage unit, the W 7 storage unit, the W 8 storage unit, and the output terminal of the third selection unit outputs the third selection message.
The 0 th bit input end of the second selection unit is connected with the 14 th storage unit in the N storage units, the input end after the 0 th bit input end is sequentially connected with the storage units after the 14 th storage unit in a one-to-one correspondence manner, and the output end of the fourth selection unit outputs a fourth selection message.
Specifically, the 16 input terminals of the fourth selection unit MUX16_3 are sequentially connected from the low order to the high order to the W 14 storage unit, the W 15 storage unit, the W 0 storage unit, the W 1 storage unit, the W 2 storage unit, the W 3 storage unit, the W 4 storage unit, the W 5 storage unit, the W 6 storage unit, the W 7 storage unit, the W 8 storage unit, the W 9 storage unit, the W 10 storage unit, the W 11 storage unit, the W 12 storage unit, the W 13 storage unit, and the output terminal of the fourth selection unit outputs the fourth selection message.
Wherein the first selection unit MUX16_0, the second selection unit MUX16_1, the third selection unit MUX16_2 and the fourth selection unit MUX16_3 are also selected using a calculator. The selection units are connected with the counter, and each selection unit is configured to select a message input by one of the N input terminals according to the count value of the counter. Here, taking 4 selection units, and 16 input ends of each selection unit as an example, the selection can be performed by using the lower 4 bits of 6 bits or directly using a counter [3:0] with 4 bits in the same manner as the 16 storage units, which is not described herein. It will be appreciated that the counters of the message storage circuit 10 and the multiplexing circuit 20 need to be synchronized, and if both 6bit counters are used, the same counter may be shared.
It will be appreciated that the connection between the 16 inputs of the 4 selection units and the 16 storage units is formed by the above formula (1) and the 4 selection units driving the 4 selection units with the same counter. In other embodiments, if each selection unit is driven by a separate counter, the connection manner of the 16 input ends and the 16 storage units may be changed, for example, the connection is correspondingly performed according to the order of the storage units and the order of the input ends, and the counting order of the 4 counters needs to be designed according to the above formula (1).
Further, referring to fig. 4, fig. 4 is a schematic circuit diagram of an arithmetic logic circuit in an embodiment of a message expansion circuit according to the present application, and the arithmetic logic circuit 30 includes a first arithmetic unit C0, a second arithmetic unit C1, a first adder adder0, a second adder adder1, and a third adder adder.
Wherein the first operation unit C0 performs an operation according to the following formula:
C0(x)＝S7(x)^S18(x)^R3(x) (2)
The second arithmetic unit C1 performs an operation according to the following formula:
C1(x)＝S17(x)^S19(x)^R10(x) (3)
Where x is the input message, S is the cyclic right shift, R is the right shift, the XOR operation, and the superscript of S and R is the right shift number.
Optionally, in conjunction with fig. 5, fig. 5 is a schematic circuit diagram of an arithmetic logic circuit in another embodiment of the message expansion circuit provided by the present application, where the arithmetic logic circuit 30 includes a first arithmetic unit C0, a second arithmetic unit C1, a first adder adder0, a second adder adder1, and a third adder adder.
In the present embodiment, the arithmetic logic circuit 30 further includes a first register B0 and a second register B1, wherein the first register B0 is connected between the first adder adder and the third adder adder and is configured to temporarily store the message output by the first adder adder. The second register B1 is connected between the second adder adder and the third adder adder, and is configured to temporarily store the message output by the second adder adder1 to improve the operation efficiency of the message.
Alternatively, the first register B0 and the second register B1 may be registers or latches, which are controlled by a clock signal.
Optionally, in other embodiments, the arithmetic logic circuit 30 may further include a 2-out-of-1 selector MUX2_0, one input of which is connected to the output of the third adder adder2, and the other input of which is configured to input the initial message, i.e., the selector MUX2_0 selects to output the initial message in the first 16 clock cycles, and the selector MUX2_0 selects to output the message output by the third adder adder from the 17 th clock cycle.
Unlike the prior art, the message expansion circuit provided in this embodiment includes: a message storage circuit including a first number of storage units configured to store an input message to one of the first number of storage units; a multiplexing circuit connected to the first number of memory cells and configured to select a second number of messages among the first number of messages stored in the first number of memory cells; and the operation logic circuit is connected with the multiplexing circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages, and input and output the messages to the message storage circuit. Through the mode, the N storage units and the multi-path selection circuit are matched to store and select the messages, each message is output through the selector after being stored in one storage unit, and the messages are not required to be shifted and stored in a plurality of storage units, so that the problem that each message is stored once in the N storage units is avoided, the enabling times of one storage unit in one rotation period based on a secure hash algorithm is reduced, and the dynamic power consumption of the circuit is reduced.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a chip provided by the present application, the chip 60 includes a message expansion circuit 100, and the circuit structure and the working principle of the message expansion circuit 100 are described in the above embodiments, which are not repeated here.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a household appliance 70 according to the present application, wherein the household appliance 70 includes a chip 60, and the chip 60 is a chip as in the above embodiment.
Wherein the chip 60 is provided in the home appliance for message expansion of the secure hash algorithm.
Referring to fig. 8, fig. 8 is a flow chart of an embodiment of a message expansion method provided by the present application, where the method includes:
Step 81: an initial message is obtained.
In the embodiment of fig. 1 and 2, the SHA256 algorithm is taken as an example, and the SHA256 algorithm has 16 initial messages in total.
Step 82: the initial message is stored in one of the first number of memory locations.
The 16 initial messages can be input into 16 storage units for storage in a serial or parallel mode.
Alternatively, in an embodiment, step 82 may specifically be: acquiring a count value of a counter; one of the first number of clock-off units is enabled according to the count value, and one message of the current time sequence input is stored in a storage unit corresponding to the enabled clock-off unit.
Step 83: a second number of messages of the first number of messages stored by the first number of storage units is selected.
The selection manner of the M (second number) messages may be determined according to a specific algorithm type, and, taking SHA256 algorithm as an example, the selection may be performed according to formula (1), and specifically, reference may be made to the above embodiment, which is not described herein again.
Alternatively, M N (first number) 1-choice selecting units are employed to select one message from the N messages, respectively.
Step 84: and logically calculating the second number of messages to obtain an output message, and storing the output message in one of the first number of storage units.
Wherein N, M is a positive integer, and N is not less than M.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a computer readable storage medium 90, where program data 91 is stored in the computer readable storage medium 90, and the program data 91, when executed by a processor, is configured to implement the following method:
Acquiring an initial message; storing the initial message to one of the first number of storage units; selecting a second number of messages from the first number of messages stored in the first number of storage units; and logically calculating the second number of messages to obtain an output message, and storing the output message in one of the first number of storage units.
Referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of a home appliance provided by the present application, the home appliance 70 includes a processor 71 and a memory 72, the memory 72 stores program data, and the processor 71 is configured to execute the program data to implement the following method:
Acquiring an initial message; storing the initial message to one of the first number of storage units; selecting a second number of messages from the first number of messages stored in the first number of storage units; and logically calculating the second number of messages to obtain an output message, and storing the output message in one of the first number of storage units.
It will be appreciated that in the various embodiments described above, the integrated circuit and computer readable storage medium on which the software is executable may be configured as a computer, cell phone or other device having data processing capabilities in addition to being configured as a home appliance, and may be configured as a server or as a network node in a network, for example, a network node in a blockchain network.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes according to the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present application.
Claims (15)
1. A message expansion circuit, the message expansion circuit comprising:
a message storage circuit comprising a first number of storage units configured to store an input message to one of the first number of storage units;
a multiplexing circuit connected to the first number of memory cells and configured to select a second number of messages among the first number of messages stored in the first number of memory cells; the multi-path selection circuit comprises a second number of selection units, the selection units comprise a first number of input ends, the first number of input ends are correspondingly connected with the first number of storage units, and the selection units are configured to select one of the first number of storage units to store information for output;
And the operation logic circuit is connected with the multiplexing circuit and the message storage circuit and is configured to logically operate the second number of messages to obtain output messages, and input the output messages to the message storage circuit.
2. The message expansion circuit of claim 1, wherein,
The message storage circuit further comprises a first number of clock shut-off units, the enabling ends of the clock shut-off units are configured to input corresponding enabling signals, the input ends of the clock shut-off units are configured to input clock signals, and the output ends of the clock shut-off units are connected with the corresponding storage units.
3. The message expansion circuit of claim 2, wherein,
The message storage circuit further includes a counter;
The enabling end of the first number of clock shut-off units is connected with the counter, the counter is configured to enable one of the first number of clock shut-off units according to a count value, the enabled clock shut-off units drive the corresponding storage units by using the clock signals, and one message of current time sequence input is stored in the storage units corresponding to the enabled clock shut-off units.
4. The message expansion circuit of claim 3, wherein,
The first number is 16, the counter is a 6bit counter configured to enable one of the first number of clock off units according to a lower 4 bits of the count value.
5. The message expansion circuit of claim 1, wherein,
The multiplexing circuit further comprises a counter;
The second number of selection units is connected to the counter, and the selection units are configured to select messages input by a corresponding one of the first number of input terminals according to the count value of the counter.
6. The message expansion circuit of claim 5, wherein,
The first number is 16, the second number is 4, the counter is a 6bit counter, and the selection unit is configured to select the message input by one of the first number of inputs based on the lower 4 bits of the count value.
7. The message expansion circuit of claim 6, wherein,
The serial numbers of the first number of storage units are sequentially 0 to 15, and the serial numbers of the first number of input ends of the selection units from low order to high order are sequentially 0 to 15;
The multiplexing circuit includes:
The first selecting unit, the 0 th bit input end of the first selecting unit is connected with the 0 th memory unit in the N memory units, the input end behind the 0 th bit input end is sequentially connected with the memory units behind the 0 th memory unit in a one-to-one correspondence, and the output end of the first selecting unit outputs a first selecting message;
the 0 th bit input end of the second selection unit is connected with the 1 st storage unit in the N storage units, the input end behind the 0 th bit input end is sequentially and correspondingly connected with the storage units behind the 1 st storage unit one by one, and the output end of the second selection unit outputs a second selection message;
The 0 th bit input end of the second selection unit is connected with the 9 th storage unit in the N storage units, the input end behind the 0 th bit input end is sequentially and correspondingly connected with the storage units behind the 9 th storage unit one by one, and the output end of the third selection unit outputs a third selection message;
And the 0 th bit input end of the second selection unit is connected with the 14 th storage unit in the N storage units, the input end behind the 0 th bit input end is sequentially and correspondingly connected with the storage units behind the 14 th storage unit one by one, and the output end of the fourth selection unit outputs a fourth selection message.
8. The message expansion circuit of claim 7, wherein,
The arithmetic logic circuit includes:
the first operation unit is connected with the output end of the second selection unit and is configured to operate the second selection message and output a first operation message;
A first adder, connected to the first selection unit and the first operation unit, configured to add the first selection message and the first operation message;
The second operation unit is connected with the output end of the fourth selection unit and is configured to operate the fourth selection message and output a second operation message;
A second adder configured to add the third selection message and the second operation message, the second adder being connected to the third selection unit and the second operation unit;
and a third adder, connected to the first adder and the second adder, configured to add the message output by the first adder to the message output by the second adder, and output the added message to obtain the output message.
9. The message expansion circuit of claim 8, wherein,
The arithmetic logic circuit further includes:
A first register connecting the first adder and the third adder, the first register configured to register a message output by the first adder;
and a second register connecting the second adder and the third adder, the second register being configured to register a message output from the second adder.
10. A chip comprising a message expansion circuit according to any of claims 1-9.
11. A household appliance, characterized in that it comprises a chip as claimed in claim 10.
12. A method of message expansion, the method comprising:
Acquiring an initial message;
Storing the initial message to one of a first number of storage units;
Selecting a second number of messages from the first number of messages stored in the first number of storage units; the method comprises the steps that a second number of selection units are adopted, the selection units comprise a first number of input ends, the first number of input ends are correspondingly connected with the first number of storage units, and the selection units are configured to select one stored message in the first number of storage units to output;
And logically operating the second number of messages to obtain an output message, and storing the output message in one of the first number of storage units.
13. The method of claim 12, wherein the step of determining the position of the probe is performed,
The storing the initial message in one of a first number of memory locations includes:
Acquiring a count value of a counter;
and enabling one clock shut-off unit in the first number of clock shut-off units according to the count value, and storing a message input at the current time sequence into the storage unit corresponding to the enabled clock shut-off unit.
14. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein program data, which when being executed by a processor, is adapted to carry out the steps of the method according to claim 12 or 13.
15. A household appliance comprising a processor and a memory, the memory having stored therein program data, the processor being configured to execute the program data to implement the steps of the method according to claim 12 or 13.
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| US4357678A (en) * | 1979-12-26 | 1982-11-02 | International Business Machines Corporation | Programmable sequential logic array mechanism |
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| US5151986A (en) * | 1987-08-27 | 1992-09-29 | Motorola, Inc. | Microcomputer with on-board chip selects and programmable bus stretching |
| JPH07262002A (en) * | 1994-03-17 | 1995-10-13 | Toshiba Corp | Logic circuit |
| JP2005057452A (en) * | 2003-08-01 | 2005-03-03 | Matsushita Electric Ind Co Ltd | Programmable logic circuit |
| US10097345B2 (en) * | 2015-04-14 | 2018-10-09 | PeerNova, Inc. | Secure hash algorithm in digital hardware for cryptographic applications |
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