JPH05251656A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce adverse influences such as etching residues due to ground steps and decreases in finish dimensions of a storage node electrode in formation of a capacitor storage node electrode with regard to the structure of memory cell of stacked cell structure and its manufacture. CONSTITUTION:An insulating film which overlies a switching transistor formed over a semiconductor substrate 101 is made in a double-layer structure of a thin insulating film 107 about 100nm or less thick and a thick insulating film 108 about 400nm or more thick, where the insulating film 108 is flattened by heat treatment and pierced by a contact hole 109, and the contact hole 109 is inner-walled with an insulating film 110, then capacitors 111, 112, 113 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a memory cell portion of a stacked cell structure of a semiconductor memory device.

[0002]

2. Description of the Related Art A DRAM is a one-transistor / one-capacitor type memory cell mounted in high density. The area of this memory cell becomes smaller with higher integration.
On the other hand, even if unnecessary charges such as leak current and alpha particles flow into the capacitor, the memory cell needs to perform a stable storage operation. Therefore, a three-dimensional structure is used for the capacitor.

A stacked capacitor is one of the three-dimensional structures. The structure of a conventional semiconductor memory device using this stacked capacitor will be described with reference to the sectional view of FIG.

The conventional semiconductor memory device shown in the figure is formed on a P-type silicon substrate 1, a field oxide film 2 formed on the surface layer of the P-type silicon substrate 1, and a P-type silicon substrate 1 adjacent to the field oxide film 2. Switching transistor (3, 4, 5A, 5B), the surface of the insulating film 9 covering the switching transistor and the field oxide film 2
And stacked capacitors 6, 7, and 8 formed on the surface of the.

The switching transistor comprises a gate oxide film 3 formed on the surface of a P-type silicon substrate 1, a gate electrode 4 formed on the upper surface of the gate oxide film 3, and P-type silicon substrates on both sides of the gate oxide film 4. 1 and source / drain diffusion layers 5A and 5B connected to the gate oxide film 3 in FIG.

Further, the stacked capacitors 6, 7,
Reference numeral 8 indicates a storage node electrode 6 formed on each surface of the insulating film 9 and the field oxide film 2, a dielectric thin film 7 covering the surface of the storage node electrode 6, and a surface of the dielectric thin film 7. And the plate electrode 8 formed as described above.

Further, the stacked capacitor 6,
An interlayer insulating film 13 is formed on the entire surface on the 7 and 8 side. A bit contact hole 11 reaching the source / drain diffusion layer 5B is provided in the interlayer insulating film 13. In addition, the bit contact hole 11 is formed on the surface of the interlayer insulating film 13.
A bit line 12 connected to the source / drain diffusion layer 5B via is disposed. A passivation film 14 is formed on the entire surface of the bit line 12 side.

[0008]

However, the conventional semiconductor memory device having the above structure has the following problems. In the stacked cell, the capacitor is formed so as to be picked up on the switching transistor or the field oxide film, so that the surface step becomes large, which hinders fine patterning. In particular, when patterning the storage node electrode of a capacitor, etching residue is likely to occur in the recess of the underlying step, which significantly reduces the yield and when overetching is lengthened to eliminate etching residue, the finished dimension of the storage node electrode Becomes smaller and the capacitor area is reduced.

An object of the present invention is to provide an excellent memory device by reducing the surface step difference in the stacked cell described above.

[0010]

According to the present invention, in a stacked cell, surface flatness is reduced by sufficiently flattening a capacitor before forming the capacitor.

That is, the insulating film between the switching transistor and the capacitor has a two-layer structure of a thin oxide film or nitride film containing no impurities and an oxide film containing a high concentration of impurities such as BPSG and PSG, and is subjected to reflow by heat treatment. The insulating film is flattened.

[0012]

As described above, according to the present invention, the insulating film is flattened before forming the capacitor, so that the patterning of the storage node electrode formed thereon can be facilitated. Further, if an oxide film is formed on the inner wall of the contact hole formed in this insulating film, the storage node does not come into direct contact with the oxide film containing a high concentration of impurities, and the impurities are intercalated through the polysilicon by the heat treatment in a later step. Is also prevented from diffusing into the diffusion layer. Further, this oxide film can prevent a short circuit between the storage node and the gate electrode.

[0013]

1 is a cross-sectional view showing a first embodiment of the present invention, in which a field oxide film 102 is formed on a P-type silicon substrate 101 and an active region where no field oxide film is formed is formed. A switching transistor (MI including a gate oxide film 103, a gate electrode 104, and source / drain N-type diffusion layers 105 and 106).
S transistor) is formed. Gate electrode 10
On the 4, N-type diffusion layers 105 and 106 and the field oxide film 102, an oxide film 107 containing no impurities or having a low concentration is deposited in a thickness of about 50 to 100 nm. Furthermore, an oxide film 108 containing a high concentration of impurities such as boron and phosphorus is formed thereon with a film thickness of 300 to 800 nm. The oxide film 108 is flattened, and the surface is almost flat. Further, in the oxide film 108 and the thin oxide film 107 thereunder, the contact hole 1 reaching the diffusion layer of the switching transistor is formed.
A hole 09 is formed, and an oxide film 110 containing no impurities or containing a low concentration is thinly formed (for example, a film thickness of about 50 to 100 nm) on the inner wall thereof. Further, a storage node electrode 111 of the capacitor is formed thereon with a film thickness of about 50 to 100 nm, and is electrically connected to the diffusion layer 106. The capacitor is composed of this storage node electrode 111, the dielectric thin film 112 and the cell plate electrode 113 formed thereon. Here, since the underlying oxide film 108 is almost completely flattened, patterning is facilitated and the gap between adjacent storage nodes can be reduced, and the cell area limited by the area of the storage node electrode 111. It can take a big inside. An insulating film 114 is formed on the capacitor, and a contact hole 115 for connecting the bit line 116 and the diffusion layer 105 of the switching transistor is opened. Further, an insulating film 117 and a word line 118 are formed on the bit line 116. The word line 118 is made of a low resistance material such as aluminum alloy and is connected to the gate electrode 104 of the switching transistor through a contact hole (not shown). A passivation film 119 for protection is formed on the uppermost layer.

The operation of the memory cell having such a structure is as follows. In the write operation, the potential corresponding to the information "1" or "0" is applied to the bit line 116, the potential of the word line 118 is set to the high level, the switching transistors (103 to 106) are made conductive, and the bit line 116 is made conductive.
The potential of is written in the capacitors (111, 112, 113). The holding operation is performed by setting the word line 116 to a low level to switch the switching transistors (103 to 10).
6) is made non-conductive and the capacitor is floated. In the read operation, after precharging the bit line 116 to a constant potential, the word line 118 is set to a high level, the switching transistor is made conductive, and the information of the capacitor is passed to the bit line 116. At this time, the size of the capacitor charge (corresponding to information "1", "0")
The potential of the bit line 116 fluctuates in response to this, and this is amplified by a sense amplifier and read.

Next, a second embodiment will be described with reference to FIG. The structure up to the insulating film on the switching transistor (101 to 108 parts) is the same as that of the first embodiment (FIG. 1). The storage node electrode 111 of the capacitor is composed of a thick conductor layer 201 formed on a portion other than the contact hole 109 and a thin conductor layer 111 formed on the 201 and in the contact hole 109. On the inner surface of the contact hole, a thin insulating film 110 is interposed between the storage node electrode 111 and the insulating film 108. Capacitor dielectric thin film 112
The configuration above is the same as that of the first embodiment. The operation is also the same.

Next, the manufacturing method in the first embodiment is shown in FIG. 3 and will be described below. A field oxide film 102 is formed on a P-type silicon substrate 101 by a selective oxidation method or the like. Forming a gate oxide film 103 of the switching transistor in the active region by thermal oxidation,
A gate electrode 104 is formed on the gate electrode 104 using polysilicon containing a high concentration of impurities such as phosphorus, and is patterned. By using the gate electrode 104 and the field oxide film 102 as a mask, N such as arsenic (As) is formed in the P-type substrate 101.
Diffusion layers 105 and 106 are formed by ion-implanting type impurities (FIG. 3A). After forming the switching transistor, a CVD (chemical vapor deposition) oxide film 107 containing no impurities is thinly formed to a film thickness of about 100 nm or less, and BPSG (boron phosphorus silicate glass) and PSG are formed on the thin film. An insulating film 108 having a heat flow property, such as (phosphorus / silicate glass), is deposited to a thickness of about 400 nm or more by the CVD method. Then 800
Alternatively, reflow is performed in an N ₂ atmosphere at about 1000 ° C. to make the surface of the insulating film 108 substantially flat (FIG. 3).
(B)).

After that, a contact hole 109 for connecting the capacitor and the switching transistor is formed in the insulating films 107 and 108. C containing no impurities on the entire surface
After forming the VD oxide film, the oxide film 110 is left only on the inner wall portion of the contact hole 109 by dry etching having strong anisotropy (FIG. 3C). Subsequently, thin polysilicon (having a film thickness of about 100 nm) to be the storage node electrode 111 of the capacitor is formed by the CVD method, and arsenic or phosphorus is introduced to have conductivity. After patterning the storage node electrode 111, a silicon nitride film to be the dielectric thin film 112 of the capacitor is deposited by CVD to a thickness of 6 to 8 nm, and polysilicon to be the cell plate electrode 113 is deposited thereon by CVD. Is deposited to a film thickness of about 150 to 300 nm, and phosphorus is doped at a high concentration. When the patterning of the cell plate electrode 113 is completed, FIG.
The shape is as shown in (d).

Although not shown, the insulating film 114 shown in FIG. 1 is formed of a material such as BPSG, a contact hole 115 for connecting the bit line and the switching transistor is formed, and the bit line 116 is polycide. (Silicide is laminated on polysilicon) or the like. Further, the insulating film 117 is formed of a material such as BPSG, and a contact hole that connects the word line and the gate electrode of the switching transistor is opened.
The word line 118 is formed of a material such as an aluminum alloy.
Finally, a passivation film 119 is applied and the wafer process is completed.

As a modification of this manufacturing method, the following method may be used in order to achieve the flatness before the formation of the storage node electrode 111 by a low temperature heat treatment. That is, the thin insulating film 107 is formed of a nitride film, and heat treatment for reflow is performed in an oxidizing atmosphere (wet O ₂ or dry O ₂ ). By doing so, the same degree of flatness can be obtained at a temperature lower by 50 to 200 ° C. than when reflowing in a non-oxidizing atmosphere. Further, when the same temperature is used, flattening is further promoted. Since the insulating film 107 is made of a nitride film having low permeability of oxidizing species, the underlying diffusion layer and the gate electrode are not oxidized.

Next, the manufacturing method in the second embodiment will be described with reference to FIG. Until the insulating film 108 is formed, it is the same as the manufacturing method of the first embodiment described above (FIGS. 3A and 3B). On top of this structure, the polysilicon 20 that will become part of the storage node electrode of the capacitor is
1 is deposited to a thickness of about 400 nm by the CVD method. To make it conductive, it is doped with phosphorus or arsenic. Then, the polysilicon 201 and the insulating films 108 and 10
7 through the contact hole 109, and
The contact hole 10 is formed by a method similar to the method of the embodiment.
An insulating film 110 is formed on the inner wall 9 (FIG. 4A). Polysilicon 1 that will be a part of the storage node electrode
When 11 is formed with a film thickness of 50 to 100 nm and the storage node electrode is patterned, a shape as shown in FIG. 4B is obtained. Since the same method as that of the first embodiment can be used for the subsequent steps, the description thereof will be omitted. Also here, as described in the manufacturing method of the first embodiment, the insulating film 107 is used.
It is also possible to use an oxidizing atmosphere reflow as the nitride film.

[0021]

As described above in detail, according to the present invention, the insulating film between the switching transistor and the capacitor has a thin oxide film or nitride film containing no impurities and a high concentration of impurities such as BPSG and PSG. Since it has a two-layer structure with the oxide film included in the above and the insulating film is flattened by the reflow by the heat treatment, there is an advantage that the storage node electrode formed thereon can be easily patterned. That is, no etching residue occurs and the yield is improved. Further, since the oxide film is formed on the inner wall of the contact hole formed in this insulating film, the storage node electrode does not come into direct contact with the oxide film containing a high concentration of impurities, and the polysilicon is formed by heat treatment in a later step. Impurities are also prevented from diffusing into the diffusion layer through. Further, this oxide film can prevent a short circuit between the storage node and the gate electrode.

[Brief description of drawings]

FIG. 1 is a structural diagram of a first embodiment of the present invention.

FIG. 2 is a structural diagram of a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the first embodiment of the present invention.

FIG. 4 is a manufacturing process drawing of the second embodiment of the present invention.

FIG. 5 is a structural diagram of a conventional example.

[Explanation of symbols]

 101 substrate 107 low concentration oxide film 108 high concentration oxide film 109 contact hole 110 oxide film 111 storage node electrode 112 dielectric film 113 cell plate electrode

Claims (4)

[Claims] 1. A first insulating film formed on a switching transistor formed on a semiconductor substrate and the first insulating film.
Second insulating film thicker than the second insulating film, contact holes formed in the second and first insulating films, a third insulating film formed on the inner wall of the contact hole, and at least in the contact hole And a storage node electrode of the capacitor formed on the storage node electrode, a dielectric thin film of the capacitor formed on the storage node electrode, and a cell plate electrode of the capacitor formed on the dielectric thin film. Memory device. 2. A first insulating film formed on a switching transistor formed on a semiconductor substrate, a second insulating film thicker than the first insulating film, and formed on the second insulating film. First storage node electrode of the formed capacitor, the first storage node electrode, a second insulating film,
And a contact hole formed in the first insulating film,
A third insulating film formed on the inner wall of the contact hole, a second insulating film formed on the first storage node electrode and in the contact hole, and electrically connected to the first storage node electrode. A semiconductor memory device comprising: a storage node electrode, a dielectric thin film of a capacitor formed on the storage node electrode, and a cell plate electrode of the capacitor formed on the dielectric thin film. 3. A step of: (a) forming a switching transistor on a semiconductor substrate and forming a first insulating film on the entire surface thereof; (b) forming a first insulating film on the first insulating film with a film thickness of the first film; Forming a second insulating film thicker than the insulating film, and flattening the insulating film by heat treatment, (c) forming contact holes in the laminated first and second insulating films, and A step of forming a third insulating film on the inner wall of the contact hole, (d) a storage node electrode as a capacitor, a dielectric film, and a cell plate electrode are provided in a portion including the inside of the contact hole where the third insulating film is formed. A method of manufacturing a semiconductor memory device, which comprises the steps of forming and the above steps. 4. A step of: (a) forming a switching transistor on a semiconductor substrate and forming a first insulating film on the entire surface thereof; (b) forming a first insulating film on the first insulating film with a film thickness of the first film. A second insulating film thicker than the second insulating film and flattening the insulating film by heat treatment, (c) forming a first conductor layer to be a storage node electrode on the second insulating film. (D) forming a contact hole in the laminated first and second insulating films and the first conductor layer and forming a third insulating film on the inner wall of the contact hole; A step of forming a storage node electrode as a capacitor, a dielectric film, and a cell plate electrode in a portion including the inside of the contact hole where the third insulating film is formed, and manufacturing of a semiconductor memory device including the above steps Method.