JPH05218074A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the method for manufacturing, as it is called, the LDD structure wherein a low-impurity-density region is specially formed at the channel side of a source, drain diffusion layer for the purpose of forming a source and a drain region of a silicon gate MOS transistor. CONSTITUTION:A polycrystalline semiconductor layer 3 is formed on a semiconductor substrate 1 through an insulating film 2. Using mask material including the insulating film 2, the polycrystalline semiconductor layer 3 is selectively etched. Before forming an impurity region in the semiconductor substrate 1 by ion implantation with the mask material and the polycrystalline semiconductor layer 3 being used as a mask, the polycrystalline semiconductor layer 3 is etched again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a silicon gate MOS.
The present invention relates to a method for forming a source / drain region of a transistor, and particularly, a so-called LDD structure (Light) having a low impurity concentration region provided on the channel side of a source / drain diffusion layer.
The present invention relates to a manufacturing method of tly Doped Drain).

[0002]

2. Description of the Related Art At present, the miniaturization of silicon gate MOS transistors is at a practical level and the gate length is 1 μm.
It has reached the stage of m or less. Along with this miniaturization, problems such as reduction of drain breakdown voltage and generation of hot electrons occur due to electric field concentration in MOS transistors. As a method for solving this problem, a so-called LDD structure (hereinafter abbreviated as LDD structure) in which a low-concentration region of impurities is formed on the channel side of the source and drain regions is formed to reduce electric field concentration in the drain region. The method of doing is becoming popular. As a method for forming the source and drain of this LDD structure MOS transistor, the conventional method shown in FIG.
The method shown in is used. First, the silicon substrate 1 is thermally oxidized to form the gate silicon oxide film 2 of the MOS transistor. Further, a polycrystalline silicon film 3 is formed on the entire surface by a chemical vapor deposition method, and N-type impurities (phosphorus or arsenic) are thermally diffused to make them conductive. This is shown in FIG. 2a. Next, the polycrystalline silicon 3 is photo-etched to form a gate electrode 3 ', and the gate electrode 3'is formed.
Is used as a mask to form the low-concentration diffusion regions 10 and 20 of the impurities necessary for the LDD structure of the source and drain of the MOS transistor by ion implantation shown by I ₁ . This results in the shape of Figure 2b. Further, after the silicon nitride film 5 is formed on the entire surface by the chemical vapor deposition method (FIG. 2c), the silicon nitride film 5 on the gate electrode 3'is completely removed by a dry etching method with good directionality such as reactive ion etching. Etching is performed until it is removed. By this etching, the silicon nitride film 5'is left only on the side wall of the gate electrode 3 '. Then, the high concentration diffusion region 1 of the required impurity source, as the drain by ion implantation showing the silicon nitride film 5 'and the gate electrode 3' to I ₂ as a mask
1, 21 are formed. Then, heating annealing is performed to activate the entire source and drain regions, and the source and drain of the LDD structure are formed as shown in FIG. 2d.

[0003]

The conventional method shown here has many ion implantation mask steps and complicated manufacturing steps. There are also the following drawbacks. That is, in FIG. 2d, the silicon nitride film 5'remaining on the side wall of the gate electrode 3'is formed by a dry etching method with good directionality. Actually, however, the thickness tn of the silicon nitride film 5'in the side wall direction can be controlled. Difficult and subject to variations. Therefore, in the LDD structure of the source and the drain of the MOS transistor formed by ion implantation using the silicon nitride film 5'and the gate electrode 3'as a mask, only the low-concentration impurity diffusion regions 10 and 20 just below the gate electrode 3'are formed. The variation of the width ld becomes large. As a result, variations occur in the drain breakdown voltage, threshold voltage, etc. of the LDD structure MOS transistor. The main purpose of the present invention is LD
It is to simplify the process for forming the source and drain of a D-structure MOS transistor. A second object is to reduce the variation in the low-concentration diffusion region width of the source and drain in the channel region immediately below the gate electrode of the MOS transistor having the above structure.

[0004]

In order to achieve the above object, the present invention forms a gate electrode by etching a polycrystalline silicon film using a photo-etched silicon nitride film as a mask, and an LDD structure source. In the ion implantation for forming the drain diffusion region, contrary to the conventional method, the ion implantation for forming the high concentration diffusion region of the LDD structure is performed first, and the ion implantation for forming the low concentration diffusion region is performed thereafter. However, in the etching for forming the gate electrode, the electrode is first formed by etching with good directionality, and then the side surface of the polycrystalline silicon film of the electrode is etched by isotropic etching.

[0005]

Next, the operation of the present invention will be described. When etching the polycrystalline silicon film to form electrodes,
The reason why the silicon nitride film is used instead of the photoresist mask of the conventional method is to etch the side surface of the polycrystalline silicon film, which is the gate electrode, with good controllability. Also,
The order of ion implantation for forming the source and drain diffusion regions of the LDD structure MOS transistor is reversed from that of the conventional method, because the silicon nitride film of the mask at the time of forming the gate electrode is used as a mask for further ion implantation. Is. That is, ion implantation for a high concentration region of the LDD structure source and drain is performed using the silicon nitride film of the mask as a mask, and then the silicon nitride film is removed to use the gate electrode itself of the polycrystalline silicon film as a mask for the low concentration region. Ion implantation is performed. According to the present invention, a mask obtained by photo-etching a silicon nitride film instead of a photoresist is used, and a gate electrode of a polycrystalline silicon film formed by etching is further subjected to isotropic etching by using the mask of the silicon nitride film as it is, and a side surface of the gate electrode is formed. Therefore, the controllability of the etching amount on the side surface, that is, the so-called side etching amount is good. In order to utilize this feature, the order of ion implantation for forming the diffusion regions of the LDD structure source and drain is reversed as described above. As a result, the side etch amount of the gate electrode becomes almost the width of the low concentration diffusion region just below the gate electrode of the LDD structure source and drain, and the controllability of the width of this diffusion region is also improved. Also, regarding the etching process, the manufacturing process is simplified because it is sufficient to make a mask by photo-etching the silicon nitride film for forming the gate electrode. Also,
Since the etching of the gate electrode is also performed by the dry etching method, it is possible to continuously switch from the etching with good directionality to the isotropic etching by only partially changing the composition of the etching gas, which makes the process complicated. Absent. However, it is necessary to increase the thickness of the silicon nitride film of the mask so that it is not completely etched during the etching for forming the gate electrode. This film thickness also depends on the etching selectivity between polycrystalline silicon and silicon nitride in the etching gas. Further, the length of the gate electrode of the MOS transistor on the photomask needs to be set in consideration of the side etching amount of the polycrystalline silicon film at the time of forming the gate electrode. As described above, the source / drain diffusion regions of the LDD structure MOS transistor can be formed with better controllability as compared with the conventional method shown in FIG.

[0006]

Embodiments of the present invention will be described below with reference to FIGS. Since FIG. 1a has undergone the same steps as the conventional example, a description thereof will be omitted. FIG. 1b shows a state in which a silicon nitride film formed on the entire surface of the polycrystalline silicon film 2 by the chemical vapor deposition method is photo-etched for a gate electrode formation mask, and the polycrystalline silicon film 5'is used as a mask. The silicon film 2 is dry-etched. First, the gate electrode 3'is formed by performing etching under the condition of good directionality. This is shown in FIG. 1c. Next, the isotropic etching conditions are switched to continue the etching, and the gate electrode 3'of the polycrystalline silicon film is side-etched by a predetermined amount .DELTA.lg to form the final gate electrode 3 ". Using the silicon nitride film 5'as a mask, ion implantation I ₁ is performed to form the high-concentration diffusion regions 11 and 21 of the LDD structure source and drain. Ion implantation I ₂ for forming the diffusion regions 10 and 20 is performed using the gate electrode 3 ″ as a mask. This state is shown in FIGS. Further, source / drain diffusion regions 10, 11, 20, 21
After the heat annealing step for activating the, the process proceeds to the next step. As I mentioned in the previous section,
In the present invention, since the gate electrode 3'of the polycrystalline silicon film is side-etched using the silicon nitride film 5'as a mask, the side etch amount Δlg is well controllable, and the LDD
Structure Source and drain diffusion regions 10, 11, 20, 21
Of the low-concentration diffusion region just under the gate electrode 3 ″ of
Is approximately equal to the side etching amount Δlg described above, and therefore the width l ′ of only the low concentration diffusion regions of the source and drain is
It can be seen that the controllability of d is improved. Further, it can be seen that the process is simpler than that of the conventional example shown in FIG.

[0007]

As described above, according to the present invention, an LD can be formed by a simple process with few masking steps for ion implantation.
It is possible to improve the controllability of the LDD structure formation of the source and the drain by reducing the variation of the impurity low-concentration diffusion region width in the channel region immediately below the gate electrode in the source and drain of the D-structure MOS transistor.
As a result, variations in characteristics such as drain withstand voltage and threshold voltage of the LDD structure MOS transistor can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process of a MOS transistor according to the present invention.

FIG. 2 is a sectional view showing a part of a manufacturing process by a conventional method.

[Explanation of symbols]

1 Silicon Substrate 2 Silicon Oxide Film 3, 3 ', 3 "Polycrystalline Silicon Film 5, 5' Silicon Nitride Film 10, 20 Source / Drain Diffusion Region (Low Concentration) 11, 21 Source / Drain Diffusion Region (High Concentration) lg , L'g Width of low-concentration region directly under gate electrode Δlg Side etching amount of gate electrode I ₁ , I ₂ Ion implantation for forming source and drain diffusion regions

Claims (1)

[Claims] 1. A polycrystalline semiconductor layer is formed on a semiconductor substrate via an insulating film, and the polycrystalline semiconductor layer is selectively etched by using a mask material including an insulating film to form the mask material and the polycrystalline semiconductor. A method of manufacturing a semiconductor device, wherein the polycrystalline semiconductor layer is etched again in forming an impurity region in the semiconductor substrate by an ion implantation method using the layer as a mask.