JPH05216847A - Information processor - Google Patents

Abstract

PURPOSE:To improve the throughput of a CPU by constituting the processor so that a write processing to an internal register by the CPU itself is made unnecessary, and also, the CPU can immediately send out data related to a different mode after sending-out of data related to one mode is finished. CONSTITUTION:A data working circuit 201 is provided with internal registers 2021...202m, executes working of data to be worked in accordance with their data, and sends out the processed data to a data line 205. Its data to be processed is written in an input register 206 by an input control circuit 216. With respect to the data in this input register 206, a control circuit 212 executes a data setting processing to the internal register, a working processing of the data to be worked, and pass-through of passing data conforming to a state of a C/*D field and mode information by cooperation with the data working circuit 201, a selector 210 and an output control circuit 221.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device forming each stage of an information processing pipeline.

[0002]

2. Description of the Related Art In a conventional information processing system having various data processing means, when performing the processing, the CPU generally provides control data such as functions and parameters necessary for the processing and processed data. The processed data is supplied to the processing means, and thereafter, the processing means processes the data to be processed into a predetermined form by executing arithmetic processing in a mode determined by the set control data.

FIG. 5 shows an example of this type of information processing system. The system shown in this figure has a conventional pipeline data processing system.

In this figure, 501 is a CPU, 502
Is an address bus, 503 is a data bus, and 504 is a control bus.

A plurality of pipeline stages 5051, 5052, ... Are connected to these buses 502-504. 5061, 5062, ... Address lines from the address bus 502 to the respective stages 5051, 5052 ,.
5071, 5072, ... Are data lines from the data bus 503 to the respective stages 5051, 5052 ,.
5082, ... From the control bus 504 to each stage 505
Control lines to 1,5052, .... Bus 502-50
4, an input interface (hereinafter referred to as an input I / F) 509 is connected, 510 is an address line from the address bus 502, and 511 is a data bus 503.
From the control bus 504.

The input I / F 509 and the plurality of stages 5051, 5052, ... Are pipeline-connected, and 513 is the input I / F 509 and the frontmost stage 5051.
A data line 514 connecting to and is also a control line 5151,
Reference numerals 5152, ... Are data lines 5161, 5162, ... Connecting the adjacent stages 5051, 5052 ,.

FIG. 6 shows the internal structure of the stage 5051, and the other stages 5052, 5053, ... Have the same structure.

In this figure, the data processing circuit 601 includes a plurality of internal registers 6021, ..., 602m (however,
m is an integer greater than or equal to 1 and corresponds to the number. )have. Control data necessary for processing the data to be processed are written in these internal registers 6021, ..., 602m through a data line 5061.
The data processing circuit 601 uses the internal register 6021,
The processing of the processed data is performed according to the control data stored in 602m.

When the control signal on the control line 5081 indicates a write command and the stage address of the address signal indicates the address of the self stage, the decoder 603 corresponds to the internal address of the register address of the address signal 6021 ( A write signal is issued to the write control line 6041 (/.../602m) (/.../604m), and the data on the data line 5061 is converted to the corresponding internal register 60.
21 (/.../602m)

Here, the input I / F 509 is a control line 512.
Indicates a write command and the address line 510 indicates its own address, the READY signal is first generated and the WAIT signal does not rise or falls so as to send the data on the data line 511 to the front stage 5051. Waiting for, the data held in the internal register is sent to the data line 513.

The input register 605 has its data line 5
Data of 13 is set, and the data set in the input register 605 is supplied to the data processing circuit 601 as data to be processed. The output data of the data processing circuit 601 is set in the output register 606. The data of the output register 606 is sent to the data line 5151 to the next stage.

Reference numeral 607 is an input control circuit, and 608 is an input I /
READY control line connecting F509 and input control circuit 607,
Similarly, 609 is a WAIT control line, and both signal lines 608,
Reference numeral 609 constitutes the control line 514. 61
Reference numeral 0 is a READY control line connecting the input control circuit 607 and the data processing circuit 601, and reference numeral 611 is a WAIT control line. When the READY signal goes up to the READY control line 608 from the input I / F 509, the input control circuit 607 receives the data processing circuit 6
The status is confirmed by raising the READY signal to the READY control line 610 to 01. At this time, if the WAIT signal goes up to the WAIT control line 611 from the data processing circuit 601, the data processing circuit 601 still has the input register 6
Since the data of No. 05 is in use, the input control circuit 607 raises the WAIT signal to the WAIT control line 609, and thereafter, the WAIT control line 611 of the data processing circuit 601 is also used.
Is monitored, the WAIT signal goes down, and the data processing circuit 60
When it is confirmed that 1 has finished processing the data of the input register 605, the WAIT signal on the WAIT control line 609 is lowered and the write control line 610 to the input register 605 is activated. As a result, the contents of the input register 605 are updated with the data on the data line 513.

613 is an output control circuit, 614 is a READY control line connecting the data processing circuit 601 and the output control circuit 613, 615 is also a WAIT control line, and 616 is connecting the output control circuit 613 and the next pipeline stage 5052. RE
ADY control line 617 is also a WAIT control line. The signal lines 616 and 617 make up the control line 5161. When the data processing circuit 601 completes the predetermined processing for the processed data, the READY control line 614 reads the data.
Increase Y signal. Upon receiving this READY signal, the output control circuit 613 raises the READY signal to the READY control line 616 toward the input control circuit of the next stage 5052. afterwards,
When the WAIT signal rises to the WAIT control line 617, the output control circuit 613 raises the WAIT signal to the WAIT control line 615. When the WAIT signal does not rise or falls on the WAIT control line 617, the output control circuit 613 outputs WA to the WAIT signal line 615.
Do not raise or lower the IT signal. Then, the data processing circuit 601 outputs the data to be processed, and the output control circuit 613.
Activates the write control line 618. as a result,
The contents of the output register 606 are updated by the processed data from the data processing circuit 601.

Next, the operation of the system configured as above will be described.

When it becomes necessary to process certain data, the CPU 501 controls the stages 5051 and 505.
2, 5053, ... In order to set the control data necessary for the processing in each internal register, each stage 5
051, 5052, 5053, ... Sequentially set for each one.

Consider, for example, that the internal registers 6021, ..., 602m of the stage 5051 are set in that order.

In this case, the CPU 501 uses the address bus 5
02 the address of the stage 5051 and the internal register 60
21 and the control data signal to be set in the internal register 6021 are output to the data bus 503, and a write command is output to the control bus 504. As a result, the decoder 603 writes the control data into the internal register 6021 as described above. In this way, the internal register 6
022, ..., 602 m will be set.

When the setting of the stage 5051 is completed, the setting of the next stage 5052 is performed similarly.

By sequentially performing the above for the stages required for the processing of the processed data, the CPU 501
After setting the control data for all the necessary stages, the input I / F 509 is placed on the address bus 502.
Output the address signal of and process data to the data bus 5
03, and a write command is sent to the control bus 504 to execute the processing of sending the processed data.

Then, the data to be processed is converted into the input I / F 50.
Taken in 9. Then, when there is another data to be processed with the same function and parameter, the CPU 501 waits until the input I / F 509 becomes a state in which it can be accepted.

On the other hand, the first processed data is the input I / F5.
09 to the front stage 5051. At this time, as described above, the input control circuit 607 and the input I / F 5
The data to be processed is taken into the stage 5051 by the exchange with the output control circuit of 09. When the first processed data is fetched by the stage 5051, the CPU 501 sends the next processed data according to the notification from the input control circuit of the input I / F 509.

As described above, when the transmission of the processed data to be processed with the same control data is completed, the processed data in another mode is waited for until the transmitted processed data is lost from the last stage. The necessary control data settings are made in the same manner as described above.

By repeating the above cycle, CP
U501 sequentially executes various processing of the processed data.

However, in the above-described information processing system, the CPU 501 finishes sending all the processed data to be processed with the same control data, and then
When it is desired to send the control data that is the target of another processing mode, a waiting time until the processed data that has been sent is lost from the last stage occurs, so that there is a problem that the throughput of the CPU is reduced accordingly. Considering increasing the throughput with the above configuration, a plurality of pipelines are installed side by side and these are switched and used. However, if this is done, not only the circuit becomes large-scale, but also the control becomes complicated. The problem arises.

Further, the problem of throughput is not limited to the above information processing pipeline, and more specifically, it is regarded as a problem in the character data processing system of the high speed page printer.

FIG. 7 shows an example of the conventional character data processing system.

In the figure, 701 is an MPU corresponding to the CPU of the system, 702 is a scale converter which is a kind of data processing circuit, 703 is a data processing circuit for performing other image expansion processing, 704 is a memory,
Reference numeral 705 is an address bus, 706 is a data bus, 707 is a memory address line, and 708 is a data line.

For example, when performing print control of character data,
When the input character data needs to be processed, the MPU 701 sequentially transmits control data and character data necessary for the processing to a predetermined processing circuit. For example, when enlarging / reducing a character, the MPU 701 sets control data such as the magnification to the scale converter 702, and then sends the target character data to be processed to the same scale converter 702. This allows the scale converter 702
The enlargement / reduction processing is performed in and the subsequent data is written in the memory 704. And this memory 704
To the page memory via the input I / F.

If there is still another processed data, the MPU 701 sequentially sets the internal register of the corresponding data processing circuit and supplies the processed data, and expands the characters in the page memory.

As described above, since the MPU 701 is involved in each data, the load is very heavy, the throughput of the entire circuit is also lowered, and it is one of the obstacles to speeding up the printout.

[0031]

As described above, in the conventional data processing information processing system, the load on the CPU is very heavy and the processing is inefficient, which causes a decrease in the throughput of the CPU.

The present invention has been made in view of the problems of the above-mentioned prior art.
An object of the present invention is to provide an information processing apparatus that reduces the burden on U and improves the execution efficiency, and greatly contributes to the improvement in throughput as a whole.

[0033]

In order to achieve this object, an information processing apparatus forming each stage of the information processing pipeline of the present invention is processed in a manner determined by control data written in an internal register. Data processing means for processing data, processed data transfer means for transferring the processed data to the next stage, passing data transfer means for transferring the pass data to the next stage, identification field and mode information in the input data According to the above, processing for setting the data of the data portion to be processed in the input data in the internal register, processing for giving the input data as the processed data to the data processing means, and sending the input data to the data transfer means. And a control means for executing the processing.

[0034]

According to the present invention, the processed data portion of the input data is treated as control data or processed data according to the identification field of the input data and the mode information, and data unrelated to itself is treated as pass-through data. Since the data is transferred to the subsequent stage, if the CPU adds the above-mentioned identification data to the data to be processed and flows it into the pipeline, it will be automatically processed by the corresponding stage. Therefore, if the CPU receives the data at the entrance of the pipeline, the processing is completed, and the CPU does not need to write the control data to the internal register of each stage.
The load on the CPU is reduced.

It should be noted that the data from the CPU to the pipeline is stored in the pipeline in the CPU.
Even if data regarding another mode is input immediately after data input regarding data processing for one mode is input, the data processing for the previous mode is performed. Since the data of the different mode is supplied to the stage after the completion of the process, the CPU immediately transmits the data of the different mode of the data processing after finishing the transmission of the data of the one mode of the data processing. Therefore, there is no processing waiting time as described above, and the throughput of the CPU is greatly improved.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an information processing system according to an embodiment of the present invention.

In this figure, 101 is a CPU and 102
Is an address bus, 103 is a data bus, and 104 is a control bus. The pipeline according to the present invention is connected to the CPU 101 through these bus lines 102 to 104. Reference numeral 105 denotes an input I / which constitutes the entrance of the pipeline.
F, 1061, 1062, ... Are pipeline stages connected to the subsequent stage of the input I / F 105, and 107 is an input I / F1.
Data line connecting 05 and the first stage 1061,
Reference numeral 108 is also a control line, reference numerals 1091, 1092, ... Are data lines connecting adjacent stages, and reference numerals 1101, 1102 ,. Stages 1061, 1062, ...
Have the same configuration.

When the CPU 101 performs the processing by the pipeline, the CPU 101 inputs the input I / F 1 onto the address bus 102.
The address data indicating the address 05 is transmitted, the control data indicating the write command is transmitted to the control bus 104, and the processed data having the structure shown in FIG. 3 is transmitted to the data bus 103. This processed data is shown in FIG.
As shown in (a), a C / * D field 301 is provided in the first 1 bit, and immediately after that, a data field 302 is provided.
Are connected. The C / * D field 301 indicates whether the content of the data field 302 is internal register setting data or processed data. When the C / * D field 301 is "1", the contents of the data field 302 are used as internal register setting data, and the stage address 3 shown in FIG.
03 and the register address 304 and the register setting data 305 shown in FIG. 3D. When the C / * D field 301 is “0”, the entire data field 302 is processed data 306 as shown in FIG. 3C. When performing the pipeline processing, the CPU 101 first sends data in which the C / * D field 301 is set to “1” in order to set the control data in the internal register of the stage necessary for the processing of the entire pipeline. After that, to process the data,
The data with the C / * D field 301 set to "0" is sent.

The input I / F 105 is the address bus 102.
When the upper address data indicates its own address and the control data on the control bus 104 indicates a write command, it is confirmed whether or not the internal input register can be updated, and then the internal input register Data bus 103
Store the above processed data. Whether or not this input register can be updated is determined by checking whether or not the data currently stored in the input register has been processed.
For example, if the data in the input register has been moved to the output register also built in, it is determined that the data has been processed. The input I / F 105 is connected to the CPU 1 after the data storage on the data bus 103 for the input register is completed.
01 is notified to that effect. The CPU 101 maintains the current output data until receiving the notification, and outputs the next data after receiving the notification. Further, the input I / F 105 confirms whether or not the output register can be updated, and then stores the data in the input register in the output register. Whether or not the output register can be updated is confirmed by determining that the data in the output register can be updated if the data in the output register has been sent to the stage 1061 at the frontmost stage, and if not, it cannot be updated.

Further, the input I / F 105 is READY to the control line 108 when the update of the output register is completed.
A signal is output to notify the stage 1061 that the data is ready, and the data in the output register is output to the data line 107.

FIG. 2 illustrates the structure of the stage 1061.

In this figure, the data processing circuit 201 includes a plurality of internal registers 2021, ..., 202m (however,
m is an integer greater than or equal to 1 and corresponds to the number. )have. The data processing circuit 201 writes the control data necessary for processing the data to be processed into the internal registers 2021, ..., 202m through the data line 203.
The processed data from the data line 204 is processed according to the control data written in 202 m, and the processed data after processing is sent to the data line 205.

Data from the CPU 101 is written in the input register 206 through the data line 106. Only the register setting data 305 is transmitted to the data line 203, only the processed data 306 is transmitted to the data line 204, and the processed data is transmitted to the data line 205. 207 is a data line for transmitting only the C / * D field 301, 208 is a data line for transmitting only the stage address 303 and the register address 304, 2
Reference numeral 09 is a passing data line through which all fields 301 and 302 are transmitted.

The decoder 213 receives the stage address 303 and the register address 304 through the data line 208 in response to the write command on the control line 214, and only when the stage address 303 indicates its own stage, the internal register is registered. A write signal is issued to the write control line 2101 (..., 210m) for the one designated by the register address 304 of 2021 ,. As a result, the register setting data 305 is written in the internal register through the data line 203.

The input control circuit 216 uses the READY control line 21.
When READY signal is received through 7, first, WAIT control line 2
The WAIT signal is raised to 18, and after confirming that the input register 206 can be updated, the WAIT signal is lowered and the processed data on the data line 107 is written in the input register 206.

Whether or not the input register 206 can be updated is determined by inquiring of the control circuit 212 as to whether or not the data in the input register 206 has been processed. The case where the data has been processed is the following three types. When the processed data in the input register 206 is the data for setting the internal register, and the setting of the register setting data 305 in the internal register is completed. When the processed data in the input register 206 is to be processed in the data processing circuit, the processing for the processed data is completed in the data processing circuit 201, and the processed output data is stored in the output register 211. If already set. The data to be processed in the input register 206 is already set in the output register 211.

Upon receiving such inquiry, the control circuit 212 receives the status information of the data processing circuit 201,
By referring to its own processing record information, when the corresponding to, the input control circuit 216 is notified that the input register 206 can be updated, and when not corresponding to, the input register 206 cannot be updated. Input control circuit 21
Notify 6.

The input control circuit 216 maintains the WAIT signal until it receives the updatable notification, receives the updatable signal, and simultaneously lowers the WAIT signal and issues a write signal to the write control line 220. As a result, the data to be processed on the data line 107 is written in the input register 206. The input control circuit 216 informs the completion of the control circuit 21.
Notify 2.

This control circuit 212 responds to the notification from the input control circuit 216 from the data line 207 to C / * D.
The field 301 is read and the next [F1] is read according to the state.
~ Perform the process of [F4].

[F1] First, when the C / * D field 301 is "1", the data setting process for the internal register of the data processing circuit 201 is performed. At this time, the control circuit 212 outputs a write command to the decoder 213 through the control line 214. As a result, when the address indicated by the stage address data 303 is that of the stage 1061, the register setting data 305 on the data line 203 is written to the internal register corresponding to the address indicated by the register address 304.

[F2] Similarly, when the C / * D field 301 is "1", the process of writing the data of the input register 206 to the output register 211 is executed. At this time, the control circuit 212 controls the selector 2 through the control line 215.
10 outputs an output selection signal to the data line 209 side and outputs an output instruction signal to the output control circuit 221 through the control line 222. As a result, the data to be processed on the data line 209 is supplied to the input end of the output register 211 through the selector 210. Therefore,
The data to be processed in the input register 206 is directly supplied to the input end of the output register 211. on the other hand,
Whether the output control circuit 221 has already sent the current data in the output register 211 to the next stage in response to the output instruction signal of the control line 222 (that is, whether the output register 211 can be updated). To confirm. This confirmation can be easily made by setting a flag indicating that when the output to the next stage is completed. And output register 2
If 11 is updatable, a write signal is issued to the write control line 225. This allows the input register 206
Is directly written in the output register 211. Then, the output control circuit 221 outputs a READY signal to the input control circuit of the next stage through the control line 223. Then, on the control line 224 from the input control circuit of the next stage
When the WAIT signal goes down and it is known that the data in the output register 211 has been taken into the next stage, the data transmission completion confirmation flag is set. As a result, the data for setting the internal register is made to flow through the pipeline, and the setting to the internal register is made at the stage where the stage address 303 matches.

[F3] Next, when the C / * D field 301 is "0", the control circuit 212 confirms the mode information held therein, and confirms whether it is the processing execution mode or the passing mode. To do. The mode information required for this confirmation processing is, for example, the control circuit 212.
In (1), there is a mode storage register, and when the internal register is set prior to the processing, the processing execution mode is set in the mode storage register. Then, the control circuit 212 can confirm whether the processing processing execution mode or the passage mode is set by checking whether or not the processing processing execution mode is set in the mode storage register.

When the mode is the processing execution mode, the control circuit 212 issues a processing command to the data processing circuit 201 through the control line 226. As a result, in the data processing circuit 201, the data line 20
4 to be processed data 306 is fetched and processed according to the setting contents of the internal register. After that, the data processing circuit 201 outputs the resulting processed data to the data line 205 and notifies the control circuit 212 of the completion notification of the processing process through the control line 227. In response to the processing completion notification, the control circuit 212 outputs an output selection signal to the data line 205 side to the selector 210 on the control line 215, and also described above.
As in the case of [F2], an output instruction signal is output to the output control circuit 221 through the control line 222. The subsequent steps are the same as in [F2]. As a result, the processing result of the data processing circuit 201 is transferred to the next stage.

[F4] Similarly, when the C / * D field 301 is "0" and the mode is the pass mode, the control circuit 212 controls the output selection signal to the data line 209 side for the selector 210. In addition to being output on the line 215, the output instruction signal is output to the output control circuit 221 through the control line 222, as in the case of [F2] described above. Later
It is the same as in [F2]. As a result, the data to be processed in the input register 206 is directly transferred to the next stage.

The other stages 1062, 1063, ... Have the same structure.

The operation when the pipeline data processing is performed by the information processing system of the present embodiment configured as above will be described.

The CPU 101 first sets the C / * D field 3
The data in which 01 is set to "1" is sent. Then, as described above, the register setting data 305 is set in the internal registers in the corresponding stages 1061, 1062, ....

Upon completion of sending all the data for setting the internal register, the CPU 101 immediately sends the data with the C / * D field 301 set to "0". Then, the processing is performed on the stages 1061, 1062, ... As described above, and the final result is output from the last stage.

Therefore, the CPU 101 first sends the data with the C / * D field 301 set to "1", and then,
By sending the data with the C / * D field 302 set to “0”, the data in the data field 302 is automatically handled as data for register setting or processed data at each stage of the pipeline. Since the data irrelevant to is transferred to the subsequent stage as pass-through data, if the CPU accepts the data at the entrance of the pipeline, then the CP
Since the processing of U itself is completed, the CPU does not have to write the control data to the internal register.
The burden on U will be reduced.

Further, since the data from the CPU 101 to the pipeline will be flowed in the pipeline in the order in which it is sent out, immediately after the data input relating to the data processing of one aspect, another aspect is sent. Even if the data related to the other mode is input, the data related to the other mode is supplied to the stage after the data processing related to the previous mode is completed.

That is, since the input register 206 is updated in each stage after the internal processing in that stage is completed and the previous data is used up,
When the CPU 101 finishes sending the data related to the data processing of one aspect, it can immediately send out the data related to the data processing of another aspect, eliminating the processing waiting time as in the related art, and the entire information processing system. Throughput will be greatly improved.

Although the general pipeline has been described above, it can be applied to various types of information processing.

FIG. 4 shows a specific example thereof. The one shown in this figure shows a case of being adopted in an information processing system for enlarging / reducing character data in a high speed page printer.

In this figure, 401 is an MPU,
Character data is generated from this MPU 401. In the pipeline, each stage is configured by various single functional units such as character enlargement / reduction, rotation, and image data decompression. Here, the frontmost stage is configured by a scale converter 402, and the scale converter 402 simultaneously inputs I. It also functions as / F. Or later,
A stage including other functional units is serially connected.

Reference numeral 403 is a group of stages, each of which is composed of other functional units, and is schematically shown. Among them, a large number of serially connected stages are included. The page memory 404 is connected after the last stage, and the output data of the pipeline is stored in this memory 404.
The data is sent from the memory 404 to the printing mechanism unit via the mechanical I / F.

Reference numeral 405 is a transmission line for transmitting internal register setting data (including contents corresponding to the register address 304 and register setting data 305 in the above-mentioned embodiment) and processed data, and 406 is C / * D data. A transmission line 407 is a function data transmission line corresponding to the stage address in the above-described embodiment.

Now, let us consider enlarging and rotating certain character data with this system.

In this case, first, the MPU 401 places the C / * D data in the internal register setting mode on the transmission line 406, the function data as the address of the scale converter 402 on the transmission line 407, and the transmission line 405. The register setting data indicating the address and the parameter (enlargement ratio) of the internal register is transmitted. Then,
In the scale converter 402, the function data is first interpreted, and when it is known that it is its own address, the parameter is written in the designated internal register and the data processing circuit is set to the processing execution mode.

Next, the MPU 401 sends the C / * D data in the internal register setting mode on the transmission line 406, the function data as the address of the character rotation circuit on the transmission line 407, and the internal register on the transmission line 405. The register setting data indicating the address and the parameter (rotation angle) is sent out. Then, the scale converter 402 at the pipeline entrance first interprets the function data, and when it knows that it is not its own address, it transmits all the data on the transmission lines 405 to 407 to the subsequent stage 403 as it is. Thereafter, similar transmission processing is performed in each stage until the data reaches the rotary circuit stage. Then, when the data reaches the rotary circuit stage, the function data is interpreted to find that the address is its own, and the parameter is written to the specified internal register and the data processing circuit is processed. Set to mode.

Upon completion of the data transmission for setting the internal register of the predetermined function, the MPU 401 immediately
Start sending the processed data. In this case, MPU40
1 transmits C / * D data in the processing mode on the transmission line 406, and processed data on the transmission line 405. Then, in the pipeline, in the scale converter 402 in the operating state, the processing data is expanded, and this is sent to the rotating circuit stage in the operating state next, and the rotation processing of the character data expanded in this stage is performed. And then memory 4 from the last stage
It will be written in 04.

Therefore, as is clear, the MPU 401
Scale converter 402, which is the entrance to the pipeline
If the data is received at, the processing is completed, and the MPU 401 does not write the internal register at each stage, so that the burden is reduced.

Further, since the data from the MPU 401 to the pipeline will be flowed in the pipeline in the order of transmission, the MPU 401 ends the transmission of data relating to the data processing of one aspect. Then, it is possible to immediately send out the data relating to the data processing of another aspect.

It should be noted that the present invention is not limited to such processing of print data, but character generation of display data in a display control device, character data enlargement / reduction, character data rotation, image data extension, image data enlargement / reduction, image data. The present invention can also be applied to processing such as rotation, image data enlargement / reduction in the scanner control device, rotation, compression, and the like.

[0075]

As described above, according to the present invention, the data of the data portion to be processed is treated as control data or processed data according to the identification field of the input data and the mode information, and data unrelated to itself is treated. path·
Since the data is transferred to the subsequent stage as through data, if the CPU adds the above identification data to the data to be processed and flows it into the pipeline, the subsequent processing is automatically performed by the corresponding stage. Therefore, if the CPU receives the data at the entrance of the pipeline, the processing is completed, and the load of the CPU is reduced because the control data is not set by the CPU.

It should also be noted that since the data from the CPU to the pipeline will be flowed in the pipeline in the order in which it was sent out, the data input relating to the data processing of one aspect is input. Even if data regarding another aspect is input immediately after, the data regarding that aspect is supplied to the stage after the data processing regarding the previous aspect is completed. As soon as the sending of the data related to the processing is completed, the data related to the data processing of another aspect can be sent, and the processing waiting time as described above is eliminated,
Throughput as a whole of the information processing system is greatly improved.

[Brief description of drawings]

FIG. 1 is a system block diagram of a general information processing pipeline according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the internal configuration of each stage shown in FIG.

FIG. 3 is an explanatory diagram of the structure of data generated by the CPU shown in FIG.

FIG. 4 is a system block diagram of an information processing pipeline for a print data processing system of a high speed page printer according to another embodiment of the present invention.

FIG. 5 is a system block diagram of a conventional general information processing pipeline.

6 is a block diagram illustrating the internal configuration of each stage shown in each stage shown in FIG.

FIG. 7 is a system block diagram of a print data processing system of a conventional high speed page printer.

[Explanation of symbols]

101 CPU 102 Address bus 103 Data bus 104 Control bus 105 Input I / F 1061, 1062, ... Pipeline stage 201 Data processing circuit 2021, ..., 202m Internal register 203 Data line of register setting data 204 Data line of processed data 205 Data line of processed data 206 Input register 207 C / * D field data line 208 Stage register Address data line 209 Data line of passing data 210 Output selector 211 Output register 212 Control circuit 2131, ..., 213m, 220, 225 Write signal Control line 214 Write command control line 215 Selection signal control line 216 Input control circuit 217, 223 READY control line 218, 224 WAIT control line 219, 222 I / O control control line 221 Output Control circuit 226, 227 Data processing circuit control line 301 C / * D field (identification field) 302 Processed data field 303 Stage address 304 Register address 305 Register setting data 306 Processed data 401 MPU 402 Scale converter 403 Other functional parts 404 page memory 405 Transmission line for transmitting internal register setting data and processed data 406 C / * D data transmission line 407 Function data transmission line

Claims (1)

[Claims] 1. An information processing device constituting each stage of an information processing pipeline, wherein processed data is processed in a manner determined by control data stored in an internal register, and the processed data is the processed result. According to the data processing means for outputting data, the processed data transferring means for transferring the processed data to the next stage, the passing data transferring means for transferring the passing data to the next stage, the identification field of the input data and the mode information. ,
A process of writing the processing target data part of the input data in the internal register, a process of giving the input data as the processed data to the data processing means, and a process of sending the input data to the data transfer means are executed. An information processing apparatus including a control unit.