JPH0520245A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To provide a data transfer equipment capable of asynchronously and rapidly transferring data. CONSTITUTION:In addition to the configuration of the data transfer equipment having a data processing part 4, a memory part 8 having many memory units 18 and an address forming part 6 for forming the address of a memory unit 18 to be accessed based upon the data of the data processing part 4, the data transfer equipment is also provided with a transfer word specifying part 12 having a transfer word specifying bit 22 for recording the memory unit 18 to be accessed, a transfer end specifying part 10 having a transfer end specifying bit 20 for recording the memory unit 18 whose access has been completed and a priority encoder part 14 for asynchronously specifying the memory unit 18 to be accessed based upon the information of both bits 22, 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in a computer system.

[0002]

2. Description of the Related Art In recent years, a data transfer device in a computer system is required to have a higher speed. Figure 3
An example of an initial data transfer device is shown in FIG. This data transfer device includes a data processing unit 4 that processes data, an address generation unit 6 that generates an address based on the data from the data processing unit, and transfer data that is generated based on the address generated by the address generation unit 6. A memory unit 8 to be accessed,
And a data line 30 to which transfer data is transferred.
In this data transfer device, a series of transfer data is accessed as follows. First, the data processing unit 6 sets an initial value of an address to be accessed in the address generation unit 6. The address generation unit 6 outputs the set address to the memory unit 8 and further updates the address and the memory unit 8
And output to. In this way, the access of the transfer data to the memory unit 8 is sequentially performed. FIG. 4 shows the timing of address generation and transfer data access in this data transfer device. As shown in FIG. 4, in this data transfer device, since address generation and memory access are performed alternately, it is impossible to transfer data at high speed.

There is known a data transfer apparatus in which address generation and memory access are pipelined in order to speed up data transfer. FIG. 5 shows an example of a conventional pipelined data transfer device. In addition to the configuration of the data transfer device shown in FIG. 3, this data transfer device is provided with a register 10 for temporarily storing the address of the memory section 8 to be accessed. In this data transfer device, access to a series of transfer data is performed as follows. First, the data processing unit 4 sets the initial address of the memory unit 8 to be accessed in the address generation unit 6. The address generator 6 outputs the address to be accessed to the register 10, and further updates the address and outputs the address to the register 10. The register 10 outputs the set address to the memory unit 8, and the memory unit 8 accesses the transfer data to the address specified by the register 10.

As described above, since the data transfer device is provided with the register 10 for temporarily holding the address of the memory section 8 to be accessed, the pipeline processing of the address generation and the memory access can be performed. It will be possible. That is, as shown in FIG. 6, the memory access and the generation of the address of the memory unit 8 to be accessed next can be executed in an overlapping manner.

[0005]

However, in the above configuration, in order to perform the above pipeline processing, memory access and address generation must be performed in synchronization. That is, the time for address generation in the address generator 6 and the time for data access in the memory unit 8 must be balanced. Therefore, for example, when a DRAM or the like is used for the memory unit 8, there is a problem that the cycle time becomes long because the memory access time differs between the page mode and the non-page mode.

In view of the above problems, it is an object of the present invention to provide a data transfer device capable of asynchronously and rapidly transferring data without increasing the cycle time.

[0007]

In order to solve the above problems, the present invention provides a transfer word designation bit and a transfer end corresponding to each of a plurality of memory units storing transfer data in word units in a memory section. An instruction bit is provided, the transfer word designation bit records that the corresponding memory unit should be accessed, and the transfer end instruction bit records that the access of the corresponding memory unit has been completed. The memory unit is asynchronously accessed based on the information of the bit and the transfer end instruction bit.

Specifically, the solving means taken by the present invention is based on the data processing section, the memory section having a large number of memory units for storing the transfer data in word units, and the address information from the data processing section. An address generation unit that generates an address that specifies the memory unit to be accessed in the memory unit, and the corresponding memory unit that is provided corresponding to each of the memory units of the memory unit are specified by the address generation unit. A transfer word designating section having a transfer word designating bit recorded therein, and a transfer in which it is recorded that access of the corresponding memory unit provided corresponding to each of the memory units of the memory section is completed. The transfer end instruction section having an end instruction bit and the transfer word designation bit corresponding to A priority encoder section for sequentially designating the memory units in which the designation by the address generation section is recorded and the transfer end instruction bit corresponding to the memory unit is recorded. A configuration is provided that includes a first reset line that clears all of the transfer word designating bits of the word designating unit and a second reset line that clears all of the transfer end designating bits of the transfer termination designating unit. It is a thing.

[0009]

According to the structure of the present invention, the initial address of the memory unit to be accessed in the memory unit is set in the address generation unit by the data processing unit, and the address generation unit specifies the transfer word of the transfer word designation unit corresponding to the address. Record in the bit that the memory unit was specified. Further, the address generation unit generates the address of the memory unit to be accessed in the memory unit and records the transfer word designating bit corresponding to this, depending on whether or not the access to the previously designated memory unit is completed. Execute regardless. On the other hand, the priority encoder section examines the data stored in the transfer word designating bit and the transfer end designating bit, records that the transfer word designating bit should be accessed, and terminates the access to the transfer end designating bit. Detect memory units that are not recorded Next, the priority encoder section sequentially designates the memory units thus detected. As a result, the detected memory unit is asynchronously accessed. At the same time, the transfer end instruction bit corresponding to the memory unit accessed by the transfer end instruction unit records that the access is completed so that the memory unit is not accessed again. As described above, the transfer of the transfer data by the series of accesses is completed. Before the transfer of the next transfer data, all the transfer word designating bits of the transfer word designating section and all the transfer end designating sections of the transfer end designating section are respectively controlled by the first reset line and the second reset line. Bits and are cleared.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer apparatus according to an embodiment of the present invention will be described below. FIG. 1 shows a schematic configuration of a data transfer device according to an embodiment of the present invention. The data transfer apparatus according to the present embodiment includes a data processing unit 4 that processes data, an address generation unit 6 that generates an address based on the data from the data processing unit, and a memory unit 8 that is a DRAM that holds data. It has a data line 30 to which transfer data is transferred, and further has a transfer end instructing section 10 composed of a dual port memory, a transfer word instructing section 12, and a priority encoder section 14.

The memory section 8 has a large number of memory units 18 for storing transfer data in word units. Also,
The transfer word designating section 12 has transfer word designating bits 22, 2 corresponding to the memory units 18, 18 ...
2, and "1" is recorded in each transfer word designation bit 22 when the corresponding memory unit 18 is to be accessed. Similarly, the transfer end instruction section 10 has transfer end instruction bits 20, 20 ... Corresponding to the respective memory units 18, 18 ... Of the memory section 8, and each transfer end instruction bit 20.
When the access to the corresponding memory unit 18 is completed, "1" is recorded in the.

The priority encoder unit 14 includes transfer word designation bits 22, 22, ... Of the transfer word designating unit 12.
The data stored in the first word lines 32, 32 ...
While checking the data stored in the transfer end instruction bits 20, 20 ...
Of the memory unit 18 in which "1" is recorded in the corresponding transfer word designation bit 22 and "0" is recorded in the corresponding transfer end instruction bit 20. It has the function of detecting. The priority encoder unit 14 also has a function of sequentially specifying the detected memory units 18 via the second word line 34 and the third word line 36. The designation of the memory unit 18 by the priority encoder unit 14 is performed asynchronously. The contents of the transfer word designating bits 22, 22, ... Of the transfer word designating section 12 are cleared by the data processing section 4 via the reset line 16. Similarly, the transfer end instruction bit 20 of the transfer end instruction unit 10,
The contents of 20 ... Are cleared by the data processing unit 4 via the reset line 17.

The operation of the data transfer apparatus of this embodiment having the above configuration will be described. First, the data processing unit 4 sets the initial address of the memory unit 18 to be accessed in the memory unit 8 in the address generation unit 6, and the reset line 16
The contents of all transfer word designating bits 22, 22 ... Of the transfer word designating part 12 and all transfer end designating bits 20, 20 ... Next, the address generator 6 sequentially generates addresses of the memory unit 18 of the memory unit 8 to be accessed,
It is output to the transfer word designation unit 12. Transfer word designator 1
2 sets the transfer word designating bit 22 corresponding to the memory unit to be accessed to "1" based on the output from the address generator 6.

The priority encoder section 14 has a first
The data stored in the transfer word designating bits 22, 22, ... Of the transfer word designating unit 12 is checked via the word line 32 of the above, and the transfer end designating bit of the transfer end designating unit 10 is carried out via the fourth word line 38. Check the data stored in 20, 20, ..., Corresponding transfer word designation bit 2
2 is "1" and the corresponding transfer end instruction bit 2
All memory units 18 in which 0 is "0" are detected. The memory unit 18 detected in this way is
Are sequentially designated by the priority encoder unit 14 via the second word line 34 and the third word line 36,
The transfer data is accessed. At the same time, "1" is set to the transfer end instruction bit 20 corresponding to the memory unit 18 for which the access of the transfer data has been completed so that it is not accessed again. The access to the memory unit 18 and the setting of "1" to the transfer end instruction bit 20 are performed asynchronously because the transfer end instruction unit 10 is a dual port.

FIG. 2 shows the operation timing in the data transfer apparatus of this embodiment. In FIG. 2, the period between the two vertical lines corresponds to three periods of the system clock. In this embodiment, the time required for the address generation in the address generation unit requires a clock, and the time required for accessing the memory unit 18 in the memory unit 8 is 2 clocks in the page mode and 6 times in the non-page mode. Suppose it was a clock. In the page mode, as shown in FIG. 2 during normal operation, it takes 3 clocks to generate an address, so memory access is also performed every 3 clocks. But DR
Immediately after the page switching of the memory unit 8 configured by AM, as shown in the operation at the time of page switching in FIG. 2, memory access requires 6 clocks. At the time when the memory is generated and the next memory access is started, 3 words are untransferred. However, after that, memory access is performed every 2 clocks, and after 9 clocks, memory access is performed asynchronously, and the overhead due to page switching is absorbed.

As described above, according to the data transfer apparatus of the present embodiment, the transfer word designation bit 22 is set to access the corresponding memory unit 18, and the transfer end instruction bit 20 is set to the corresponding memory unit. It is set that the access of 18 has been completed, and it becomes possible to access the memory unit asynchronously based on the information of the transfer word designation bit 22 and the transfer end instruction bit 20, and the overhead in the page mode is absorbed. can do. Therefore, high-speed data transfer can be performed.

[0017]

As described above, the data transfer apparatus of the present invention has a transfer word designating section having a transfer word designating bit designating a memory unit to be accessed, and a transfer end designating a memory unit which has been accessed. Since the transfer end instruction section having the instruction bit and the priority encoder section for sequentially designating the memory unit by the information of the transfer word designating bit and the transfer end instruction bit are provided, the memory unit can be asynchronously accessed, and the page It is possible to prevent the cycle time from increasing due to the memory access time being different between the mode and the non-page mode, and to perform high-speed data transfer.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation timings in the embodiment of FIG.

FIG. 3 is a schematic configuration diagram of a conventional data transfer device.

FIG. 4 is a diagram showing operation timings in a conventional data transfer device.

FIG. 5 is a schematic configuration diagram of another conventional data transfer device.

FIG. 6 is a diagram showing an operation timing in the data transfer device of FIG.

[Explanation of symbols]

 4 data processing unit 6 address generating unit 8 memory unit 10 transfer end instructing unit 12 transfer word designating unit 14 priority encoder unit 16 first reset line 17 second reset line 18 memory unit 32 first word line 34 second Word line 36 Third word line 38 Fourth word line 30 Data line

Claims (1)

Claim: What is claimed is: 1. A data processing unit, a memory unit having a large number of memory units for storing transfer data in word units, and access to the memory unit based on address information from the data processing unit. An address generation unit that generates an address that specifies the memory unit to be recorded, and that the corresponding memory unit that is provided corresponding to each of the memory units of the memory unit is specified by the address generation unit is recorded. A transfer word designating section having a transfer word designating bit, and a transfer end designating bit provided corresponding to each of the memory units of the memory section and recording that the corresponding memory unit has been accessed. And a transfer end instruction section having the address generation in the corresponding transfer word designation bit. A priority encoder section for sequentially designating the memory units in which the designation by a unit is recorded and the corresponding transfer termination instruction bit is recorded as having completed the transfer of the transfer data; and the transfer word designating section, A data transfer device comprising: a first reset line that clears all transfer word designation bits; and a second reset line that clears all of the transfer end instruction bits of the transfer end instruction unit. ..