JPH04338846A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To attain the accesses to plural types of memories having different access speeds with the machine cycle of an arithmetic processor kept fixed. CONSTITUTION:When an MPU part 1 has an access to a memory 2, a wait signal is outputted to the part 1 and therefore the part 1. is kept in a wait state for a prescribed time by a WAIT control circuit 8. Then the generating time of the wait signal is pointed by the pointing signals 9 and 10. Thus the accesses are possible to the memories of different types which have the different access times.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device for reading/writing (accessing) information from a connected memory.

0002

[Prior Art] Figure 8 shows a typical circuit configuration of an arithmetic processing device.
Shown below.

In FIG. 8, a main processor unit section (hereinafter sometimes abbreviated as MPU section) that performs arithmetic processing
1 and a memory (RAM) 2 for storing information are connected by a bus.

[0004] The MPU unit 1 operates using a clock (CLK) 3 as a basic clock.

One of the plurality of memories 2 is selected by the chip select signal CS of the MPU section 1, and the write signal WR is selected.
, read/write to the memory 2 is instructed by the read signal RD.

FIG. 9 shows the address space allocated to the MPU section 1, and the RAM space corresponding to the memory (RAM) 2 is allocated to the space where A0="1", which is the most significant bit of the address bus 5. It is assumed that there is

FIGS. 10 and 11 are timing charts showing the timing at which the MPU unit 1 accesses the memory (RAM) 2. One cycle such as a read (READ) cycle or a write (WRITE) cycle, that is, an arithmetic processing cycle (also referred to as a machine cycle) consists of four cycles of clock (CLK) 3 (t1, t2, t3, t4).
).

In the timing chart shown in FIG. 10, since one cycle of clock (CLK) 3 is long, CPI (Cycle Per
Instruction) 6 is also longer, so
Memory (RAM) 2 with slow access time can be accessed.

In the timing chart shown in FIG.
Compared to the timing chart of 0, clock (CLK) 3
Since one cycle of is short, the CPI 6 is also short, and the processing speed can be increased, but the memory (RAM) 2, which has a slow access time, cannot be accessed.

[0010] Conventionally, therefore, in order to selectively use memories with different access times, a clock (CLK) is used.
An arithmetic processing device has been proposed in which a plurality of oscillators with different generation cycles are prepared, and the oscillators corresponding to the access time of the connected memory are switched and used according to instructions from an operator.

[0011]

However, the above proposal has the disadvantage that the number of oscillators increases and the shape of the arithmetic processing device itself becomes larger.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide an arithmetic processing system that allows an arithmetic processing unit to operate with one type of operating clock while reading/writing to and from memories having different access times. The goal is to provide equipment.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an arithmetic processing device that can access a connected memory, the arithmetic processing cycle time of the arithmetic processing device being reduced. In the arithmetic processing device whose access time is shorter than the access time of the memory, the arithmetic processing device includes access detection means for detecting the access of the arithmetic processing device to the memory, and the arithmetic processing device that corresponds to the access time of the memory in response to the detection. Based on an external instruction signal that instructs a wait time, the arithmetic processing unit is set in a wait state for the wait time indicated by the instruction signal for each arithmetic processing cycle, thereby adjusting the access time of the memory and the calculation of the arithmetic processing unit. The present invention is characterized by comprising a weight control means for synchronizing processing timing.

[0014]

[Operation] In the present invention, when the access of the arithmetic processing unit to the memory is detected, the arithmetic processing is performed for the specified time in each arithmetic processing cycle in order to synchronize the arithmetic processing timing with the access time of the memory which is longer than the arithmetic processing cycle. Set the device to wait state. Therefore, the arithmetic processing device can access memories with different access times. Furthermore, even when using memories with different access times, such as memory cards, by instructing the wait time to the wait control means using an instruction signal,
A memory card can be used instead.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the circuit configuration of an embodiment of the present invention. Note that the same parts as in the conventional example in FIG. 8 are given the same reference numerals, and detailed explanations will be omitted.

In the circuit shown in FIG. 1, the MPU section 1 and the memory (R
In addition to AM) 2, an access time setting switch 11 and a wait (WAIT) control circuit 8 are provided. The memory (RAM) 2 and the access time setting switch 11 are
It is integrated as a memory card 7 and is detachable from the MPU unit 1 side.

In this embodiment, the clock (CLK) signal 4
The MPU section 1 can access a plurality of memories having four types of access times, from double period to seven times the period, and the MPU section 1 itself normally operates with four times the clock period as a machine cycle.

The wait control circuit 8 generates a wait signal for a predetermined period of time to the MPU unit 1 at a constant cycle, and
By setting the memory 2 to wait (standby state), the access processing of the connected memory 2 and the arithmetic processing timing of the MPU unit 1 are synchronized.

The generation time of the wait signal generated by the wait control circuit 8 is determined by the 2-bit instruction signals SET0 (symbol 9) and SET1 generated by the access time setting switch 11.
(10).

In this embodiment, as shown in FIG. 2, the wait signal generation time can be variably set by three types of time corresponding to 0 to 3 operation clock pulses of the MPU unit 1.

An example of the circuit configuration of the weight control circuit 8 in FIG. 1 is shown in FIG.

In this circuit, there is an access request to the memory 2 (address signal A0="1"), and the MPU
When the CPI signal of section 1 is at level “1” and the conditions for wait signal generation (wait number “0”, WSET0 signal = “0”) are met, the output level of the AND gate is set to 17.
That is, the J input of the JK flip-flop 19 becomes level "1", and at this point the wait signal becomes level "1".
becomes.

This AND gate operates as the access detection means of the present invention.

[0025] Furthermore, the instruction signal may be any one of the first time point when the CPI signal becomes "0", the second time point 1 CLK after the time the CPI signal becomes "0", and the third time point 2 CLK after the time the CPI signal becomes "0". It is selected by SET0 and SET1, and at the time of selection, the K input of the J, K flip-flop 19 becomes level "1", and the weight signal at level "1" is reset.

[0026] Through this reset processing, the pulse width of the wait signal is variably set.

In such a circuit, when the wait (WAIT) signal generated by the wait control circuit 8 is input, the MPU unit 1 outputs the signal between the t3 portion and the t4 portion of the normal clock (CLK) 3 as shown in FIG. Then, a wait clock W is generated according to the length of the wait signal to maintain the wait state. Note that the timing chart in FIG.
SET0 signal = by access time setting switch 11
This shows the timing of signal generation in the wait control circuit 8 when the SET1 signal is set to "0" and the SET1 signal is set to "1" and two wait clocks are generated.

FIG. 5 shows the signal generation timing within the MPU unit 1 at this time.

Further, FIG. 6 shows the signal generation timing in the wait control circuit 8 when the SET0 signal is set to "1" and the SET signal is set to "1" by the access time setting switch 11 to prevent the wait clock from being generated. It is shown below.

Another example of the circuit configuration of this embodiment is shown in FIG.

The circuit of FIG. 7 has a read register 13 and a write register 14 added to the circuit of FIG.

The read register 13 holds the 2-bit instruction signal generated by the access time setting switch 11 using the instruction signal *RDS of the MPU section 1, and outputs it to the data bus 12.

[0033] The MPU unit 1 *R according to the program instructions.
DS is generated and the instruction signal of the read register 14 is read from the data bus. After this, the MPU unit 1 generates the *WRS signal according to the program instruction, and the data bus 12
The above-mentioned read instruction signal is sent to the write register 14 via
write to. The write register 14 holds and outputs the written instruction signal to the wait control circuit 8.

The holding signal of the write register 14 is reset by the *RST signal generated by the MPU unit 1 based on a program instruction.

In this manner, by transferring the instruction signal of the access time setting switch 11 to the wait control circuit 8 via the data bus 12 via the MPU unit 1, a dedicated signal for connecting the access time setting switch 11 and the wait control circuit No signal line is required.

As explained above, in this embodiment, 1
By inserting a specified number of wait clocks between the third and fourth operation clocks in the machine cycle, the MPU section 1 is set in a wait state. Therefore, the MPU unit 1 waits from the time the MPU unit 1 generates an address signal and read/write related control signals to the memory 2, which has a slow access speed, until the memory 2 side determines the read/write information. Since the state continues, arithmetic processing can be executed in synchronization with the memory 2, which takes a long access time.

The following other examples of this embodiment are given.

1) In this embodiment, an example is given in which memories (cards) 2 with different access times are connected to the MPU unit 1 in an exchange manner, but if there is additional fixed memory on the MPU unit 1 side, the fixed memory It is also possible to automatically switch the access timing of the MPU section 1 in accordance with the access time of the memory card.

In this case, the memory to be accessed is determined by a decoder that decodes the address signal, and if the memory card is to be accessed, the instruction signal of the access setting switch 11 on the memory card side is sent to the wait control circuit 8. Transfer to. Furthermore, if the memory to be accessed is an internal fixed memory, an instruction signal corresponding to this memory is transferred from the decoder to the wait control circuit 8. It is preferable to use a gate circuit for switching the transfer of this instruction signal.

2) In this embodiment, a circuit using a JK flip-flop has been described as an example of the wait control circuit 8, but a pulse width changing circuit that variably sets the pulse width of a pulse signal used as a wait signal according to an instruction signal is also applicable. It goes without saying that other well-known pulse width modification circuits can be used.

[0041]

As explained above, according to the present invention, an arithmetic processing unit can access various memories with different access times in a fixed machine cycle.
There is no need to prepare multiple types of oscillators as in the past, and this can contribute to miniaturization of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the correspondence between weight lengths and their instruction signals according to the embodiment of the present invention.

3 is a circuit diagram showing the circuit configuration of the weight control circuit 8 of FIG. 1. FIG.

FIG. 4 is a timing chart showing signal generation timing in the embodiment of the present invention.

FIG. 5 is a timing chart showing signal generation timing in the embodiment of the present invention.

FIG. 6 is a timing chart showing signal generation timing in the embodiment of the present invention.

FIG. 7 is a block diagram showing another circuit configuration of the present invention.

FIG. 8 is a block diagram showing a circuit configuration of a conventional example.

9 is an address map showing the address space of the MPU unit 1 in FIG. 8. FIG.

FIG. 10 is a timing chart showing conventional signal generation timing and generation time.

FIG. 11 is a timing chart showing conventional signal generation timing and generation time.

[Explanation of symbols]

1 MPU section 2 Memory (RAM) 3 Clock (CLK) signal 4 RAM space 5 Address bus 7 Memory card 8 Wait (WAIT) control circuit 9 SET0 signal line 10 SET1 signal line 11 Access time setting switch 12 Data bus 13 Read register 14 Write register 15 Wait (WAIT) signal line

Claims (1)

[Claims] 1. An arithmetic processing device that is capable of accessing a connected memory, the arithmetic processing cycle time of the arithmetic processing device being shorter than the access time of the memory; for each arithmetic processing cycle based on an access detection means for detecting an access of the processing device, and an external instruction signal that instructs a wait time of the arithmetic processing device corresponding to the access time of the memory according to the detection; An operation comprising: wait control means for synchronizing the access time of the memory and the arithmetic processing timing of the arithmetic processing device by setting the arithmetic processing device in a wait state for a wait time indicated by the instruction signal. Processing equipment.