JP2689452B2 - Storage device - Google Patents

Description

The present invention relates to a storage device, and more particularly to a storage device of an information processing device.

[Conventional technology]

Conventional storage devices include a storage device that can perform block transfer and a storage device that can perform interleave transfer.

FIG. 4 is a block diagram showing an example of a conventional storage device capable of block transfer.

In FIG. 4, the activation circuit 41 receives a command instructing read or write and an access request signal R41 designating an address and a data length for the command,
The activation request signal for activating the access operation of the designated bank is output.

In addition, the address generation circuit 42 receives the activation request signal from the activation circuit 41, and sequentially from the designated address to the last address of the designated data length, in units of data access or word by word. To generate respective address selecting signals, and distribute and output the address selecting signals A40, A41, A42, A43 for each of the four data access unit rows.

FIG. 5 is a timing chart showing the operation of a conventional storage device capable of block transfer.

In FIG. 5, in synchronization with the clock, the address selection signals A40, A41, A42, A43 of the address generation circuit 42 specify the position of the word address i for each data access unit row, and then the storage element. It is sent to matrix 43.

On the other hand, since the storage element matrix 43 has N words in each of the four data access unit rows, the address selection signals A40, A41, A42, A43 of the address generation circuit 42 and the write data W41 at the time of writing. In response to this, the designated words are sequentially selected, and the read or write access operation instructed by the command is executed on the selected words to perform the block transfer of the instructed data length. it can.

At the time of reading, the read selection circuit 44 has a storage element matrix.
Read data D40, D41, D42, D4 read from each of the four data access unit rows sequentially from 43 in word units
3 is the address selection signal A40, A41, A of the address generation circuit 42
42 and A43 are selected and received, and they are combined and output as total read data D44.

Word address i of each data access unit row in FIG.
The data b _i , b _{i + 1} , b _{i + 2} , b _{i + 3} at the position of are read as read data D40, D41, D42, D43, respectively, as shown in FIG. The output data of the read data D44 is the data b _i b _{i + 1} b _{i + 2} b _{i + 3} .

However, since the conventional memory device shown in FIG. 4 can select only one word address at a time from one activation circuit and one address generation circuit, a plurality of data access units can be selected in parallel. High-speed interleaved transfer that requires address selection cannot be performed.

FIG. 6 is a timing chart showing the operation of interleave transfer in the conventional memory device of FIG. In the conventional memory device shown in FIG. 4, in interleaved transfer, as shown in FIG. 6, the next word is selected from respective addresses A40, A41, A42, A43, ... The operation by the next address A41, A42, A43, ... Is started after waiting for each operation time t until the operation of the storage element matrix 43 by the address A40, A41, A42 ,. For this reason,
The read data b _i , b _j , b _k , b _l , ... Are read at intervals of the operation time t, and high-speed interleave transfer cannot be executed.

An example of a conventional storage device capable of interleave transfer is shown in FIG. 4 for each data access unit row.
This is a storage device in which separate starting circuits and address generating circuits are provided so that four data access unit rows can be independently and concurrently selected for address.

This memory device can perform interleave transfer for up to four words by selecting addresses for words in up to four data access unit rows in parallel at predetermined short time intervals.

However, in this case, the sending side of the request has to perform the process of outputting the address and the command for each address selection, and if the address and the command are output by the bus, the traffic of the bus increases. At the same time, since the next word having consecutive addresses is selected from different address generation circuits, consecutive addresses cannot be selected in order from one address generation circuit. A block transfer that requires selection cannot be executed.

[Problems to be solved by the invention]

The conventional storage device capable of block transfer as described above can select an address of one data access unit at a time when accessing a lot of data having non-consecutive addresses. If is not completed, the next access operation cannot be started, and the processing speed is significantly reduced.

On the other hand, the conventional storage device that can perform the interleave transfer described above generates individual addresses one by one like data having non-contiguous addresses even when accessing data having contiguous addresses. Therefore, there is a problem that the processing speed is lowered when accessing data having many consecutive addresses.

An object of the present invention is to provide a storage device that can perform block transfer and interleave transfer.

[Means for Solving the Problems] The storage device of the present invention receives (A) a command for instructing read or write and an access request signal for specifying a bank, an address and a data length for the command, and specifies the command. The activation request signal that activates the access operation of the specified bank, and
When the specified address and data length extends to the next bank, the command for reading or writing for the next bank at a predetermined time interval, and the next bank for the command, the following address and the remaining data A start circuit provided in each bank for transmitting an access request signal specifying a length and capable of operating in parallel, (B) In response to a start request signal from the start circuit, sequentially from a specified address in a specified bank , An address generation circuit for each bank that generates an address selection signal for each data access unit, up to the address of the boundary of the bank or the last address of the specified data length, (C) for each L banks Each of the M data access unit rows has N data access units and the address By receiving the address selection signal of the raw circuit and the write data at the time of writing, sequentially selecting the data access unit, and executing the read or write access operation designated by the command in the selected data access unit. , A storage element matrix for performing block transfer or interleave transfer according to a given command, (D) Each of the data access unit rows having M banks for each L bank sequentially from the storage element matrix And a read selection circuit which receives the read data read by the address selection signal of the address generation circuit, and outputs the combined read data as integrated read data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device of the present invention.

In FIG. 1, start circuits 1-0 and 1-1 provided in bank 0 and bank 1 and capable of operating in parallel specify a command instructing read or write and a bank, an address and a data length for the command. In response to the access request signal R1, the activation request signals S0 and S1 for activating the access operation of the designated bank 0 or bank 1 are output, and the designated address and data length are transferred to the next bank 1 or bank 0. When extending over, the access request signal R2 specifying a command for instructing read or write for the next bank 1 or bank 0 at a predetermined time interval, the next bank for the command, the subsequent address and the remaining data length. , R3 is sent.

Further, the address generation circuit 2-for each of bank 0 and bank 1
0,2-1 is the activation request signal S from the activation circuit 1-0,1-1
Receiving 0, S1, sequentially from the specified address in the specified bank to the address of the boundary of the bank or the last address of the specified data length for each word that is the data access unit Signals for selecting respective addresses are generated, and these are distributed and output as address selection signals A0, A1, A2, A3 for each of the four data access unit rows.

FIG. 2 is a timing chart showing the operation of block transfer in the memory device of this embodiment. FIG. 3 is a timing chart showing the operation of interleave transfer in the memory device of this embodiment.

2 and 3, in synchronization with the clock,
The address selection signals A0 and A1 of the address generation circuit 2-0 are
The position of the word address i is designated for each data access unit row, and then the data is transmitted to the storage element matrix 3.

Subsequently, in FIG. 2, the address selection signals A2 and A3 of the address generation circuit 2-1 specify the position of the word address i for each data access unit row, and are subsequently sent to the storage element matrix 3. Although FIG. 3 shows the case, the address selection signals A2 and A3 of the address generation circuit 2-1 are shown in FIG.
Shows the case where the position of the word address j is designated for each data access unit row and subsequently sent to the storage element matrix 3.

On the other hand, the storage element matrix 3 has L = 2 and M = 2, and each of the two banks has N data access units in two data access unit rows.
Address selection signals A0, A of address generation circuits 2-0,2-1
1, A2, A3 and the write data W1 when writing, select the words in sequence, and execute the read or write access operation designated by the command to the selected word Block transfer or interleaved transfer according to

At the time of reading, the read selection circuit 4 reads the read data D0, D1, D2, read data from the storage element matrix 3 sequentially for each word in each of the two data access unit rows each having two banks. D3 is selected by the address selection signals A0, A1, A2, A3 of the address generation circuits 2-0, 2-1 and received, and these are combined and output as total read data D4.

In FIG. 2, data straddling the bank located at the word address i of each data access unit row in FIG.
b _i , b _{i + 1} , b _{i + 2} , b _{i + 3} are read data D0, D1, D2,
The output of the total read data D4 read out to D3 and combining them is continuous high-speed read data b _i b _{i + 1} b _{i + 2} b _{i + 3}
Becomes

On the other hand, in FIG. 3, the data at the position of word address i of each data access unit row in bank 0 of FIG.
b _i and b _{i + 1} are read as read data D0 and D1, respectively, and data b _j and b _{j + 1 at} the position of word address j of each data access unit row in bank 1 are read data D2. , D3, and the combined read data D4 output from them is output as continuous high-speed read data b _i b _{i + 1} b _j
It becomes b _{j + 1} .

As described above, the storage device of the present embodiment can perform block transfer at high speed or interleave transfer at high speed depending on the contents of the access request signal.

〔The invention's effect〕

As described above, since the storage device of the present invention can perform block transfer and interleave transfer,
There is an effect that both data having continuous addresses and data having non-continuous addresses can operate at a high processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device of the present invention, FIG. 2 is a timing diagram showing a block transfer operation in the storage device of the present embodiment, and FIG. 3 is an interleave in the storage device of the present embodiment. FIG. 4 is a timing diagram showing a transfer operation, FIG. 4 is a block diagram showing an example of a conventional storage device capable of block transfer, FIG. 5 is a timing diagram showing an operation of a conventional storage device capable of block transfer, and FIG. Fourth
FIG. 10 is a timing diagram showing an operation of interleave transfer in the conventional storage device shown in FIG. 1-0,1-1 ... Start-up circuit, 2-0,2-1 ... Address generation circuit, 3 ... Storage element matrix, 4 ... Read selection circuit,
41 …… Starting circuit, 42 …… Address generating circuit, 43 …… Storage element matrix, 44 …… Read selection circuit, A0, A1, A2, A3, A40, A4
1, A42, A43 …… Address selection signal, D0, D1, D2, D3, D40, D4
1, D42, D43 …… Read data, D4, D44 …… Comprehensive read data, R1, R2, R3, R41 …… Access request signal, S0, S1 ……
Start request signal, W1, W41 ... Write data.

Claims (1)

(57) [Claims] 1. A start request signal for receiving a command for instructing read or write and an access request signal for designating a bank, an address and a data length for the command, and for activating an access operation of the designated bank. When the specified address and data length extend to the next bank, the command for reading or writing for the next bank at the predetermined time interval and the next bank for the command, An activation circuit provided in each bank for transmitting an access request signal designating an address and the remaining data length and capable of operating in parallel; (B) Receiving a activation request signal from the activation circuit, designated in the designated bank. From the specified address to the address of the bank boundary or the last address of the specified data length. An address generation circuit for each bank that generates an address selection signal for each data access unit, (C) a data access unit row having M number for each L banks, and N data access units for each row, and Receiving the address selection signal of the address generation circuit and write data at the time of writing, sequentially selecting the data access unit, and executing the read or write access operation designated by the command in the selected data access unit. A storage element matrix for performing block transfer or interleave transfer according to a given command, (D) From the storage element matrix, in order for each data access unit, for each L banks, M data access unit rows are provided. The read data read from each is sent to the address Receiving is selected by the address selection signal of the circuit, the read select circuit for outputting them as a comprehensive reading data according, storage device, characterized in that it comprises a.