JPH04242452A - Storage device and its control circuit - Google Patents

Abstract

PURPOSE:To improve the block transfer ability by providing a means which interleaves the requests given from a system controller and a means which performs the transfer of blocks for each bank. CONSTITUTION:An address signal 11 is decoded by the decoders 1A0 and 1B0, and a 0-bank signal 1A0A, a 0-block signal. 1.B0A, etc., are produced. A command signal 8 is decoded by a commend control circuit 31, end a block transfer command signal 1G0 is outputted. Then a 0-back/0-block start signal 1C5 is produced by a request signal. 7 and the signal 8. A 0-bank/l.-block start signal 1D5 is produced by the signals 7 and 1G0, and a 1,-bank/1-block start signal 1F5 is produced by the signals 7, 8 and 11. Furthermore a 1-bank/0-block start signal 1E5 is produced by the signals 7 and 1G0.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and its control circuit.

0002

2. Description of the Related Art Conventional storage devices perform interleaving operations depending on the number of bytes of the interface with a system control device, and perform interleaving operations by increasing the number of bytes of the interface to increase transfer capacity, or It adopted a technology that increases the number of interleaves while keeping the number of bytes the same.

0003

The conventional storage device described above has the disadvantage that the number of input/output interface signals increases and the amount of hardware increases.

0004

[Means for Solving the Problems] A control circuit for a storage device according to a first aspect of the invention includes (A) means for performing an interleaving operation in response to a request from a system control device;
and means for performing block transfer for each bank.

The control circuit for a storage device of the present invention includes a decoder for decoding bank addresses and a decoder for decoding block addresses in a storage device that performs interleaving operations in response to write/read requests from a system control device. Each bank address decoder signal and the request signal are logically ANDed, and the output signals (M) of these logical products are input to each bank one after another in time series (N-1) registers. It also has (N-1) registers in which each block address decoder signal (N) is inputted to each block in time series one after another, and the bank address decoder signal and request signal are input for each bank. The logical product signal, the (N-1) register signals, each block address decoder signal, and the register output signal of the (N-1) register output signals are synchronized according to predetermined conditions. The means by which the logical product is taken and the logical sum of these logical product signals are M
×N means.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, a case of two banks and two blocks will be explained. When the request signal 7a, command signal 8, and address signal 11 are transferred from the system control device, the address signal 11 is decoded by the bank address decoder 1A0, the 0 bank signal 1A0A becomes logic "1", and the block address decoder 1A0 decodes the address signal 11. Address signal 11 is decoded, 0 block signal 1
B0A becomes logic "1". Since the request signal 7a is generated, the 0 bank 0 block activation signal 1C5 is generated via the AND circuit 1C0 and the OR circuit 1C4.

0 bank signal 1A0A, 0 block signal 1
B0A is input to registers 1C2 and 1B1, respectively, and becomes logic "1". The command signal 8 is decoded by the command control circuit 31, and if the result is a block transfer operation, the block transfer command signal 1G0 becomes a logic “
It becomes 1”.

One clock after receiving the request signal 7a, the block transfer command signal 1G0 becomes logic "1".
If so, a 0 bank 1 block activation signal 1D5 is generated via an AND circuit 1D3 and an OR circuit 1D4.

Two clocks after receiving the request signal 7a, the next request signal 7b, command signal 8b,
When the address signal 11b is transferred, the 1 bank signal 1A0B and the 1 block signal 1A0B become logic "1", and the 1 bank 1 block activation signal 1F5 is generated via the AND circuit 1F0 and the OR circuit 1F4.

1 bank signal 1A0B, 1 block signal 1
B0B is input to registers 1E2 and 1B2, respectively, and becomes logic "1". If the block transfer command signal 1G0 is logic "1" one clock after receiving the request signal 7b, the AND circuit 1E3 and the OR circuit 1E4
A 1 bank 0 block activation signal 1E5 is generated via the 1 bank 0 block activation signal 1E5.

Timing control circuit 30 generates MOS timing signals 14A-14D based on each activation signal.

FIG. 2 is a time chart for explaining the operation of the control circuit of the storage device shown in FIG. The relationship from the request signal 7a to the clock signal to the 1 bank 1 block starting signal 1F5 is as shown in the figure, and the relationship between write data and read data, which will be explained next, is also shown.

FIG. 3 is a block diagram illustrating one example of use of the present invention. The contents of the main control circuit 1 are shown in FIG. Write data 12 is stored in memory matrix circuits 5A to 5D.
is written via the write data control circuit 3, and read data 13 is read via the read data control circuit 4.

First, the write operation to the 0 bank and 0 block will be explained. Address signal 11 is set in address control circuit 2 by address control signal 24, and address 16A is sent to memory matrix circuit 5A. Further, a MOS timing signal 14A is generated by the address signal 11 and the request signal 7. Write data 12 is set in write data control section 3 by write control signal 23, and write data 18A is sent to memory matrix circuit 5A. As a result, the write data 18A is written to the designated address of the memory matrix circuit 5A.

Similarly, a MOS timing signal 14B is generated, and the address signal 11 is modified by the address control circuit 2 and sent to the memory matrix circuit 5B as an address 16B. With the above steps, the block transfer operation for bank 0 is completed. The block transfer operation to one bank (memory matrix circuits 5C to 5D) is performed in the same manner.

[0017]

As described above, the control circuit for a storage device according to the present invention has the advantage that the transfer capacity can be improved without increasing the number of input/output interface signals and without increasing the amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of a control circuit of the storage device shown in FIG. 1;

FIG. 3 is a block diagram illustrating an example of use of the present invention.

[Explanation of symbols]

1 Main controller 5A to 5D Memory matrix circuit 31
command control circuit

Claims (2)

[Claims] Claim 1: (A) means for performing an interleaving operation in response to a request from a system control device; (B)
A storage device comprising: means for performing block transfer for each bank. 2. A storage device that performs an interleaving operation in response to write/read requests from a system control device, comprising a decoder for decoding bank addresses and a decoder for decoding block addresses, each bank address It has (N-1) registers in which the decoder signal and the request signal are ANDed, and the output signals (M) of these ANDs are input to each bank one after another in time series, and each block address Decoder signal (N
) are input into each block one after another in chronological order (
N-1) registers, and for each bank, an AND signal of a bank address decoder signal and a request signal,
The (N-1) register signals, each block address decoder signal, and the register output signals of the (N-1) register output signals are synchronously ANDed according to predetermined conditions. 1. A control circuit for a storage device, comprising: means for calculating the logical sum of M×N logical product signals.