JPH0519309B2 - - Google Patents
Info
- Publication number
- JPH0519309B2 JPH0519309B2 JP59099839A JP9983984A JPH0519309B2 JP H0519309 B2 JPH0519309 B2 JP H0519309B2 JP 59099839 A JP59099839 A JP 59099839A JP 9983984 A JP9983984 A JP 9983984A JP H0519309 B2 JPH0519309 B2 JP H0519309B2
- Authority
- JP
- Japan
- Prior art keywords
- well region
- region
- film
- conductivity type
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002955 isolation Methods 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法に係り、特に
分離用不純物導入領域の形成方法の改良に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming an isolation impurity-introduced region.
第１図Ａ〜Ｄは従来の製造方法の主要段階にお
ける状態を示す断面図である。まず、第１図Ａに
示すように、半導体基板、例えばシリコン基板１
にｎ形ウエル領域２とｐ形ウエル領域３とを形成
した後に、その全上面に下敷酸化膜４を形成し、
次に後述の分離用酸化膜の形成用のマスクとなる
べき窒化膜５を形成する。つづいて、第１図Ｂに
示すように、所要パターンに形成した第１のレジ
スト膜６を介して、窒化膜５に選択的にエツチン
グを施して分離用酸化膜を形成すべきｎ形ウエル
領域２とｐ形ウエル領域３との境界部位の上に開
孔７を形成する。次に、第１図ｃに示すように、
開孔７に露出するｎ形ウエル領域２の表面部分を
覆うようにパターニングされた第２のレジスト膜
８を形成した後に、ホウ素Ｂ等のイオンを注入し
て分離用不純物導入領域９を形成する。そして、
第１図Ｄに示すように、第２のレジスト膜８およ
び第１のレジスト膜７を除去した後に、窒化膜５
をマスクとして酸化を施し、分離用酸化膜１０を
形成していた。
FIGS. 1A to 1D are cross-sectional views showing the main stages of a conventional manufacturing method. First, as shown in FIG. 1A, a semiconductor substrate, for example a silicon substrate 1
After forming an n-type well region 2 and a p-type well region 3, an underlying oxide film 4 is formed on the entire upper surface thereof,
Next, a nitride film 5 is formed to serve as a mask for forming an isolation oxide film to be described later. Subsequently, as shown in FIG. 1B, the nitride film 5 is selectively etched through the first resist film 6 formed in a desired pattern to form an n-type well region where an isolation oxide film is to be formed. An opening 7 is formed above the boundary between the p-type well region 2 and the p-type well region 3. Next, as shown in Figure 1c,
After forming a second resist film 8 patterned to cover the surface portion of the n-type well region 2 exposed in the opening 7, ions such as boron B are implanted to form an isolation impurity introduction region 9. . and,
As shown in FIG. 1D, after removing the second resist film 8 and the first resist film 7, the nitride film 5 is removed.
Oxidation was performed using the mask as a mask to form the isolation oxide film 10.
ところが、上記従来の方法では、分離用不純物
導入領域９の形成のためのマスクとなる第２のレ
ジスト膜８のパターニングに当つて写真製版工程
を必要とするが、これはその時点では既に形成さ
れているｐ形ウエル領域３と直接結びつけてパタ
ーン合わせをする手段がないのでパターンずれを
生じ、適確に分離用不純物導入領域９を形成でき
ないおそれがあつた。 However, in the conventional method described above, a photolithography process is required for patterning the second resist film 8 that serves as a mask for forming the isolation impurity introduced region 9; Since there is no means for directly connecting and pattern matching the p-type well region 3, there is a possibility that the pattern may be misaligned, and the isolation impurity introduced region 9 may not be formed properly.
この発明は以上のような点に鑑みてなされたも
ので、第２導電形（ｐ形）ウエル領域を形成する
ためのマスクを分離用不純物導入領域の形成にも
利用することによつて、写真製版工程を減少させ
るとともに、両領域間のパターンのずれのない半
導体装置の製造方法を提供するものである。
This invention was made in view of the above points, and by using the mask for forming the second conductivity type (p-type) well region also for forming the isolation impurity introduced region, it is possible to It is an object of the present invention to provide a method for manufacturing a semiconductor device that reduces the number of plate-making steps and eliminates pattern misalignment between both regions.
第２図Ａ〜Ｆはこの発明の一実施例方法の主要
段階における状態を示す断面図で、第１図の従来
例と同一符号は同等部分を示す。まず、第２図Ａ
に示すように、シリコン基板１の主面部の一部に
リン（Ｐ）、ヒ素（As）などのイオンを注入して
ｎ形ウエル領域を形成するためのn+形領域１１
を形成し、その全上面に下敷酸化膜４を形成し、
次に分離用酸化膜の形成用のマスクとなるべき窒
化膜５ａを形成した後に、所要パターンに形成し
た第１のレジスト膜６ａを介して窒化膜５ａにエ
ツチングを施して後に分離用酸化膜形成のための
開孔７ａを形成する。次に、第２図Ｂに示すよう
に、第１のレジスト膜６ａを除去した後に、開孔
７ａの内部を含めて、窒化膜５ａの上に酸化膜１
２を形成し、更に、その上にｐ形ウエル領域形成
部位の上に開孔を有するようにパターニングされ
た第２のレジスト膜１３を形成する。つづいて、
第２図Ｃに示すように、この第２のレジスト膜１
３を介して酸化膜１２にエツチングを施してｐ形
ウエル領域形成部位に対応する開孔１４を形成
し、その部位の窒化膜５ａを露出させ、次に、こ
の窒化膜５ａを貫通する加速電圧で、図示矢印の
ように、ホウ素Ｂなどのイオンを打込んでｐ形ウ
エル領域を形成するためのp+形領域１５を形成
する。更につづいて、第２図Ｄに示すように、高
温処理して、シリコン基板１の上面露出部を酸化
させつつ、n+形領域１１およびp+形領域１５の
不純物をドライブしてそれぞれｎ形ウエル領域２
およびｐ形ウエル領域３を形成する。次に、第２
図Ｅに示すように、酸化膜１２とｐ形ウエル領域
３上の窒化膜５ａとをマスクとして、図示矢印の
ように、ホウ素Ｂなどのイオンを低エネルギーで
打込むか、または拡散によつて、分離用不純物導
入領域９をｐ形ウエル領域３のｎ形ウエル領域２
に接する部分に形成する。その後に、第２図Ｆに
示すように、酸化膜１２を除去し、窒化膜５ａを
マスクとして酸化を施して、ｐ形ウエル領域３と
ｎ形ウエル領域２との境界の表面部に分離用酸化
膜１０を形成する。
FIGS. 2A to 2F are sectional views showing the main stages of a method according to an embodiment of the present invention, and the same reference numerals as in the conventional example of FIG. 1 indicate equivalent parts. First, Figure 2A
As shown in FIG. 1, an n + type region 11 is formed to form an n type well region by implanting ions such as phosphorus (P) and arsenic (As) into a part of the main surface of the silicon substrate 1.
, and an underlying oxide film 4 is formed on the entire upper surface thereof,
Next, after forming a nitride film 5a to serve as a mask for forming an isolation oxide film, the nitride film 5a is etched through a first resist film 6a formed in a desired pattern, and then an isolation oxide film is formed. An opening 7a is formed for this purpose. Next, as shown in FIG. 2B, after removing the first resist film 6a, an oxide film 1 is formed on the nitride film 5a, including the inside of the opening 7a.
A second resist film 13 is formed thereon, which is patterned to have an opening above the p-type well region formation site. Continuing,
As shown in FIG. 2C, this second resist film 1
3, the oxide film 12 is etched to form an opening 14 corresponding to the p-type well region formation region, and the nitride film 5a in that region is exposed, and then an accelerating voltage is applied to penetrate the nitride film 5a. Then, as shown by the arrow in the figure, ions such as boron B are implanted to form a p + -type region 15 for forming a p-type well region. Further, as shown in FIG. 2D, high-temperature treatment is performed to oxidize the exposed upper surface of the silicon substrate 1 while driving the impurities in the n + type region 11 and the p + type region 15 to form n-type regions. Well area 2
and p-type well region 3 is formed. Next, the second
As shown in FIG. , the isolation impurity introduced region 9 is connected to the n-type well region 2 of the p-type well region 3.
Formed on the part that touches the. After that, as shown in FIG. 2F, the oxide film 12 is removed and oxidation is performed using the nitride film 5a as a mask to form an isolation layer on the surface of the boundary between the p-type well region 3 and the n-type well region 2. An oxide film 10 is formed.
以上この実施例ではｐ形ウエル領域３の形成に
用いたマスク酸化膜１２を分離用不純物導入領域
９の形成にも用いたので、写真製版工程を１回減
らすことができ、従つてパターンずれのおそれも
ない。 As described above, in this embodiment, since the mask oxide film 12 used for forming the p-type well region 3 is also used for forming the isolation impurity introduced region 9, the number of photolithography steps can be reduced by one, and pattern misalignment can be avoided. There's no fear.
なお、上記実施例ではｐ形ウエル領域とｎ形ウ
エル領域との分離の場合を示したが、半導体基板
内の第１導電形層とそれに接して形成された第２
導電形ウエル領域との分離に広く、この発明は適
用できる。 In the above embodiment, the p-type well region and the n-type well region are separated, but the first conductivity type layer in the semiconductor substrate and the second conductivity type layer formed in contact with it are separated.
The present invention is widely applicable to separation from conductive well regions.
以上説明したように、ウエル領域の形成に用い
たマスクを分離用不純物導入領域の形成にも利用
するようにしたので、写真製版工程が１回減少
し、従つてマスクずれのおそれもなくなり、コス
トの低減と製品品質の向上が可能となる。
As explained above, since the mask used to form the well region is also used to form the isolation impurity doped region, the number of photolithography steps is reduced by one, and therefore, there is no risk of mask displacement, and costs are reduced. This makes it possible to reduce energy consumption and improve product quality.
第１図Ａ〜Ｄは従来の製造方法の主要段階にお
ける状態を示す断面図、第２図Ａ〜Ｆはこの発明
の一実施例方法の主要段階における状態を示す断
面図である。
図において、１は半導体基板、２はｎ形ウエル
領域（第１の領域）、３はｐ形ウエル領域（第２
導電形のウエル領域）、５ａは窒化膜（第１の
膜）、７ａは第１の開孔、９は分離用不純物導入
領域、１２は酸化膜（第２の膜）、１４は第２の
開孔である。なお、図中同一符号は同一または相
当部分を示す。
1A to 1D are sectional views showing the main stages of a conventional manufacturing method, and FIGS. 2A to 2F are sectional views showing the main stages of a method according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an n-type well region (first region), and 3 is a p-type well region (second region).
conductivity type well region), 5a is a nitride film (first film), 7a is a first opening, 9 is an isolation impurity introduced region, 12 is an oxide film (second film), and 14 is a second film. It is an open hole. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
域と接し、ともに上記半導体基板の表面に露出す
る第２導電形の第２のウエル領域と、上記第１、
第２のウエル領域の境界に分離酸化膜と分離用不
純物導入領域とを有する半導体装置の製造方法に
おいて １ 上記第１のウエル領域と上記第２のウエル領
域との境界となるべき線をはさんで上記両ウエ
ル領域にわたる所要幅の第１の開孔を有する第
１の膜を上記基板上に形成する工程と、 ２ 上記第２のウエル領域を形成すべき部位に第
２の開孔を有する第２の膜を形成する工程と、 ３ 上記第２の膜をマスクとして、上記第２の開
孔内にある上記第１の膜を貫通する加速電圧で
第２導電形不純物イオンを打込む工程と、 ４ 上記イオン打込み後に熱処理を行い上記第２
のウエル領域を形成する工程と、 ５ 上記第２の膜および上記第２の開孔内にある
上記第１の膜をマスクとして第２導電形不純物
イオンを打込む工程と、 ６ 上記イオン打込み後に熱酸化処理を行い、上
記分離用酸化膜および分離用不純物導入領域を
形成する工程 とを備えたことを特徴とする半導体装置の製造方
法。 ２ 第１導電形の第１の領域がｎ形ウエル領域で
あり、第２導電形のウエル領域がＰ形ウエル領域
であることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。[Scope of Claims] 1. A second well region of a second conductivity type in contact with a first well region of a first conductivity type in a semiconductor substrate and both exposed on the surface of the semiconductor substrate;
In a method for manufacturing a semiconductor device having an isolation oxide film and an isolation impurity doped region at the boundary of a second well region, 1. A line that should be a boundary between the first well region and the second well region is sandwiched between the two. forming on the substrate a first film having a first aperture of a required width spanning both the well regions; 2 having a second aperture in a region where the second well region is to be formed; forming a second film; 3 using the second film as a mask and implanting second conductivity type impurity ions with an accelerating voltage that penetrates the first film in the second opening; 4. After the ion implantation, heat treatment is performed and the second
5. Implanting second conductivity type impurity ions using the second film and the first film in the second opening as a mask; 6. After the ion implantation. A method for manufacturing a semiconductor device, comprising the step of performing thermal oxidation treatment to form the isolation oxide film and the isolation impurity introduction region. 2. Manufacturing a semiconductor device according to claim 1, wherein the first region of the first conductivity type is an n-type well region, and the well region of the second conductivity type is a p-type well region. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59099839A JPS60242637A (en) | 1984-05-16 | 1984-05-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59099839A JPS60242637A (en) | 1984-05-16 | 1984-05-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60242637A JPS60242637A (en) | 1985-12-02 |
| JPH0519309B2 true JPH0519309B2 (en) | 1993-03-16 |
Family
ID=14257966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59099839A Granted JPS60242637A (en) | 1984-05-16 | 1984-05-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60242637A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5436077A (en) * | 1977-08-24 | 1979-03-16 | Toshiba Corp | Sintered electrode for use in discharge tube lamp |
-
1984
- 1984-05-16 JP JP59099839A patent/JPS60242637A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5436077A (en) * | 1977-08-24 | 1979-03-16 | Toshiba Corp | Sintered electrode for use in discharge tube lamp |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60242637A (en) | 1985-12-02 |
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