JP3325692B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a plurality of grooves having different depths are formed in a semiconductor layer on a semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing a structure of a conventional semiconductor device. In the figure, reference numeral 1 denotes a p-type semiconductor substrate, 2 denotes an n ⁺ -type buried region formed on the semiconductor substrate 1, and 3 denotes an n ^-- type epitaxial layer (for example) formed on the buried region 2. Hereinafter referred to as the epi layer),
Reference numerals 4 and 5 denote first and second grooves formed to the depth of the semiconductor substrate 1 for separating elements, and 6 is provided in a region sandwiched between the grooves 4 and 5 to define an active region in the element. This is a third groove provided in the epi layer 3 for separation.

Reference numeral 7 denotes an oxide film buried in each of the trenches 4, 5, and 6, reference numeral 8 denotes a base diffusion region formed in a region sandwiched between the first and third trenches 4, 6, and reference numeral 9 denotes a base diffusion region. An emitter diffusion region 10 formed in the diffusion region 8 is a region sandwiched between the second and third trenches 5 and 6, a collector diffusion region connected to the buried region 2, and 11 is an epi layer 3. An interlayer insulating film 12 formed on the base diffusion region 8 through a contact hole provided in the interlayer insulating film 11,
These are wiring electrodes formed to be connected to the emitter diffusion region 9 and the collector diffusion region 10, respectively.

[0004] Next, a manufacturing process of a conventional semiconductor device will be described with reference to FIGS. 9 to 12. First, p
N ⁺ into the semiconductor substrate 1 by, for example, As ion implantation.
Buried region 2 is formed, and an n ^- type epi layer 3 is formed thereon.
Is grown (FIG. 10-a). Next, a resist material is applied on the epi layer 3 to form a first groove forming mask 13 in which openings for forming the third grooves 6 are patterned by photolithography (FIG. 10B). .

Next, the epitaxial layer 3 is etched through the first groove forming mask 13 to form a third groove 6 (FIG. 10-c). Then, the first groove forming mask 13 is removed (FIG. 10D). Next, a resist material is applied on the epi layer 3 again, and a second groove forming mask 14 in which openings for forming the first and second grooves 4 and 5 are patterned by photolithography is formed. (FIG. 11-a).

Next, through the second groove forming mask 14, the etching amount is increased from the etching time to reach the semiconductor substrate 1, and the first and second grooves 4 are formed.
5 is formed (FIG. 11-b). Then, the second groove forming mask 14 is removed (FIG. 11C). Next, each groove 4,
An oxide film 7 is buried in 5 and 6 (FIG. 12-a).
Doping with N-type impurities such as phosphorus by thermal diffusion,
A collector diffusion region 10 is formed. Next, a P-type impurity such as boron and an N-type impurity such as arsenic are ion-implanted and activated by heat treatment to form a base diffusion region 8 and an emitter diffusion region 9, respectively (FIG. 12B). ).

Next, an interlayer insulating film 11 is formed on the epi layer 3, and contact holes are formed in the interlayer insulating film 11, and the base diffusion region 8, the emitter diffusion region 9 and the collector are formed through these contact holes. Forming wiring electrodes 12 connected to the diffusion regions 10 respectively,
A semiconductor device including the bipolar transistor shown in FIG. 9 can be obtained.

[0008]

As described above, in the conventional method of manufacturing a semiconductor device, a plurality of grooves having different depths are formed by performing photolithography for each of the grooves having the respective depths. Since the etching process is repeatedly performed, there is a problem that relative misalignment of the groove due to misalignment of the mask occurs.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and has as its object to provide a method of manufacturing a semiconductor device which can prevent relative displacement between grooves due to misalignment of a mask. .

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an opening area narrower than an opening area of a deep groove is formed in a region where a deep groove is formed.
To form a mask for ion implantation, and
Ion implantation through an on-implantation mask and ion implantation
Groove corresponding to the width of the groove opening area by removing the mask for
A formation mask is formed on the semiconductor layer, and a mask is formed through the groove formation mask.
Then, etching is performed to form a groove .

A semiconductor device according to a second aspect of the present invention.
Is a method of manufacturing the second conductive type on a substrate of the first conductive type.
The buried layer and the epitaxial layer of the second conductivity type are sequentially deposited.
To form a semiconductor substrate and form a deeper groove.
Implants deeper than the region where the shallow trench is formed
At the same time as ion implantation,
To form a trench after forming a collector diffusion region.
A mask having an opening at a location where
Etching through a mask to form a groove.
You.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
Ion injection where the opening area smaller than the area is patterned
A mask for ion implantation and a mask for ion implantation on the semiconductor layer.
Through the ion implantation and remove the ion implantation mask
To form a groove forming mask corresponding to the width of the groove opening area.
Formed on the body layer and etched through a groove forming mask.
By forming the grooves, grooves having different depths are simultaneously formed.

According to a second aspect of the present invention, a semiconductor device is provided.
The method of manufacturing the device comprises the steps of: forming a second conductive type on a substrate of a first conductive type;
Buried layer and the second conductivity type epitaxial layer
Deposit to form a semiconductor substrate, forming a deeper groove
Implant ions deeper than the region that forms the shallower groove in the region
At the same time as ion implantation,
To form a trench after forming a collector diffusion region.
A mask having an opening at a location where
Etching through a mask allows for different depths
And a collector diffusion region are simultaneously formed.

[0014]

[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating the configuration of the semiconductor device according to the first embodiment. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted. Reference numerals 15 and 16 denote first and second layers formed to the depth of the semiconductor substrate 1 for separating the elements.
The groove 17 is a third groove provided in a region sandwiched between the grooves 15 and 16 and provided in the epi layer 3 for isolating the active region in the device.

Next, the first embodiment configured as described above
1 to 3 will be described with reference to FIGS. First, as in the conventional case, an n ⁺ -type buried region 2 is formed in a p-type semiconductor substrate 1 by, for example, As ion implantation, and an n ⁻ -type epi layer 3 is grown thereon (FIG. 2). -A).

Next, a resist material is applied on the epi layer 3 and an opening 19 having a width W19 of, for example, 1 μm and a third groove 17 for forming the first and second grooves 15 and 16 by photolithography. For example, a groove forming mask 18 is formed by patterning an opening 20 having a width W20 of, for example, 0.1 μm according to the width of the groove (FIG. 2B). At this time, the width W19 of the deeper grooves 15 and 16 is equal to the width W2 of the shallower groove 17.
It is formed wider than zero.

Next, etching is performed through the groove forming mask 18 to simultaneously form the grooves 15, 16 and 17 (FIG. 2C). As is clear from the figure, the micro-loading effect in which the amount of the etchant reaching the etched portion changes depending on the opening width, so that even if etching is performed at the same time, the wider portion W 19 has a depth 2 to the semiconductor substrate 1.
μm, and the etching amount at the narrower width W20 is 1 μm to the epi layer 3. Then, the groove forming mask 18 is removed (FIG. 3A).

Next, as in the conventional case, each groove 15, 1
The oxide film 7 is buried in 6 and 17 (FIG. 3B), and then an N-type impurity such as phosphorus is doped by thermal diffusion to form a collector diffusion region 10. Next, a P-type impurity such as boron and an N-type impurity such as arsenic are ion-implanted and activated by heat treatment to form a base diffusion region 8 and an emitter diffusion region 9, respectively (FIG. 3).
-C). Next, an interlayer insulating film 11 is formed on the epi layer 3,
Then, contact holes are formed in the interlayer insulating film 11, and wiring electrodes 12 respectively connected to the base diffusion region 8, the emitter diffusion region 9 and the collector diffusion region 10 via these contact holes are formed. The semiconductor device provided with the bipolar transistor shown in FIG.

As described above, in the first embodiment, the plurality of grooves 15, 16, 17 having different depths are patterned so that the opening width W19 of the deeper grooves 15, 16 is wider than the opening width W20 of the shallower groove 17. Since it is formed in a single etching process via the groove forming mask 18, the manufacturing process is of course simplified, and the relative positions between the grooves 15, 16 and 17 due to misalignment of the mask. Misalignment can be prevented.

Embodiment 2 FIG. FIG. 4 is a sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 21 denotes a silicon oxide film formed at the bottom of the third groove 6 slightly wider than the width of the groove.

Next, a manufacturing process of the semiconductor device according to the second embodiment will be described with reference to FIGS. First,
As in the first embodiment, the buried region 2 is formed on the semiconductor substrate 1.
And an epi layer 3 are sequentially formed, a resist material is applied on the epi layer 3, and, for example, one side is 0.25 μm or more wider than the width of the groove at a position where the shallow third groove 6 is formed by photolithography. Oxygen implantation mask 22 with wide openings patterned
To form Then, O ⁺ ions are implanted through the oxygen implantation mask 22 at 10 ¹⁸ cm ⁻² at, for example, 300 KeV, and at one side corresponding to the bottom of the third groove 6, for example, 0.25 μm or more from one side of the width of the groove An expanded oxygen ion implanted region 23 is formed, and heat treatment is performed so that the oxygen ion implanted region 23 has a silicon oxide film 2 of about 10 ^-1 μm.
1 (FIG. 5-b).

Next, a resist material is applied on the epi layer 3 again, and a photolithography is performed to form a groove forming mask 24 in which openings for forming the grooves 4, 5, and 6 are patterned (FIG. 5). c). Next, etching is performed through the groove forming mask 24 to form the grooves 4, 5, and 6 having different depths (FIG. 6A). As is apparent from the figure, the third groove 6 is formed shallow because the etching rate of the silicon oxide film 21 formed in advance is much slower than the etching rate of the epi layer 3 and serves as a stopper. Then, the groove forming mask 24 is removed (FIG. 6B).

Next, an N-type impurity such as phosphorus is doped by thermal diffusion to form a collector diffusion region 10.
Next, a P-type impurity such as boron, for example, and an N-type impurity such as arsenic
The base diffusion region 8 and the emitter diffusion region 9 are respectively formed by ion-implanting the type impurity and activating it by performing a heat treatment. Next, an interlayer insulating film 11 is formed on the epitaxial layer 3, and contact holes are formed in the interlayer insulating film 11, and the base diffusion region 8, the emitter diffusion region 9, and the collector diffusion region 1 are formed through these contact holes.
By forming the wiring electrodes 12 connected to 0, respectively, a semiconductor device having a bipolar transistor as shown in FIG. 4 is formed. Even if a mask misalignment between the oxygen implantation mask 22 and the groove forming mask 24 occurs, the silicon oxide film 21 is formed in a region wider than the bottom of the third groove 6 by a margin for mask misalignment. Therefore, the silicon oxide film 21 is not etched off.

As described above, in the third embodiment, the plurality of grooves 4, 5, and 6 having different depths are formed by forming the silicon oxide film 21 in the region corresponding to the bottom of the shallower third groove 6. Since it is formed by one-time etching via the forming mask 24, it is possible to prevent relative displacement between the grooves 4, 5, and 6 due to misalignment of the mask.

Embodiment 3 FIG. In the second embodiment, an example is shown in which the silicon oxide film 21 is used as a stopper at the time of etching. However, the present invention is not limited to this, and instead of O ⁺ ions, N ⁺ ions are implanted in the same manner as in the third embodiment, and annealing is performed. The same effect as in the second embodiment can be obtained by forming the silicon nitride film in a region corresponding to the bottom of the groove by performing the processing, and then using the silicon nitride film as a stopper at the time of etching.

Embodiment 4 FIG. FIG. 7 is a sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted. Reference numerals 25 and 26 denote first and second grooves formed to the depth of the semiconductor substrate 1 for separating the elements.

Next, the fourth embodiment configured as described above.
The method of manufacturing the semiconductor device will be described with reference to FIGS. First, the buried region 2 and the epi layer 3 are sequentially formed on the semiconductor substrate 1 in the same manner as in the first embodiment, a resist material is applied on the epi layer 3, and the first and second deeper layers are formed by photolithography. An ion implantation mask 27 is formed at a position where the second grooves 25 and 26 are to be formed, in which an opening narrower than, for example, 0.25 μm on one side is patterned. Then, 10 ¹⁶ example, phosphorus ions (P ⁺⁾ at 100KeV
10 ¹⁶ to 10 ¹⁷ cm at -10 ¹⁷ cm ^-2 and 300 KeV
^-2 to form an ion implanted region 28 (FIG. 8-
a).

Next, the ion implantation mask 27 is removed,
A resist material is applied on the epi layer 3 again, and a photolithography process is performed to form a groove forming mask 29 in which openings for forming the grooves 25, 26, and 6 are patterned (FIG. 8B).
Next, etching is performed through the groove forming mask 29 to form the grooves 25, 26, and 6 having different depths (FIG. 8-).
c). As is clear from the figure, since the etching rate of the ion implantation region 28 formed in advance is higher than that of the region not ion-implanted, the grooves 25, 2
6 is deeply formed. Then, the groove forming mask 29
Is removed (FIG. 8D).

Next, the collector diffusion region 10 is formed by doping an N-type impurity such as phosphorus by thermal diffusion.
Next, a P-type impurity such as boron, for example, and an N-type impurity such as arsenic
The base diffusion region 8 and the emitter diffusion region 9 are respectively formed by ion-implanting the type impurity and activating it by performing a heat treatment. Next, an interlayer insulating film 11 is formed on the epitaxial layer 3, and contact holes are formed in the interlayer insulating film 11, and the base diffusion region 8, the emitter diffusion region 9, and the collector diffusion region 1 are formed through these contact holes.
By forming the wiring electrodes 12 respectively connected to 0, a semiconductor device having a bipolar transistor as shown in FIG. 7 is formed. The ion implantation mask 27
Even if a mask misalignment between the mask and the groove forming mask 29 occurs, the ion-implanted region 28 remains in the first and second grooves 2.
Since it is formed narrower than the regions 5 and 26 by the margin of the mask misalignment, the ion implantation region 28 which may cause a trouble at the end of the etching does not remain.

As described above, in the fourth embodiment, the plurality of grooves 25, 26, and 6 having different depths are
After the ion implantation regions 28 are formed in the regions 5 and 26, they are formed by a single etching using the groove forming mask 29.
It is possible to prevent the relative displacement between 6,6.

Embodiment 5 FIG. In the fourth embodiment, the example in which the ion implantation region 28 is formed by phosphorus ions is described. However, the present invention is not limited to this. For example, the ion implantation region may be formed by using B ions, As ions, or the like. Needless to say, the same effect as in the fourth embodiment is obtained.

Embodiment 6 FIG. In the fourth embodiment, the example in which the collector diffusion region 10 is formed after the formation of each of the grooves 25, 26, and 6 has been described. However, the present invention is not limited to this.
If an n-type impurity such as P or As is used as an ion species to be implanted into the ion implantation region, for example, simultaneously with the opening of the ion implantation region 28 at the time of forming the ion implantation mask 27 shown in FIG. An opening in the collector diffusion region 10 is also provided, as shown in FIG.
As shown in (b), when the ion implantation region 28 is formed, the collector diffusion region 10 may also be formed at the same time, so that the manufacturing process can be simplified.

Embodiment 7 FIG. In each of the above embodiments, the case where grooves of two kinds of depths are formed is shown. However, the present invention is not limited to this, and the same effects as those of the above embodiments can be obtained when grooves of three or more kinds of depths are formed. To play.

[0034]

As described above, according to the first aspect of the present invention, the opening area of the deep groove is formed in the region where the deep groove is formed.
Ion implantation where the opening area smaller than the area is patterned
A mask for ion implantation through the semiconductor layer
And ion implantation, removing the ion implantation mask,
The semiconductor layer is provided with a groove forming mask corresponding to the width of the groove opening area.
Formed on top and etched through a groove forming mask
By forming the grooves, it is possible to provide a method of manufacturing a semiconductor device capable of preventing a relative positional shift between the grooves due to a mask misalignment.

According to a second aspect of the present invention, the first
A buried layer of a second conductivity type on the substrate of the conductivity type and a second conductive layer;
Semiconductor substrate by successively depositing
And shallow groove in the area where the deep groove is to be formed
Implant ions deeper than the region to be
Ion implantation into specified area of buried layer and collector diffusion
After forming the region, a mask having an opening at the location where the groove is to be formed
Mask is formed on the semiconductor layer and etched through the mask
To form a groove,
Can prevent relative displacement between grooves
To provide a method of manufacturing a semiconductor device which can simplify the process.
Can be.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device shown in FIG.

3 is a cross-sectional view showing the remaining part of the method for manufacturing the semiconductor device shown in FIG.

FIG. 4 is a sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

5 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device shown in FIG.

6 is a cross-sectional view showing the remaining part of the method for manufacturing the semiconductor device shown in FIG.

FIG. 7 is a cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 7;

FIG. 9 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

10 is a cross-sectional view showing a part of the step of the method for manufacturing the semiconductor device shown in FIG. 9;

11 is a cross-sectional view showing a part of the step of the manufacturing method of the semiconductor device shown in FIG. 9;

12 is a cross-sectional view showing a part of the step of the method for manufacturing the semiconductor device shown in FIG. 9;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 buried region, 3 epitaxial layer, 4, 15, 25 first groove, 5, 16, 26 second
Groove, 6, 17 third groove, 18, 24, 29 groove forming mask, 21 silicon oxide film, 22 oxygen implantation mask, 23 oxygen ion implantation region, 27 ion implantation mask, 28 ion implantation region.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-166748 (JP, A) JP-A-5-121537 (JP, A) JP-A-60-171730 (JP, A) JP-A-62-162 213258 (JP, A) JP-A-62-165541 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 H01L 21/331 H01L 21/76

Claims (2)

(57) [Claims] In a method for manufacturing a semiconductor device, wherein at least two grooves having different depths are formed in a semiconductor layer on a semiconductor substrate, the deeper groove is formed in a region where the deeper groove is formed .
An opening area narrower than the opening area of the groove was patterned
Forming an ion implantation mask; and
A step of implanting ions through the ion implantation mask
And removing the ion implantation mask and opening the groove.
A groove forming mask corresponding to the width of the region is formed on the semiconductor layer.
Forming and etching through the groove forming mask
And forming the groove by performing etching . 2. The semiconductor device according to claim 1 , wherein the semiconductor layers on the semiconductor substrate have different depths.
A method for manufacturing a semiconductor device in which at least two grooves are formed.
A buried layer of a second conductivity type on a substrate of the first conductivity type.
And sequentially depositing the epitaxial layer of the second conductivity type.
To form a semiconductor substrate, and
Deeper than the shallow groove
The step of implanting ions, and
The above-mentioned ions are also implanted into a predetermined region of the buried layer to collect
Step of forming a diffusion region and opening at the location where the groove is to be formed.
Forming a mask having an opening on the semiconductor layer,
Etching through the mask to form the groove
And a method for manufacturing a semiconductor device, comprising:
Law.