JPH06151832A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a MOS transistor with a high element breakdown strength. CONSTITUTION:A process for forming an element isolation oxide film 30 consisting of a field oxide film part 31 and a bird's peak part 32 by forming a selective oxidation mask 20 on a buffer oxide film 11 which is formed on a semiconductor substrate for selectively oxidizing a semiconductor substrate 10, a process for forming a gate oxide film 40, a process for forming a gate electrode 51 reaching the bird's peak part 32 by covering the gate oxide film 40, and a process for forming an ion implantation mask 61 covering the gate electrode 51, forming a source part 70 and a drain part 80 by performing ion implantation of desired conductive type impurities to the semiconductor substrate 10, and then forming a PN junction part 72 reaching the lower part of the bird's peak part 32 by thermally diffusing the source part 70 and the drain part 80 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method for manufacturing a MOS transistor having an improved device breakdown voltage.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing a MOS transistor having an increased breakdown voltage, an LDD (Light) shown in FIG.
A manufacturing method for forming a tally doped drain structure is known. FIG. 2 is a schematic view of a manufacturing process of a conventional MOS transistor having an LDD structure.

In FIG. 2A, after a buffer oxide film 11 is formed on a silicon semiconductor substrate 10 by thermal oxidation, a silicon nitride film 2 is formed on the buffer oxide film 11.
0 for CVD (Chemical Vapor Dep)
The silicon nitride film 2 is laminated by
0 is photoetched to form a selective oxidation mask 21.

Next, referring to FIG. 2B, the semiconductor substrate 1
0 is selectively oxidized to form a thick element isolation oxide film 30.
Next, in FIG. 2C, after the selective oxidation mask 21 and the buffer oxide film 11 are removed, a gate oxide film 40 is formed on the removed portion by thermal oxidation, and N-type impurities such as phosphorus are added. Doped polysilicon film 5
0 is laminated on the entire surface by CVD to form a polysilicon film 5
0 is photo-etched to form a gate electrode 51 on the gate oxide film 40.

Next, referring to FIG. 2D, the semiconductor substrate 1
An impurity 63 of a conductivity type opposite to the conductivity type of the semiconductor substrate 10 is ion-implanted at a low concentration on the entire surface of the semiconductor substrate 0 to self-align with the gate electrode 51 and the isolation oxide film 30 in the LDD portion 71.
To form.

Next, in FIG. 2 (e), a silicon oxide film 90 is laminated on the entire surface by CVD, and in FIG. 2 (f), this silicon oxide film 90 is subjected to reactive ion etching in a direction perpendicular to the semiconductor substrate 10. The LDD mask 91 is left on the sidewall of the gate electrode 51 by anisotropic etching.

Then, in FIG. 2G, an impurity 64 of a conductivity type opposite to the conductivity type of the semiconductor substrate 10 is ion-implanted at a high concentration on the entire surface of the semiconductor substrate 10 to form the LDD mask 9
The source part 70 and the drain part 80 are formed in a self-aligned manner with respect to 1 and the element isolation oxide film 30.

In the MOS transistor manufactured as described above, since the low-concentration LDD portion 71 connected to the high-concentration source portion 70 and the drain portion 80 is formed under the gate electrode 51, the gate electrode 51 and the drain portion are formed. When a bias is applied to 80, the depletion layer also extends to the LDD portion 71 on the drain portion 80 side. Therefore, the electric field from the gate electrode 51 is not concentrated in the high-concentration drain portion 80 and LDD
Dispersed on the side of the portion 71, the breakdown voltage of the element is improved.

[0009]

In such a conventional technique, the silicon oxide film 90 is anisotropically etched in the direction perpendicular to the semiconductor substrate 10 by reactive ion etching or the like to form a sidewall of the gate electrode 50. When the LDD mask 91 is left unetched, it is difficult to control the end point of the etching, which makes it difficult to stably form the LDD structure. The present invention has been made in view of the above problems of the related art, and an object of the present invention is to provide a method for manufacturing a MOS transistor capable of stably manufacturing a MOS transistor having a high device breakdown voltage. It is to be.

[0010]

In order to achieve the above object, the present invention is directed to forming a selective oxidation mask having oxidation resistance on a buffer oxide film formed on a semiconductor substrate to selectively oxidize the semiconductor substrate. Then, a step of forming an element isolation oxide film including a field oxide film portion outside the selective oxidation mask and a bird's beak portion connected from the field oxide film portion under the selective oxidation mask, the selective oxidation mask and the buffer oxidation film are formed. A step of forming a gate oxide film in the portion where the film is removed, a step of forming a gate electrode that covers the gate oxide film and reaches the bird's beak portion, and an ion implantation mask that covers the gate electrode are formed to form a desired film on the semiconductor substrate. After the source and drain parts are formed by ion-implanting the impurities of the conductivity type, the source and drain parts are thermally diffused, It is a manufacturing method of a MOS transistor, characterized by comprising the steps of forming a PN junction reaches the bottom of the click portion.

[0011]

According to the present invention, the bird's beak portion is formed by selectively oxidizing a semiconductor substrate after forming a selective oxidation mask on a buffer oxide film formed on the semiconductor substrate.
The gate oxide film is formed in a portion where the selective oxidation mask and the buffer oxide film are removed, the gate electrode is formed so as to reach the bird's beak portion covering the gate oxide film, and the source portion and the drain portion are formed by ion implantation formed so as to cover the gate electrode. The semiconductor substrate is formed by ion-implanting impurities of a desired conductivity type through the mask, and the PN junction is formed by thermally diffusing the source and drain under the bird's beak.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. In the following drawings, the same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. Figure 1
FIG. 4 is a schematic view of a manufacturing process of a MOS transistor showing an embodiment according to the present invention.

In FIG. 1A, a buffer oxide film 11 is formed on a silicon semiconductor substrate 10 by thermal oxidation, and then a silicon nitride film 2 is formed on the buffer oxide film 11.
0 is stacked by CVD and the silicon nitride film 20 is photoetched to form a selective oxidation mask 21.

Next, referring to FIG. 1B, the semiconductor substrate 1
0 is selectively oxidized to form an element isolation oxide film 30 including a thick field oxide film portion 31 and a bird's beak portion 32. In this case, the bird's beak portion 32 is formed with a triangular cross section by the selective oxidation entering under the selective oxidation mask 21 and proceeding.

Next, in FIG. 1C, after the selective oxidation mask 21 and the buffer oxide film 11 are removed, the gate oxide film 40 is formed on the portion where the selective oxidation mask 21 and the buffer oxide film 11 are removed by thermal oxidation. Then, a polysilicon film 50 doped with an N-type impurity such as phosphorus is formed on the entire surface by CVD or the like, and the polysilicon film 50 is photoetched to cover the gate oxide film 40 and the bird's beak portion 32. Then, the gate electrode 51 is formed.

Next, in FIG. 1D, a metal film 60 made of aluminum or the like is laminated on the entire surface, and the metal film 60 is photoetched to cover the gate electrode 51 with an ion implantation mask 61.
To form. Then, in FIG. 1E, the semiconductor substrate 1
An impurity 62 having a conductivity type opposite to that of 0 is ion-implanted into the boundary portion between the field oxide film portion 31 and the bird's beak portion 32 with a high concentration and a high implantation energy to form a source portion 70 and a drain portion 80.

Next, in FIG. 1F, after removing the ion implantation mask 61, the source portion 70 and the drain portion 8 are formed.
0 is thermally diffused to form the PN junction 72. In this case, the diffusion also proceeds in a direction parallel to the surface of the semiconductor substrate 10, so that the PN junction 72 is formed below the bird's beak 32.

In the MOS transistor manufactured in this way, the oxide film thickness of the bird's beak portion 32 below the gate electrode 51 is larger than that of the gate oxide film 40. When a bias is applied, the electric field from the gate electrode 51 is dispersed in the PN junction 72, and the breakdown voltage of the device is improved.

[0019]

As described above, according to the present invention, the gate electrode is formed on the bird's beak formed by selective oxidation for element isolation without the difficult process of forming the LDD mask on the side wall of the gate electrode. Since the source portion and the drain portion are formed so as to form the PN junction portion under the bird's beak, a MOS transistor having a high device breakdown voltage can be stably manufactured by a simple process.
A method for manufacturing an OS transistor can be provided.

[Brief description of drawings]

FIG. 1 is a schematic view of a manufacturing process of a MOS transistor showing an embodiment according to the present invention.

FIG. 2 is a schematic view of a manufacturing process of a conventional MOS transistor having an LDD structure.

[Explanation of symbols]

 10 semiconductor substrate 11 buffer oxide film 21 selective oxidation mask 30 element isolation oxide film 31 field oxide film portion 32 bird's beak portion 40 gate oxide film 51 gate electrode 61 ion implantation mask 62 impurity 70 source portion 72 PN junction portion 80 drain portion

Claims (1)

[Claims] 1. A field oxide film portion outside the selective oxidation mask and a field oxide film portion outside the selective oxidation mask are formed by forming an oxidation resistant selective oxidation mask on a buffer oxide film formed on the semiconductor substrate. A step of forming an element isolation oxide film consisting of a bird's beak portion connected from a film portion under the selective oxidation mask, a step of forming a gate oxide film in a portion where the selective oxidation mask and the buffer oxide film are removed, Forming a gate electrode covering the gate oxide film and reaching the bird's beak portion; forming an ion implantation mask covering the gate electrode, and implanting a desired conductivity type impurity into the semiconductor substrate to form a source portion and a drain portion. After the formation, a step of thermally diffusing the source part and the drain part to form a PN junction reaching the lower part of the bird's beak part, A method of manufacturing a MOS transistor, comprising: