JPH0519010A - Chip for evaluating resin-sealed semiconductor - Google Patents

Abstract

PURPOSE:To simply and correctly evaluate aluminum sliding ability or wiring sliding ability in a chip for evaluating a resin-sealed semiconductor which is used for evaluating performance of a semiconductor device which has been manufactured with a semiconductor chip sealed with resin. CONSTITUTION:Reference wires 40, 70 and evaluating wires 30, 50, 60 are provided in the vicinity of an outer periphery perpendicular to a line S connecting the center C of a chip substrate 10 and an outer peripheral corner T on an insulation layer 20 formed on a surface of the chip substrate 10. The reference wires 40, 70 are formed with a sufficiently wide width to a degree that no wire sliding occurs, while the evaluating wires 30, 50, 60 are placed in parallel with a constant distance to the reference wires 40, 70 with their width formed narrower than those of the reference wires 40, 70. Therefore electric conductivity between the reference wires 40, 70 and the evaluating wires 30, 50, 60 can be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor evaluation chip, and more particularly to a resin-encapsulated semiconductor device manufactured by encapsulating a semiconductor chip with a resin. In order to evaluate the movement of wiring, that is, wiring slide, and the occurrence of defects such as short circuit and disconnection of wiring accompanying it, and performance degradation in advance using a performance evaluation chip manufactured in the same manner as a semiconductor chip to be a product. The present invention relates to a performance evaluation chip to be used.

[0002]

2. Description of the Related Art In recent years, resin-encapsulated semiconductor devices have become larger and larger due to the large capacity, high functionality, and high integration of elements.
The package itself tends to become smaller and smaller. Along with this, the problem due to the thermal stress of the semiconductor device has been greatly highlighted.

The problem due to the thermal stress of the semiconductor device occurs due to the difference in the thermal characteristics such as the thermal expansion coefficient and the thermal conductivity of the silicon chip, the lead frame, the sealing resin and the like which form the semiconductor device, that is, the semiconductor package. Such failure modes include package cracks, chip cracks, gold wire breaks, aluminum slides, passivation cracks and the like.

Among them, the aluminum slide means that the aluminum wiring formed on the surface of the semiconductor chip is moved or deformed by receiving a force from the sealing resin based on the difference in thermal deformation amount between the sealing resin and the semiconductor chip. If the aluminum wiring moves or deforms, adjacent aluminum wiring may cause a short circuit between the aluminum wiring, the aluminum wiring may be broken, or the electrical performance of the aluminum wiring may be adversely affected. Will be done.

Therefore, in order to evaluate the aluminum slidability of the semiconductor device, various environmental tests are performed on the semiconductor device. Specifically, there are temperature cycle test and thermal shock test, etc., and low temperature side (-65 ° C) and high temperature side (+
By repeatedly changing the environment between 150 ° C.), heat stress is applied to the test sample, and the performance of the test sample after the environmental test is evaluated.

In order to evaluate the performance of the test sample, defects such as package cracks appearing in the appearance can be visually judged.
The performance of the part hidden inside the sealing resin cannot be evaluated from the outside. Therefore, conventionally, the sealing resin of the test sample is melted with fuming nitric acid or the like and opened to expose the surface of the semiconductor chip inside, and observation and evaluation are performed.

[0007]

However, when the sealing resin is unsealed to expose the surface of the semiconductor chip as described above, the semiconductor chip must be subjected to subsequent evaluation tests. There is a drawback that you cannot do it. That is, since the semiconductor chip once the sealing resin has been unsealed cannot be used for another evaluation test, the semiconductor chip for the unsealing test is different from the semiconductor chip for testing that is performed in another sealed state. It is necessary to prepare separately. Therefore, the evaluation test cannot be performed efficiently, and the test cost is high. Further, since the semiconductor chip sealing resin is made of a material having excellent chemical resistance and mechanical strength, there is also a problem that it takes a lot of time to melt the sealing resin and open it. It was

In particular, the aluminum slidability has the highest sensitivity at the corners of the outer periphery of the semiconductor chip, and is greatly affected by the presence of aluminum wiring near this corner.
In conventional evaluation test chips, aluminum wiring is manufactured without considering such differences in characteristics depending on the location. Since evaluation is performed, there is also a problem that the semiconductor device actually manufactured cannot be evaluated accurately.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a resin-encapsulated semiconductor evaluation chip as described above, which allows easy and accurate evaluation of aluminum slidability, that is, wiring slidability.

[0010]

A resin-sealed semiconductor evaluation chip according to the present invention, which solves the above-mentioned problems, is a semiconductor device in which a semiconductor chip is sealed with a resin, and has wiring slidability associated with the resin sealing. A performance evaluation chip used for evaluation, on the insulating layer formed on the surface of the chip board, orthogonal to the line connecting the center of the chip board and the outer peripheral corner, and the reference wiring and evaluation near the outer peripheral corner. Wiring is provided, the reference wiring is formed wide enough not to cause wiring sliding, and the evaluation wiring is arranged in parallel with the reference wiring at a constant interval, and is larger than the reference wiring. The width is narrow, and the electrical continuity between the reference wiring and the evaluation wiring can be measured.

As the basic structure of the resin-encapsulated semiconductor evaluation chip, an ordinary semiconductor chip structure similar to that of a known evaluation chip or the like is adopted in accordance with the structure of the semiconductor device and the chip to be manufactured. The chip substrate is made of a semiconductor material such as silicon and has a polygonal shape such as a square or a rectangle. An insulating layer made of a silicon thermal oxide film or the like is formed on the surface of the chip substrate, and conductor wiring necessary for performance evaluation is formed on the insulating layer. Aluminum wires are usually used for the conductor wires, but wires made of other conductors may be used. The structure of the insulating layer and the conductor wiring formed on the chip substrate is set according to the structure of the semiconductor chip to be evaluated.

In the present invention, two kinds of wirings, that is, a reference wiring and an evaluation wiring, are provided as conductor wirings. Both the reference wiring and the evaluation wiring are arranged in the vicinity of the outer peripheral corner, orthogonal to the line connecting the center of the chip substrate and the outer peripheral corner. For example,
When the chip substrate has a rectangular shape, the reference wiring and the evaluation wiring are formed in any of the four corners or in all the corners. It should be noted that the term "orthogonal" means that the angle formed by the line connecting the center of the chip substrate and the outer peripheral corner and the wiring is 90 °, but this angle may be regarded as substantially orthogonal even if the angle is not exactly 90 °. It only needs to be within a certain angle range. The vicinity of the outer peripheral corner may be a position closer to the outer peripheral corner, which is more sensitive to the wiring slide than the center of the chip substrate.

The reference wiring is formed in a sufficiently wide width so as not to cause so-called wiring sliding, which is deformed or moved by thermal stress even if various environmental changes occur in the state where the resin is sealed. To be done. Specifically, depending on the structure of the semiconductor chip to be evaluated, the width is set wide enough to determine that wiring sliding does not occur based on the result of a normal evaluation test. As the conductor material and the manufacturing means for forming the reference wiring, the conductor material and wiring forming means for wiring in a normal semiconductor chip can be applied.

The evaluation wiring is arranged in parallel with the reference wiring at a constant interval and is formed narrower than the reference wiring. As the conductor material and the manufacturing means constituting the evaluation wiring, the same material and means as the wiring for the semiconductor chip to be evaluated can be adopted. Aluminum wiring is usually used for the wiring for the semiconductor chip, but conductor wiring other than that may be used. The evaluation wiring is arranged on the side closer to the reference wiring when the wiring slide due to thermal stress occurs. Normally, the evaluation wiring may be arranged on the outer peripheral side of the substrate chip with respect to the reference wiring. If the width of the evaluation wiring is set to, for example, the width of the wiring used for the semiconductor device product that is actually manufactured, it is possible to evaluate whether or not the wiring slide problem will occur when this wiring width is applied. In addition, the width of the evaluation wiring may be set according to the width of the wiring to be evaluated. The distance between the evaluation wiring and the reference wiring is set so that the evaluation wiring electrically contacts the reference wiring when the evaluation wiring slides.
The interval between the evaluation wiring and the reference wiring is changed depending on conditions such as how much wiring sliding of the evaluation wiring is allowed, or how much the detection accuracy of the wiring slide is set. If the height of the evaluation wiring is increased and the so-called aspect ratio (height / cross-section width) is increased, the evaluation wiring reacts sensitively to thermal stress, so that the occurrence of wiring slide becomes more sensitive. It becomes possible to detect.

A plurality of evaluation wirings having different line widths or different distances from the reference wiring can be provided. A plurality of evaluation wirings may be provided for one reference wiring, or a plurality of pairs of a pair of reference wirings and evaluation wirings may be provided. For example, if multiple evaluation wirings with different line widths are provided, it is possible to quantify the relationship between the line width and the occurrence of wiring slides by evaluating up to which line width the evaluation wirings cause wiring sliding. You can know it. If multiple evaluation wirings with the same line width and different distances from the reference wiring are provided, it is possible to know up to which distance the evaluation wirings make contact with the reference wiring due to the wiring slide. It is also possible to quantitatively know the size of the wiring slide.

The reference wiring and the evaluation wiring are provided with a terminal portion for connecting a bonding wire or the like to an external wiring such as a lead frame. The specific structure of the terminal portion may be the same as that of the terminal portion for wiring connection in a normal semiconductor chip or semiconductor device. The terminal part is
Connected to external wiring such as a lead frame of a semiconductor device, the wiring is drawn to the outside of the semiconductor device, and electrical conduction between a pair of reference wiring and evaluation wiring is provided outside the semiconductor device. Make it possible to detect at the terminal. That is, when the evaluation chip is sealed with resin,
It is sufficient that a part of the wiring electrically connected to the reference wiring and the evaluation wiring is exposed to the outside of the sealing resin. As a structure for pulling out the wiring from the reference wiring and the evaluation wiring to the outside, the wiring structure in a normal semiconductor device can be freely adopted. However, in this wiring structure, it is necessary to prevent problems and defects when an environmental test is performed on the evaluation chip so that the electrical continuity between the reference wiring and the evaluation wiring can be accurately evaluated. Needed for.

If various structures necessary for other evaluation tests are formed on the evaluation chip in addition to the above-described reference wiring and evaluation wiring, one evaluation chip can be used for wiring slidability and other characteristics. It can also be used for evaluation tests.

[0018]

With the evaluation chip on which two types of wirings, the reference wiring and the evaluation wiring, have been formed, the evaluation chip is sealed with a resin to produce an evaluation semiconductor device. If you use it for environmental tests,
Thermal stress acts due to the relative thermal deformation difference between the evaluation chip and the resin.

Since the reference wiring and the evaluation wiring are arranged in the vicinity of the outer peripheral corner orthogonal to the line connecting the center of the chip substrate and the outer peripheral corner, they are most sensitive to the thermal stress. That is, the chip substrate and the resin expand and contract in the radial direction from the center to the outer periphery. Therefore, the thermal stress also acts on the radiation from the center toward the outer periphery. Moreover, the closer to the outer periphery, the larger the relative movement amount of the sealing resin and the chip substrate due to the thermal stress. Therefore, if the wiring is placed near the outer peripheral corner orthogonal to the line connecting the center of the chip substrate and the outer peripheral corner, the wiring is moved or deformed due to the thermal stress in the direction orthogonal to this wiring direction. It is easy to do.

Since the reference wiring is formed wide enough so as not to cause wiring sliding, it does not move or deform even when the thermal stress acts. However, since the evaluation wiring is formed to have a width narrower than that of the reference wiring, when the thermal stress acts, the evaluation wiring moves or deforms, which causes so-called wiring sliding. Since the evaluation wiring is arranged in parallel with the reference wiring at a constant interval, when the evaluation wiring moves or deforms, the whole or part of the evaluation wiring contacts the reference wiring and short-circuits. It will be.

A semiconductor device for evaluation in which the evaluation chip is sealed with resin so that the reference wiring and the evaluation wiring are electrically connected to each other by connecting the wiring of the lead frame to each other. If it can be detected from the outside, the contact between the reference wiring and the evaluation wiring due to the wiring sliding of the evaluation wiring can be known as a change in the electrical conduction state. That is, the wiring slidability of the evaluation semiconductor device can be evaluated.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show the structure of the evaluation chip 1. In the evaluation chip 1, an insulating layer 20 made of a thermal oxide film of silicon or the like is formed on the surface of a rectangular substrate chip 10 made of silicon or the like, and a reference wiring 40 made of aluminum wiring is formed on the insulating layer 20. 70
And the evaluation wirings 30, 50, 60 are formed.

Each of the wirings 30 to 70 is formed in a direction orthogonal to the line S connecting the center C of the substrate chip 10 and the corner T. That is, the angle θ between the wirings 30 to 70 and the line S is set to 90 °. The evaluation wiring 30, the reference wiring 40, the evaluation wirings 50 and 60, and the reference wiring 70 are arranged in parallel in this order from the corner T side of the substrate chip 10. The evaluation wirings 50 and 60 are provided on the left and right along one reference wiring 70. At both ends or one end of each of the wirings 30 to 70, a rectangular terminal portion 32 for connecting to an external wiring,
42, 52, 62, 72 are provided. Terminal part 32
Has a structure capable of wiring connection by wire bonding or the like.

The evaluation wirings 30, 50 and 60 are set to the width of the wirings to be evaluated, while the reference wirings 40 and 7 are set.
The width 0 is set to be much wider than the evaluation wirings 30, 50, and 60. Between the reference wiring 40 and the evaluation wiring 30,
And, between the reference wiring 70 and the evaluation wirings 50 and 60,
There is a slight gap. The distance between the evaluation wiring 50 and the reference wiring 70 is set smaller than the distance between the evaluation wiring 60 and the reference wiring 70.

Evaluation chip 1 having the above structure
Using, for example, a semiconductor device for evaluation as shown in FIG. 3 is manufactured. That is, the evaluation chip 1 is placed on the lead frame 2 and fixed by die bonding or the like.
In addition, each terminal portion 3 of each wiring 30 to 70 of the evaluation chip 1
2 to 72 and wiring of the lead frame 2 (not shown),
The wires 3 are wire-bonded with an Au wire 3 or the like for electrical connection. In this state, most of the evaluation chip 1 and the lead frame 2 are sealed with a sealing resin 4 such as an epoxy resin. The end portion of the lead frame 2 extends to the outside of the sealing resin 4, and if an external wiring or circuit is connected to the end portion of the lead frame 2, the evaluation wirings 30 ... And the reference wirings 40, 70 are electrically connected, Alternatively, the continuity between the evaluation wirings 30 ... And the reference wirings 40, 70 can be measured.

The semiconductor device thus manufactured is
Used for thermal shock test and temperature cycle test. When the encapsulating resin 4 and the evaluation chip 1 expand and contract due to heat, the amounts of thermal deformation of the two differ due to the difference in thermal expansion coefficient between the two, so that they relatively move or deform. Then, due to this thermal deformation or thermal stress, the evaluation wirings 30 ... Are moved or deformed toward the reference wirings 40 and 70.

For the semiconductor device which has been tested for a fixed cycle, the electrical continuity between the reference wirings 40, 70 and the evaluation wirings 30 ... Check by connecting the electrode to. If the evaluation wirings 30 are not in contact with the reference wirings 40 and 70, the evaluation wirings 30 are electrically cut off from the reference wirings 40 and 70. .. are in contact with the reference wirings 40, 70, the reference wirings 40, 70 and the evaluation wirings 30 are electrically connected. That is, the occurrence of wiring slide in the evaluation wirings 30 can be detected by the electrical conduction state between the reference wirings 40 and 70 and the evaluation wirings 30 without opening the sealing resin 4 of the semiconductor device. ..

In the case where the evaluation wirings 50 and 60 having different intervals from the reference wiring 70 are provided, for example, only the evaluation wirings 50 having a narrow distance are electrically connected to the reference wiring 70 and the distance between the evaluation wirings 50 is reduced. If the wide evaluation wiring 60 is not electrically connected to the reference wiring 70, it can be understood that the amount of wiring slide is a value intermediate between the distance between the evaluation wiring 50 and the reference wiring 70 and the distance between the evaluation wiring 60 and the reference wiring 70. That is, it is possible to quantitatively know the wiring slide.

Next, the embodiment shown in FIG.
This is the case where the height of 0 ... Is made higher than the height of the reference wirings 40 and 70. That is, the aspect ratio (height / cross section width) of the evaluation wirings 30 is set to be larger than that in the embodiment shown in FIG. By doing so, the evaluation wirings 30 move or deform sensitively due to the thermal deformation or thermal stress. as a result,
When wiring slide occurs, the evaluation wiring 30 ... Is the reference wiring 4
It becomes easy to contact with 0 and 70, and it becomes possible to detect the occurrence of wiring slide with higher sensitivity.

[0030]

As described above, according to the resin-sealed semiconductor evaluation chip of the present invention, the two types of wiring, that is, the reference wiring and the evaluation wiring, are provided, and the electrical conduction state between the two types of wiring is provided. Therefore, in the semiconductor device in the resin-sealed state, the movement or deformation of the evaluation wiring due to the thermal deformation difference or thermal stress generated between the sealing resin and the chip substrate, that is, the occurrence of wiring slide To
It is possible to make a reliable evaluation without opening the sealing resin for the semiconductor device.

As a result, the performance evaluation of the resin-encapsulated semiconductor device can be performed efficiently and economically, and the performance or reliability of the semiconductor device can be greatly improved.

[Brief description of drawings]

FIG. 1 is a plan view showing substantially four quarters of an evaluation chip showing an embodiment of the present invention.

FIG. 2 is a sectional view of the above.

FIG. 3 is a schematic schematic cross-sectional view of a resin-sealed semiconductor device.

FIG. 4 is a sectional view of an evaluation chip showing another embodiment.

[Explanation of symbols]

 1 Evaluation Chip 10 Chip Substrate 20 Insulating Layer 30, 50, 60 Evaluation Wiring 32, 52, 62 Terminal 40, 70 Reference Wiring 42, 72 Terminal

Claims (1)

Claims: 1. A semiconductor device in which a semiconductor chip is sealed with resin, which is a performance evaluation chip used for evaluating wiring slidability associated with resin sealing. On the insulating layer formed on the surface, a reference wiring and an evaluation wiring are provided in the vicinity of the outer peripheral corner orthogonal to the line connecting the center of the chip substrate and the outer peripheral corner, and the reference wiring is such that wiring sliding does not occur. Is formed sufficiently wide, the evaluation wiring is arranged in parallel with the reference wiring at a constant interval, and is formed narrower than the reference wiring. A resin-sealed semiconductor evaluation chip characterized by being capable of measuring electrical continuity.