NL2029560B1

NL2029560B1 - Thermal test chip

Info

Publication number: NL2029560B1
Application number: NL2029560A
Authority: NL
Inventors: qi zhang Guo; Sattari Romina; Wilhelminus Van Zeijl Hendrikus
Original assignee: Univ Delft Tech
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2023-05-26
Also published as: WO2023075598A2; WO2023075598A3

Abstract

A system comprising a thermal test chip and an encapsulation layer is disclosed. The chip comprises one or more heater elements configured to generate heat. The encapsulation layer is configured to protect the chip against moisture. Further, the chip comprises a moisture sensorthat is configured to measure moisture content in said encapsulation layer.

Description

NL33469 —Id/av

Thermal test chip

FIELD OF THE INVENTION

This disclosure relates to system comprising a thermal test chip and an encapsulation layer.

The thermal test chip comprises a moisture sensor configured to measure moisture content in the encapsulation layer, to a chip comprising a capacitor and to methods for fabricating such chips.

BACKGROUND

The rapid shrinking of semiconductor devices and increasing power densities have created challenging circumstances in semiconductor packages. Semiconductor devices are shrinking in size while they demand higher power dissipation. Thus, the power density levels in semiconductor devices are increasing. Automotive applications like self-driving cars demand a high amount of power and complexity. A high level of power density is often required to do parallel complex tasks including comprehensive vision processing, object recognition, and intelligent traffic system. These computer systems, as a substitution for the human brain, must safely be capable of always handling all driven situations autonomously. However, the computer chips are by no means designed for use in the harsh conditions of real vehicles. In such applications with extremely high power densities, reliability and lifetime of electronic devices are becoming more and more important as it directly impacts the passengers’ safety. With this in mind, it is of high significance to identify the critical reasons that cause package failure.

There is often a link between the reliability of electronic devices and their power density.

Increasing power densities necessitates in-situ reliability investigation of electronic packages to identify relevant destructive causes of package failure and guarantee the required lifetime of an electronic device. To this end, researchers have been studying the failure causes of semiconductor packaging to guarantee the future of power electronics, especially in case of device performance under harsh conditions e.q., freezing cold, summer heat, on/off performance cycling. There are a number of reasons which prevent us from doing reliability investigations on semiconductor chips: having no access to future products, a high number of samples needed, cost-effectiveness, and accelerated cycling tests needed.

As a cost-effective and flexible platform, thermal mock-up chips, or thermal test chips (TTC), have been presented recently. See for example {STATE OF THE ART TEST CHIP FOR THE

QUALIFICATION OF NON-HERMETIC MCM ENCAPSULATION, Puig et al., European Space

Components Conference, ESCCON 2002} and {Development and Fabrication of a Thin Film Thermo

Test Chip and its Integration into a Test System for Thermal interface Characterization, AboRas et al, 19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 25-27

Sept. 2013} and {JEDEC publication JESD51-4A: THERMAL TEST CHIP GUIDELINE (WIRE BOND

AND FLIP CHIP), published July 2019}. Thermal test chips include heater elements, such as microheaters, to mimic the power mapping of real power modules and, typically, on-chip temperature sensors for temperature monitoring during power cycling tests to assess the reliability of the system.

Systems comprising thermal test chips aid thermal engineers to answer critical questions relating to thermal packaging, for example under what circumstances a chip fails. The current test systems, however, leave room for improvement in terms of the failure analysis that they enable.

SUMMARY

To that end, a system comprising a thermal test chip and an encapsulation layer is disclosed. the encapsulation layer is configured to protect the thermal test chip against moisture. The chip comprises one or more heater elements configured to generate heat. Further, the chip comprises a moisture sensor that is configured to measure moisture content in said encapsulation layer.

The encapsulation layer preferably covers at least 50%, more preferably at least 75% of a surface, e.g. a top surface, of the thermal test chip. Most preferably, the encapsulation layer covers an entire surface of the thermal test chip. The encapsulation layer is typically also configured to protect the test chip from contamination and/or oxidizing.

The one or more heater elements, which may be micro-heaters and/or thin-film heaters known in the field of thermal test chips, may comprise resistive material that heats up when an electrical current flows through it. Each of the one or more heater elements may have a resistance at room temperature between 40-60 Ohm, preferably between 45-55 Ohm, more preferably between 50-55

Ohm. The one or more heater elements may be distributed across the thermal test chip. Preferably, at least 70%, preferably at least 80%, more preferably at least 82% of the chip area is dedicated to heater elements in order to maximize temperature homogeneity. The one or more heater elements may be separately controllable so that heat can be locally generated. This for example allows to generate non-uniform power mapping thus providing great flexibility in what kind of electronic circuitry and associated power cycles can be simulated by the thermal test chip. This is for example very useful for testing chips for automotive applications, because, as described in the background section, chips in automotive application are exposed to severe temperature cycling.

Advantageously, the disclosed system comprising the thermal test chip is not limited to thermal investigations, but can also measure the moisture content in the encapsulation layer by means of the moisture sensor. It is valuable to know the moisture content in the encapsulation layer because absorbed/desorbed humidity in the encapsulation layer can be a source of mechanical stress, also referred to as moisture induced stress. Such moisture induced stress can be caused by moisture in the encapsulation layer evaporating and can also cause delamination and package failure. The disclosed test chip thus enables to determine to what extent a failure of the test chip is caused by such moisture induced stress, at least enables to determine more precisely the cause of a chip failure. The moisture sensor on the chip thus enables more powerful and flexible chip investigations.

The thermal test chip may comprise semiconductor material, such as silicon, on which electronic circuitry may be formed. In any case, the thermal test chip can be fabricated by means of thin-film technology, such as physical vapor deposition techniques (PVD) and/or chemical vapor deposition techniques (CVD). In principle, any suitable material may be used as substrate, such as

SiC or GaN.

The encapsulation layer may be a homogeneous layer, which may be understood as that it consists of the same material throughout.

The thermal test chip may have been assembled using a flip-chip technology or wire bonding technique, for example.

In an embodiment, the moisture sensor is a capacitive moisture sensor. A capacitive sensor comprises a capacitor that typically comprises a first electrical conductor and a second electrical conductor spaced apart. Typically, such two electrical conductors are spaced apart by a dielectric material. In a capacitive moisture sensor, the dielectric constant of the dielectric material typically varies in dependence of the moisture content in the dielectric material. It will be understood that a change in dielectric constant causes a change of the capacitance of the capacitor, which can be measured. For this reason, the dielectric material between two conductors in a capacitive moisture sensor, or in any other capacitive sensor such as capacitive gas sensor, may also be referred to as the sensing material.

In an embodiment, the moisture sensor comprises a capacitor comprising a first electrical conductor and a second electrical conductor. In this embodiment, a part of the encapsulation layer sits between the first electrical conductor and second electrical conductor.

In this embodiment, the encapsulation layer itself may be understood to be used as sensing material. Thus, the moisture sensor can directly measure the moisture content in the encapsulation layer, which greatly improves the measurement accuracy. If for example the capacitive moisture sensor would make use of a sensing material different from the encapsulation layer, then any moisture in the encapsulation layer would first need to diffuse into the sensing material for it to become detectable. This negatively affects the response time and measurement accuracy. The sensing material and encapsulation layer may have, for example, different moisture distribution coefficients, which may distort measurements. In any case, using the encapsulation layer as sensing material provides for an easily manufacturable sensor, because the sensing material need not be deposited separately from the encapsulation layer.

The capacitor may be a so-called interdigitated capacitor, also referred to as an interdigital capacitor. Such capacitor may be planar. If the capacitor is an interdigitated capacitor, then typically the first conductor as well as the second conductor comprises so-called fingers, wherein the fingers of first conductor are interdigitated with the fingers of the second conductor.

In an embodiment, the first electrical conductor and second electrical conductor define a volume between them, said volume being substantially entirely filled with said part of the encapsulation layer.

Thus, in this embodiment, substantially no other material than the material forming the encapsulation layer sits between the first conductor and second conductor. This embodiment even further improves the measurement accuracy and response time of the moisture sensor.

In an embodiment, the moisture sensor is monolithically integrated on the thermal test chip.

As used herein, an element that is monolithically integrated on a chip may be understood as that fabrication of the element involved depositing thin films and/or other typical chip fabrication techniques, such as etching steps. Additionally or alternatively a monolithically integrated element may be understood to be part of an integrated circuit formed on a chip.

In an embodiment, the thermal test chip comprises one or more temperature sensors. This embodiment allows even more accurate chip failure analysis, because the one or more temperature sensors allow to measure the actual chip temperature, especially on the chip surface, during for example power cycling tests for reliability assessments in a semiconductor package.

Each of the one or more temperature sensors preferably has a linear and stable performance.

In an example, each of the one or more temperature sensors has a sensitivity of 10-20 Ohm/degrees

Celsius, preferably 13-19 Ohm/degrees Celsius.

In an embodiment, the thermal test chip comprises one or more stress sensors configured to measure mechanical stress. This embodiment allows even more accurate chip failure analysis. The one or more stress sensors may be configured to measure the mechanical stress in flip-chip solder bumps, in the encapsulation layer, and/or the mechanical stress that arises on the chip surface.

The multilayer nature of semiconductor packages causes different thermal expansions within the package. This mismatch in thermal expansion coefficients directly affects die surface tensions and could lead to delamination and package failure. Therefore, it is very useful to monitor the induced surface tensions.

The one or more stress sensors may comprise a serpentine resistor, such as a low/medium doped implanted serpentine resistor, and/or may comprise a Van der Pauw (VDP) stress sensor, which are known in the art.

Preferably, the thermal test chip comprises a first stress sensor and a second stress sensor, wherein the first stress sensor is configured to measure the so-called normal mechanical stress — caused by a force that at least partially acts perpendicularly (or “normal”) to the chip surface, e.g. in X and/or Y and/or Z crystallographic directions, and the second stress sensor is configured to measure shear mechanical stress caused by a force acting parallel to the chip surface. The stress sensors may be planar stress sensors or three-dimensional (3D) stress sensors by using different substrates with different crystal orientations.

The thermal test chip is typically electrically connected to external circuitry, such as a printed circuit board (PCB), by means of solder bumps (in case of a flip chip configuration) or wire bonds (in case of wire bond configuration). Preferably the one or more stress sensors are positioned at such solder bumps (if present), because this allows to accurately monitor whether cracks are formed close by solder bumps.

Preferably, the thermal test chip comprises the moisture sensor and the one or more stress sensors and the one or more temperature sensors. This allows to precisely identify the causes of chip failures during testing.

In an embodiment, the one or more heater elements are monolithically integrated on the thermal test chip, and/or the one or more temperature sensors are monolithically integrated on the thermal test chip, and/or, the one or more stress sensors are monolithically integrated on the thermal test chip.

This embodiment enables a compact chip design and also enables large scale production of the test chips, e.g. using thin film technology.

In an embodiment, the encapsulation layer comprises an epoxy resin and/or a polyester resin and/or a polyurethane resin and/or a silicone resin.

The encapsulation layer may essentially consist of and/or consist of an epoxy resin. The encapsulation layer may essentially consist of and/or consist of an polyester resin. The encapsulation 5 layer may essentially consist of and/or consist of an polyurethane resin. The encapsulation layer may essentially consist of and/or consist of a silicone resin.

Each epoxy molded compound (EMC) comprises an epoxy resin. Thus, the encapsulation layer may also comprise, or essentially consists of and/or consists of, an epoxy molded compound. Epoxy molded compounds are extensively used to protect delicate electronic structures on chips, for example against moisture.

One aspect of this disclosure relates to a method for fabricating a system comprising a thermal test chip and an encapsulation layer. This method comprises fabricating one or more heater elements on the chip and fabricating a capacitive moisture sensor on the chip, wherein the capacitive moisture sensor comprises a capacitor comprising a first electrical conductor and a second electrical conductor.

The method further comprising depositing an encapsulation layer onto the chip such that the encapsulation layer protects the chip against moisture and such that part of the encapsulation layer sits between the first electrical conductor and second electrical conductor.

This method allows to fabricate thermal chips with a capacitive moisture sensor having as sensing material the encapsulation material of the encapsulation layer.

One aspect of this disclosure relates to a chip comprising a capacitor. The capacitor comprises a first electrical conductor supported by a plurality of electrically insulating support structures. Said plurality of electrically insulating support structures are separated from each other by one or more intermediate spaces and the first electrical conductor bridges the intermediate spaces. The capacitor further comprises a second electrical conductor.

This capacitor is particularly advantageous in that at least some parts of the first electrical conductor do not have an electrically insulating support layer directly below it, in the intermediate spaces, meaning that that there is room for other material in the intermediate spaces, such as for the dielectric material that is used in the capacitor to separate the first and second electrical conductor. It should be appreciated that a shielding metal layer may be present below the electrically insulating layer. Herewith, effectively, an undesired capacitor may be formed by the first/second electrical conductor and the shielding metal layer which gives rise to a parasitic capacitance. Such parasitic capacitance is preferably kept as small as possible because it will cause the capacitor to have a different capacitance than intended. It will be understood that the parasitic capacitance is dependent on the material that sits between the first electrical conductor and the shielding metal layer. If some dielectric material having a smaller dielectric constant than the material forming the support structures, is present below at least parts of the first/second electrical conductor, instead of the electrically insulating support structures, then the parasitic capacitance is smaller. Typically, an epoxy resin has a smaller dielectric constant than a PECVD oxide layer. Hence, this capacitor allows for a very small capacitor having very accurate capacitance values, i.e. having capacitance values as was intended by the design.

In an embodiment, the second electrical conductor is supported by a second plurality of electrically insulating support structures, wherein said second plurality of electrically insulating support structures are separated from each other by second one or more intermediate spaces and the second electrical conductor bridges the second intermediate spaces.

Preferably, each support structure of the plurality of electrically insulating support structures consists of the same material, such as an oxide. Likewise, each support structure of the second plurality of support structures consists of the same material. Typically, all support structures, of both the plurality of support structures and of the second plurality of support structures, consist of the same material. The plurality of electrically insulating support structures as well as the second plurality of electrically insulating support structures may have been obtained by etching away parts of an electrically insulating layer. Remaining parts of the electrically insulating layer may then form the plurality of electrically insulating support structures and/or second plurality of support structures. The electrically insulating layer may have been obtained by depositing, e.g. using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD) process, electrically insulating material onto a substrate, for example on a metal surface of such substrate, such as on a titanium surface of such substrate. Such metal layer beneath the electrically insulating layer, and thus below the electrically insulating support structures in the final capacitor form a bottom shielding electrode. Such shielding layer is deposited under the interdigital fingers and increases the sensor sensitivity.

The support structures supporting an electrical conductor that are described herein may be understood to be configured to keep an electrical conductor at a fixed position. Without such support structures, an electrical conductor may namely sink downwards due to gravity pulling on the electrical conductor. Such structure deformation may also be referred to as the buckling effect. The buckling effect is especially prone to happen when parts of the electrically insulating layer are removed. At this step there is no encapsulation layer yet. Once buckling has occurred, it cannot be remedied by coating the chip with an encapsulation layer because the buckling and deformation have already occurred.

In an embodiment, as viewed from a top view, each electrically insulating support structure supporting an electrical conductor is completely covered by the supported electrical conductor. Thus, if the electrical conductor is for example a metal trace having a certain width, then any electrically insulating support structure will have a width smaller than said certain width.

As used herein, electrically insulating may be understood as having an electrical conductivity lower than 1e-3 ohm'm’', preferably lower than 1e-5 ohm™m*, more preferably lower than 1e-10 ohm mt, for example. As used herein, electrically conductive may be understood as having an electrical conductivity higher than 1e2 ohm™'m*, preferably higher than 1e3 ohm'm™', more preferably higher than 1e4 ohm™*m, for example.

As used herein, when elements are said to be separate, this may be understood as that these elements are not in physical contact with each other.

In an embodiment, dielectric material, e.g. sensing material in case the capacitor is used as a capacitive sensor, is present below the parts of the first and/or second conductor that are not supported by an electrically insulating support structure, e.g. in the intermediate spaces.

In an embodiment, the plurality of electrically insulating support structures, as viewed from a top view, are below the first electrical conductor. In this embodiment, each position, e.g. as viewed from a top view, on the first electrical conductor has a distance from an edge of the first electrical conductor, preferably a side edge, that is nearest to the position in question, wherein the distance is either smaller than or equal to a threshold distance or larger than the threshold distance. The positions on the first electrical conductor of which the distance is larger than the threshold distance define a plurality of areas and the positions on the first electrical conductor of which the distance is smaller than or equal to the threshold distance define second one or more areas. The plurality of areas are separated from each other by one or more of the second one or more areas. The plurality of electrically insulating support structures are positioned, as viewed from the top view, below the plurality of areas. Such embodiment of the capacitor is relatively easy to fabricate, because the support structures can be obtained with a single wet etching step as will be described in further detail with reference to the figures.

Optionally, the second plurality of electrically insulating support structures are below the second electrical conductor. Then, preferably, each position, e.g. as viewed from a top view, on the second electrical conductor has a distance from an edge, preferably a side edge, that is nearest to the position in question, wherein the distance is either smaller than or equal to the threshold distance or larger than the threshold distance. The positions on the second electrical conductor of which the distance is larger than the threshold distance define a third plurality of areas and the positions on the second electrical conductor of which the distance is smaller than or equal to the threshold distance from fourth one or more areas. The third plurality of areas are separated from each other by one or more of the fourth one or more areas. In such case, preferably, the second plurality of electrically insulating support structures are positioned, as viewed from the top view, below the third plurality of areas.

The chip may be substantially planar. Unless stated otherwise, the side of the chip on which the capacitor and/or moisture sensor is/are formed may be understood to be the top side. A top view, referred to herein may be understood to be a view on the top side from a point above the top side.

The first electrical conductor may at least partially be formed as a conductive path, wherein a width of the path varies along its length and wherein the path comprises one or more parts where the width of the path is less than twice the above mentioned threshold distance and wherein the path comprises one or more parts where the width of the path is larger than twice the above mentioned threshold distance.

Likewise, the second electrical conductor may at least partially be formed as a second conductive path, wherein a width of the second path varies along its length and wherein the second path comprises one or more parts where the width of the second path is less than twice the above mentioned threshold distance and wherein the second path comprises one or more parts where the width of the path is larger than twice the above mentioned threshold distance.

In an embodiment of the chip comprising the capacitor, a distance, for example as viewed from a top view, between the first electrical conductor and second electrical conductor is substantially the same throughout the capacitor.

The first electrical conductor and second electrical conductor may define a path between them, for example when the capacitive sensor is an interdigitated capacitive sensor. In such case, the path may have substantially the same width throughout.

One aspect of this disclosure relates to a chip comprising a capacitive sensor, wherein the capacitive sensor comprises any of the capacitors described herein that comprises a first electrical conductor supported by a plurality of electrically insulating support structures, wherein the plurality of electrically insulating support structures are separated from each other by one or more intermediate space and wherein the first electrical conductor bridges the one or more intermediate spaces, and that comprises a second electrical conductor. Preferably, the second electrical conductor is supported by a second plurality of electrically insulating support structures and said second plurality of electrically insulating support structures are separated from each other. This capacitive sensor may be a moisture sensor.

This capacitive sensor is particularly advantageous in that at least some parts of the first electrical conductor do not have an electrically insulating support layer directly below it, meaning that that there is room below these parts, in the intermediate spaces, for other material, such as for the sensing material of the capacitive sensor. If such sensing material is present below at least parts of the first electrical conductor, instead of the first electrical conductor being supported throughout by the electrically insulating support structures, then the electrical field generated by the first and second electrical conductor will occupy more sensing material. As a consequence, changes in the dielectric constant of the sensing material, for example because a to be measured substance, such as moisture or gas, has entered into the sensing material, will cause greater changes in the capacity of the capacitor. In other words, the capacitive sensor will become more sensitive.

It should be appreciated that any of the capacitors described herein can be used as the capacitive moisture sensor on the thermal test chip described herein.

One aspect of this disclosure relates to a method for fabricating a chip comprising a capacitor.

The method comprises fabricating a first electrical conductor and a second electrical conductor onto an electrically insulating layer. Each position, e.g. as viewed from a top view, on the first electrical conductor has a distance from an edge, preferably a side edge, that is nearest to the position in question, wherein the distance is either smaller than or equal to a threshold distance or larger than the threshold distance. The positions on the first electrical conductor of which the distance is larger than the threshold distance define a plurality of areas and the positions on the first electrical conductor of which the distance is smaller than or equal to the threshold distance define second one or more areas.

Further, said plurality of areas are separated from each other by one or more of the second one or more areas. The method further comprises etching away parts of the electrically insulating layer such that the electrically insulating layer is removed, e.g. completely removed, from beneath the one or more second areas yet at least partially remains below said plurality of areas so that the remaining parts of the electrically insulating layer below the plurality of areas form a plurality of electrically insulating supports structures. Said plurality of electrically insulating support structures are separated from each other by one or more intermediate spaces and the first electrical conductor bridges the one or more intermediate spaces.

Preferably, each position, e.g. as viewed from a top view, on the second electrical conductor has a distance from an edge, preferably a side edge, that is nearest to the position in question, wherein the distance is either smaller than or equal to a threshold distance or larger than the threshold distance. The positions on the second electrical conductor of which the distance is larger than the threshold distance define a third plurality of areas and the positions on the second electrical conductor of which the distance is smaller than or equal to the threshold distance from one or more fourth areas.

Further, said third plurality of areas are separated from each other by one or more of the one or more fourth areas. The method further comprises etching away parts of the electrically insulating layer such that the electrically insulating layer is removed, e.g. completely removed, from beneath the one or more fourth areas yet at least partially remains below said third plurality of areas so that the remaining parts of the electrically insulating layer below the third plurality of areas form a plurality of electrically insulating supports structures. Said plurality of electrically insulating support structures are separated from each other by one or more second intermediate spaces and the second electrical conductor bridges the one or more second intermediate spaces.

Fabricating the first and second electrical conductor on the chip may comprise fabricating conductive traces having a varying width along their lengths on the chip as described above.

The method may further comprise filling the one or more intermediate spaces and/or the second one or more intermediate space with a dielectric material, e.g. by depositing the dielectric material onto the chip after etching away parts of the electrically insulating layer.

One aspect of this disclosure relates to a chip obtainable by performing any of the methods for fabricating a chip described herein.

Elements and aspects discussed for or in relation with a particular embodiment may be suitably combined with elements and aspects of other embodiments, unless explicitly stated otherwise.

Embodiments of the present invention will be further illustrated with reference to the attached drawings, which schematically will show embodiments according to the invention. It will be understood that the present invention is not in any way restricted to these specific embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the invention will be explained in greater detail by reference to exemplary embodiments shown in the drawings, in which:

FIG. 1 shows a test package in flip chip configuration comprising a system according to an embodiment;

FIG. 2 shows a test package in wire bond configuration comprising a system according to an embodiment;

FIG. 3A illustrates a thermal test chip according to an embodiment fabricated using flip chip technology;

FIG. 3B illustrates a thermal test chip according to an embodiment suitable for wire bonding technology;

FIG. 4A illustrates a parallel plate capacitive moisture sensor known in the art;

FIG. 4B illustrates an IDE (interdigital electrodes) capacitive moisture sensor according to an embodiment;

FIG. 5 illustrates how a capacitive sensor according to an embodiment that may be used as moisture sensor on a thermal test chip may be fabricated;

FIG. 6 illustrates a method for fabricating a chip comprising a capacitor according to an embodiment

DETAILED DESCRIPTION OF THE DRAWINGS

In the figures, identical reference number indicate identical or similar elements. Further, the figure shows the x, y , z-directions. As used herein, the +z-direction may be referred to as upwards, the -z direction as downwards, and directions in the xy-plane as lateral directions. The top side or top surface of the chip 12 may be understood to be the side or surface facing upwards and the downside of the chip may be understood to be the side facing downwards.

Figure 1 shows test package comprising a system disclosed herein, thus comprising a thermal test chip 12 and an encapsulation layer 30. The encapsulation layer 30 in figure 1 covers the top surface completely. In this example, the configuration has been assembled using flip-chip technology.

Solder bumps 10 connect the thermal test chip 12 to an interposer 8. The interposer may function as an electrical routing between one connection to another. The purpose of an interposer may be to reroute or spread a connection to a wider pitch. It should be appreciated that figure 1 is only an example kind of a packaging, in particular an example in which the thermal test chip 12 is connected to an interposer 8 using solder bumps. The person skilled in the field of thermal test chips will understand that other packaging configuration are also possible. For example, the thermal test chip 12 could also be assembled without the interposer 8 directly connected to PCB 2. Also, wire-bonding technology could be used without using solder bumps, for example quad-flat no-leads (QFN) packaging.

In the embodiment of figure 1, solder balls 4 connect the interposer 8 to the PCB (printed circuit board) 2. Via the PCB 2 the different elements on the thermal test chip can be controlled, tested and the PCB can process output from elements of the chip. To illustrate, via the PCB 2 one or more heater elements can be controlled by causing an electrical current flow through the heater elements. Also, via the PCB, voltages and/or currents and/or capacitances relating to any of the sensors described herein can be measured.

Between solder bumps 10 underfill material is preferably present, which may or may not be the same material as the encapsulation layer. Between solder bumps 4, underfill material 6 is preferably present. This underfill material 8 may or may not be the same as the underfill material between solder bumps 10. Also, this underfill material may or may not be the same as the material forming the encapsulation layer 30.

A thermal interface material (TIM) 16 sits between the chip 12 and a heat sink 18 to fill air gaps in between and provide better thermal conductivity of the heat removal path.

Figure 1B is a simplified top view which shows the thermal test chip 12 and the PCB 2 as a general concept in flip-chip packaging format.

Figure 2 also illustrates a test package comprising a system as disclosed herein, thus comprising a thermal test chip 12 and an encapsulation layer 30. In this embodiment, the encapsulation layer covers the entire top surface of the test chip 12. This configuration is based on wire bonding assembly technology. Herein, the test chip 12 is attached by a die attaching material 13 to a lead frame 15. Further, wire bonds 60 electrically connect conductors on the lead frame 15 to connectors 62 on the test chip 12. Figure 2 also schematically indicates (monolithically integrated) elements on the chip, such as heater elements, e.g. microheaters, moisture sensors 64, temperature sensors 66 and stress sensors 68. Encapsulation layer 30 is provided in order to protect the chip 12 and the package against moisture.

Figure 3A illustrates a thermal test chip 12 as viewed from a top view according to an embodiment. The depicted thermal test chip 12 comprises six heater elements, one of which is indicated by 70 having two electrical connectors 72a and 72b in order to cause an electrical current through the heater element 70 and two electrical connectors 71a and 71b for measuring the voltage across the heater element. The additional connectors 71a and 71b allow to accurately measure the voltage across the heater element. Since no current flows through connectors 71a and 71b, the voltage measurements do not suffer from probing resistance. The other six heater elements (the other six light grey areas in figure 3A) are the same and are not indicated for clarity reasons. Further, the test chip 12 comprises two stress sensors 68a and 68b. Further, the chip 12 comprises three temperature sensors, RTD 66a, RTD 66b and RTD 66c¢. The solder bumps 10 (under bump metallization solder bumps) are daisy chained by means of conductive traces 74. As known in the art, such daisy chains allow to study why failures occur in an economical way.

When testing a test chip having daisy chain circuits, it may fail in the sense that a crack is formed in a solder bump. In such case, the resistance of the daisy chain circuit increases. The daisy chain circuit may even go from a short to an open circuit. Once such open circuit is detected, the cause of the failure may be analyzed. In this analysis, it is very valuable to know the moisture content and/or temperature and/or stress on the chip at the time of the failure.

The chip that is depicted in figure 3A does not comprise a moisture sensor.

The thermal test chips disclosed herein preferably meet several requirements including: “The chip size preferably closely approximates the chip being simulated. “The chip preferably has a large heating area relative to chip size (JEDEC standards specify a minimum of 85%). «Preferably, the heater elements are configured to cause a uniform temperature profile across the heating area with the ability to simulate hotspots in specific areas.

+Preferably the test chip allows to manipulate and measure different temperature profiles using standard lab equipment.

Figure 3B illustrates a test chip 12 according to an embodiment, in which the test chip is configured to be connected to a PCB using wirebond technology. Herein, the temparature sensors, heater elements, stress sensors are the same and at the same position as in the embodiment of figure 1A. The embodiment of figure 3B comprises eight moisture sensors 64a-64h as described herein.

When testing a wirebond test chip, failure of the chip, e.g. after or during temperature cycling, may be detected by detecting an increased temperature somewhere on the chip. Such increased temperature may namely be indicative of a crack being formed somewhere on an interface which increases the thermal resistivity, which hampers heat removal from the chip. This causes the chip to heat up.

Figure 4A illustrates a parallel plate capacitive moisture sensor known in the art. A first electrical conductor 32 and second electrical conductor 34 are separated by some dielectric material 80.

Further, an electrically insulating layer 22 separates the first conductor 32 from a substrate 26.

Upon moisture entering into the dielectric material 80, which in this context may be referred to as the sensing material, the capacitance of the capacitor formed by the first 32 and second 34 conductor also changes. Based on this change in capacitance, the moisture content may be measured.

The second electrical conductor 34 comprises holes so that any moisture from the environment can diffuse into the dielectric material 80 more easily. The holes herewith increase the response time of the moisture sensor. If moisture is present, it will diffuse faster into dielectric material 80 which will cause a faster change of the capacitance.

Figure 4B illustrates an embodiment of a capacitive moisture sensor according to an embodiment. The depicted moisture sensor is an IDE (interdigital electrodes) capacitive moisture sensor. The first 32 and second 34 conductors are deposited on a substrate 26 (for clarity, insulating layer 22 is not shown). The conductors have interdigitated fingers and form a capacitor. The capacitor is covered by encapsulation layer 30, which is preferably an epoxy molded compound, which also sits between the fingers of the electrical conductors. Thus, effectively, the epoxy molded compound is used as sensing material in this moisture sensor. This is beneficial as any moisture that is present in the encapsulation layer will directly cause a change of the capacitance of the capacitor. Hence this sensor has a very fast response time.

Figure 5A illustrates how a capacitive sensor according to an embodiment may be fabricated that may be used as moisture sensor on a thermal test chip. In particular, figure 5A shows four different stages |, Il, lll, IV during the fabrication process.

At stage |, four different layers 20, 22, and 24 and 25 have been deposited onto a substrate 26.

It should be appreciated that any stress sensor described herein may be implanted in substrate 26 using methods known in the art.

Layer 25 may be an insulation layer such as silicon oxide and may have been formed by

PECVD (plasma enhanced chemical vapor deposition) or thermal oxidation.

Then, a conductive metal layer 24, e.g. a titanium layer, may have been deposited onto layer 25. In this metal layer 24 the heating elements and RTDs (temperature sensors) may be formed (not shown). Such heater elements, temperature sensors and stress sensors may be formed using methods known in the art. The metal layer 24 may function as a shielding layer for the to-be-fabricated capacitive moisture sensor. If Ti is used as metal layer 24 and if this layer is going to be exposed to

BHF during a wet etching insulation layer (see below) then it may be beneficial to add a thin layer of

TiN (not shown) on top of Ti as a barrier layer for Ti against being etched by BHF. Instead of TiN, an additional layer of aluminum layer may also be used to protect the titanium layer against being etched by BHF.

Thereafter an electrically insulating layer 22, e.g. a PECVD oxide layer, may have been deposited onto the conductive metal layer 24. Thereafter, again an electrically conductive layer 20 may have been deposited onto the electrically insulating layer 22. The electrically conductive layer 20 is for example a sputtered aluminum layer.

Thereafter, fabricating the capacitive sensor may comprise depositing a layer of photoresist (PR) material 28 which can be used for patterning the electrically conductive layer 20. This layer 28 is for example a UV sensitive layer. In photolithography process light is used to transfer a geometric pattern from a photomask to a photoresist 28 on the substrate. A photomask may be used that includes the geometric design of the layer to expose the photoresist. In case of positive photoresist, the photosensitive material is degraded by light and the developer (a chemical material) will dissolve away the regions that were exposed to light. In case of negative photoresist, the photosensitive material is strengthened by light and the developer will dissolve away only the regions that were not exposed to light, leaving behind a coating in areas where the mask was not placed. After development of the photoresist material, those areas which are covered by photoresist will be protected from etching. The etching process could for example be a wet etching process (using a chemical solvent) or a dry etching process (using ion bombardments for example). In both cases photoresist-covered areas will stay there and those unprotected area will be etched away. Such etching may be performed in order to form the first electrical conductor 32 and second electrical conductor 34, if present, of the capacitive moisture sensor. In particular, the etching of the conductive layer 20 may be used to form one or more conductive paths on the chip. Also see figure 5C which shows a top view of the moisture sensor and clearly shows the first electrical conductor 32 and second electrical conductor 34. The side view that is presented (four times) in figure 5A shows a cross section along line A-A indicated in figure 5C and figure 5B shows a cross section along line B-B indicated in figure 5C. Etching of the conductive layer 20 may be performed by dry etching, e.g. ion bombarding, the conductive layer.

After the etching of the conductive layer 20, at least part of the electrically insulating layer 22 may be removed in a separate step in order to arrive at the depicted stage III. Preferably, at least part of the electrically insulating layer 22 is removed using a wet etchant. As etchant, BHF 7:1 (buffered hydrofluoric acid) may be used at 25 degree Celsius to etch silicon oxide. The etch duration is dependent on the thickness and type of the oxide insulating layer (for example PECVD, LPCVD, or thermal oxide). Some experimental trial and errors may be required to, given a certain configuration,

find the appropriate etching time in order to arrive at a structure as desired, for example as depicted in stage Ill.

After the wet etching is completed. the photoresist material 28 can be removed using acetone in order to arrive at stage III.

Further, an encapsulation layer 30, preferably comprising an epoxy resin, may be deposited onto the thus obtained structure in order to protect the chip against moisture. This encapsulation layer preferably also sits between the first electrical conductor and second electrical conductor as shown in stage IV and in figure 5A. Hence, the encapsulation material is used as sensing material for the capacitive sensor. If for example moisture diffuses into the encapsulation material 30, then it can be directly detected because it will directly change the capacitance of the capacitor.

Figure 5A also illustrates that the first electrical conductor 32 and the second electrical conductor 34 define a volume 38 between them. This volume is preferably substantially entirely filled by encapsulation layer 30. In this way, the encapsulation layer may function as the sensing material of the capacitive moisture sensor.

As stated above, figure 5B shows the cross section along line B-B indicated in figure 5C.

Figure 5C illustrates that a distance d between the first electrical conductor 32 and second electrical conductor 34 is substantially the same throughout the capacitor. Path 33 defined by the first and second electrical conductor has the same width d throughout. In the depicted example, the capacitor is an interdigitated capacitor.

Figure 5D is a top view of the capacitive moisture sensor wherein the remaining parts of the electrically insulating layer 22 below the first and second electrical conductor are made visible. These remaining parts are support structures in the sense that they support the first 32 and second 34 electrical conductor. It can be said that a single support structure supports the first electrical conductor and that a single support structure supports the second electrical conductor.

Figures 6A-6E illustrate a method for fabricating a chip comprising a capacitor according to an embodiment. Herein, figure 6A illustrates different stages |, Il, lll, IV of the fabrication process for a cross section along line A-A indicated in figure 6D. Further figure 6B illustrates stage IV for cross section along line B-B indicated in figure 6D. Figure 6C illustrates a top view of the chip, at least of the part of the chip where the capacitor is present, after the first and second electrical conductor have been formed, e.g. after the electrically conductive layer 20 has been etched as desired, for example to form two conductive paths. Figure 6D illustrates stage IV for a top view of the chip. Figure 6E illustrates, for cross section along part of line A-A indicated in figure 6D, how parts of the electrically insulating layer 22 may be etched away to form the plurality of supports structures.

The method for fabricating the chip comprising the capacitor can be used for fabricating a capacitive moisture sensor on a thermal test chip. The capacitor that is fabricated may namely be used as a capacitive moisture sensor on a thermal test chip as described herein.

This method comprises fabricating a first electrical conductor 32 and a second electrical conductor 34 onto an electrically insulating layer 22. Stages | and Il illustrate how this may be performed. First, the same stack of layers may be formed that is also shown in stage | of figure 5A.

Then, similarly as in figure 5, the conductive layer 20 may be etched, for example using a photoresist material 28 and a dry etching step as described above. Figure 6C illustrates how the first 32 and second 34 electrical conductor may be shaped. Both the first and the second electrical conductor are conductive traces having a varying width along its length. Note that figure 6C shows a top view of the part of the chip that contains (will contain) the capacitor. The bottom part of figure 6C shows the indicated rectangular area 31 in more detail.

Each position on the first electrical conductor 32, as viewed from the top view of figure 6C, has a distance from an edge, preferably a side edge, that is nearest to the position in question. This distance is either smaller than or equal to a threshold distance 50 or larger than the threshold distance 50. The positions on the first electrical conductor of which the distance is larger than the threshold distance define a plurality of areas 35 and the positions on the first electrical conductor of which the distance is smaller than or equal to the threshold distance define second one or more areas. These second one or more areas may be understood to be the areas on the first electrical conductor that do not belong to said plurality of areas 35. The plurality of areas 35 are separated from each other by one or more of the second one or more areas.

Likewise, in the depicted embodiment, each position on the second electrical conductor 34, as viewed from the top view of figure 6C, has a distance from an edge, preferably a side edge, that is nearest to the position in question. This distance is either smaller than or equal to the threshold distance 50 or larger than the threshold distance 50. The positions on the second electrical conductor of which the distance is larger than the threshold distance define a plurality of areas 37 and the positions on the second electrical conductor of which the distance is smaller than or equal to the threshold distance from fourth one or more areas. These fourth one or more areas may be understood to be the areas on the second electrical conductor that do not belong said plurality of areas 37. The plurality of areas 37 are separated from each other by one or more of the fourth one or more areas.

The method for fabricating the chip comprising the capacitor further comprises etching away parts of the electrically insulating layer 22 such that the electrically insulating layer 22 is removed, e.g. substantially completely removed, from beneath the one or more second resp. fourth areas yet at least partially remains below said plurality of areas 35 resp. third plurality of areas 37 so that the remaining parts of the electrically insulating layer below the plurality of areas 35 resp. third plurality of areas 37 form a plurality of electrically insulating supports structures 42. The resulting plurality of electrically insulating support structures 42 are separated from each other by one or more intermediate spaces 40 resp. second one or more intermediate spaces and the first 32 resp. second electrical conductor 34 bridges the one or more intermediate spaces 40 resp the second one or more intermediate spaces (also refer to figure 6B).

The etching step for etching away parts of the electrically insulating layer 22 may be a wet etching step and may comprise letting the etchant work for a predetermined time. Again, BHF 7:1 (buffered hydrofluoric acid) may be used at 25 degree Celsius to etch silicon oxide. Some trial and error may be used to find a suitable etching time which yields the structure as desired, e.g. the structure as depicted in stage III. It should be appreciated that for the etchant to etch away electrically insulating material 22 that sits below the electrical conductors, the etchant has to work its way to the material sitting below the electrical conductor from the side, because the insulating material is shielded from the top by the etch resistant electrically conductive material 20. This is illustrated in figure 6E, which schematically illustrates the wet etching according to an embodiment. Figure 6E may be understood to show how to reach stage lll starting from stage Il as depicted in figure 6A. For clarity, the photoresist material 28 is not shown in figure 6E. By taking into consideration the etch rate in the side directions, i.e. in the directions parallel to the indicated xy-plane, an etch time can be determined such that the etchant 45 removes electrically insulating material that sits, as viewed from a top view, closer to a nearest side edge than the threshold distance or that is at the threshold distance 50 from the edge of the conductor or, in other words, the etch time can be determined such that the etchant does not remove electrically insulating material that sits, as viewed from a top view, further than the threshold distance 50 from an edge of the electrical conductor. The appropriate etch time may also be found using some trial and error approach, of course.

After the wet etch, the photoresist material 28 may be removed using acetone. Thereafter, encapsulating layer 30 may be deposited on the thus obtained structure in order to arrive at stage IV (see figures 6A and 6B). Figure 6B shows that the first electrical conductor 32 forms a bridge over intermediate space 40. It should be noted in the cross section shown for stage IV in figure 6A, it can be seen that the first electrical conductor 32 does not have any electrically insulating support structure beneath it. As a result, electrical field lines between the first and second electrical conductor will pass, at least below the first electrical conductor, to a greater extent through the encapsulating material 30 (and not through electrically insulating material 42 beneath the first conductor 32 because there isn't any). Hence, this increases the sensitivity of the moisture sensor (if the capacitor is used as moisture sensor).

In any case, as explained above, having encapsulation material present in the intermediate spaces 40 instead of electrically insulating support structures 42, assuming that the encapsulation material has a lower dielectric constant than electrically insulating material 22, the parasitic capacitance is reduced. This configuration thus allows to fabricate very small capacitors having accurate capacitance values, i.e. having capacitance values as intended by the design.

Figure 6D illustrates for stage IV a top view. In particular, figure 6D shows the plurality of electrically insulating supports structures 42 below the first electrical conductor 32 and the third plurality of electrically insulating support structures 43 below the second electrical conductor 34. The plurality of electrically insulating support structures 43 are positioned, as viewed from the top view, below the plurality of areas 35 indicated in figure 6C and the third plurality of electrically insulating supports structures 43 are, as viewed from the top view, below the third plurality of areas 37 depicted in figure 6C.

Figure 6D also shows that the distance between the first electrical conductor and second electrical conductor is substantially the same throughout the capacitor. In particular, in figure 6D, the path 33 that is defined by the first and second electrical conductor has the same distance d throughout.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the implementations in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present invention. The embodiments were chosen and described in order to best explain the principles and some practical applications of the present invention, and to enable others of ordinary skill in the art to understand the present invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CONCLUSIONS

A system comprising a thermal test chip and an encapsulation layer for protecting the thermal test chip against moisture, the thermal test chip comprising - one or more heating elements arranged to generate heat, and - a moisture sensor arranged to measure moisture content in said encapsulation layer.

The system of claim 1, wherein the moisture sensor is a capacitive moisture sensor.

The system of claim 2, wherein the moisture sensor comprises a capacitor comprising a first electrical conductor and a second electrical conductor and wherein a portion of the encapsulation layer is located between the first electrical conductor and second electrical conductor.

The system of claim 3, wherein the first electrical conductor and second electrical conductor define a volume between them, said volume being substantially completely filled with said portion of the encapsulation layer.

The system according to any one of the preceding claims, wherein the moisture sensor is monolithically integrated on the thermal test chip.

The system according to any one of the preceding claims, wherein the thermal test chip further comprises one or more temperature sensors.

The system according to any one of the preceding claims, wherein the thermal test chip further comprises one or more mechanical stress sensors arranged to measure mechanical stress.

The system according to any one of the preceding claims, wherein the one or more heating elements are monolithically integrated on the thermal test chip, and/or wherein the one or more temperature sensors are monolithically integrated on the thermal test chip, and/or wherein the one or more mechanical stress sensors are monolithically integrated on the thermal test chip.

The system according to any one of the preceding claims, wherein the encapsulation layer comprises an epoxy resin and/or a polyester resin and/or a polyurethane resin and/or a silicone resin.

10. A chip comprising a capacitor, the capacitor comprising

- a first electrical conductor supported by a plurality of electrically insulating support structures, said plurality of electrically insulating support structures being separated from each other by one or more interstices and wherein the first electrical conductor forms a bridge across the one or more interstices, and -a second electrical conductor.

The chip of claim 10, wherein the second electrical conductor is supported by a second plurality of electrically insulating support structures, said second plurality of electrically insulating support structures are separated from each other by a second one or more gaps, and the second electrical conductor comprises a bridge forms over the second one or more interspaces.

The chip of claim 10 or 11, wherein as viewed from a top view, the plurality of electrically insulating support structures are located below the first electrical conductor, and each position, as viewed, for example, from a top view, on the first electrical conductor is a distance of an edge of the first electrical conductor, preferably a side edge, which is nearest to the position in question, the distance being less than or equal to the threshold distance or greater than the threshold distance, the positions at the first electrical conductor whose distance is greater than the threshold distance define a plurality of regions and wherein the positions on the first electrical conductor whose distance is less than or equal to the threshold distance second define one or more regions, the plurality of regions separated from each other at one or more of the second one or more regions, the plurality of electrically conductive support structures being positioned, as viewed from the plan view, below the plurality of regions.

The chip of any one of claims 10-12, wherein a distance between the first electrical conductor and second electrical conductor is substantially the same through the capacitor.

14. A method of fabricating a chip comprising a capacitor, the method comprising fabricating a first electrical conductor and a second electrical conductor on an electrically insulating layer, each position, e.g. as viewed from a plan view, on the first electrical conductor is spaced from an edge, preferably a side edge, nearest to the position in question, the distance being less than or equal to a threshold distance or greater than the threshold distance, the positions on the first electrical conductor whose distance is greater than the threshold distance define a plurality of regions and wherein the positions on the first electrical conductor whose distance is less than or equal to the threshold distance second define one or more regions, the plurality of regions being separated from each other by one or more of the second one or more regions, the method further comprising etching away portions of the electrically insulating layer so that the electrically insulating layer is removed, e.g. completely removed, from beneath the one or more second regions and yet remains at least partially beneath said plurality of regions such that the remaining portions of the electrically insulating layer form beneath the plurality of regions a plurality of electrically insulating support structures, said plurality of electrically insulating support structures being separated from each other by one or more interstices and wherein the first electrical conductor forms a bridge across the one or more interspaces.

A chip obtainable by carrying out the method of claim 14.