JPH0518999A - Chip for evaluating resin sealed semiconductor - Google Patents

Abstract

PURPOSE:To obtain a chip for evaluation capable of carrying out simply and correctly the evaluation of leak characteristics and the corrosion characteristics of the wiring, the chip being used for evaluating semiconductor device encapsulated with resin. CONSTITUTION:A pair of parallel wirings 20, 30 for evaluation are set up in a spiral from the center of a chip substrate to the periphery of the chip substrate 10. Pad parts 42, 44 for connection to the outside wiring are provided in a plurality of positions of the wiring 20, 30 for evaluation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor evaluation chip, and more specifically, in a resin-encapsulated semiconductor device manufactured by encapsulating a semiconductor chip with resin, for evaluating various performances of the semiconductor device. The present invention relates to a performance evaluation chip used in the evaluation test.

[0002]

2. Description of the Related Art There are various items for evaluating the performance of semiconductor devices, and of these, the evaluation of leak characteristics is also an important item. Leakage characteristics mean that moisture penetrates into the sealing resin of a resin-sealed semiconductor device, which lowers the insulating properties of the sealing resin and the like, causing a leak current between the conductor wiring formed on the semiconductor chip. There is a problem that this occurs, and the state of occurrence of this leak current is evaluated as the leak characteristic.

Another item for evaluating the performance of a semiconductor device is the corrosion characteristic of wiring. This means that the water that has penetrated into the sealing resin as described above corrodes the aluminum wiring or the like, resulting in disconnection or deterioration in performance as a conductor circuit. Conventionally, the method disclosed in Japanese Examined Patent Publication No. 1-09936 has been proposed as a method for evaluating leak characteristics. This method is intended to clarify the distribution of leak current in the entire chip substrate by providing parallel wiring in a grid pattern on the chip substrate for evaluation and measuring the leak current at each intersection. ..

[0004]

However, in the conventional leak characteristic evaluation method as described above, since it is necessary to provide complicated grid-like parallel wirings, the evaluation chip is manufactured, especially the wiring is manufactured. However, there is a problem in that the work efficiency of the entire evaluation test is reduced and the test cost is increased.

Further, in the case of the grid-like parallel wiring, the leak state at each intersection cannot be measured under a bias voltage applied, so that the leak state at the bias test cannot be confirmed. Similarly, a test for measuring the corrosion state of the wiring during the bias test cannot be performed. Therefore, an object of the present invention is to easily and accurately measure the distribution of the leakage current by simply forming a wiring of a simple structure on the evaluation chip, and to corrode the wiring in a state where a bias voltage is applied to the wiring. An object of the present invention is to provide an evaluation chip capable of performing a test for measuring the condition.

[0006]

A resin-sealed semiconductor evaluation chip according to the present invention for solving the above-mentioned problems is a performance evaluation chip for a semiconductor device in which a semiconductor chip is sealed with a resin, and is a chip substrate. In addition, a pair of parallel evaluation wirings are spirally provided from the center of the chip substrate to the outer periphery, and each evaluation wiring is provided with a pad portion for connecting to an external wiring at a plurality of locations.

As the basic structure of the resin-sealed semiconductor evaluation chip, a normal semiconductor chip structure similar to that of a known evaluation chip or the like is adopted according to the structure of the semiconductor device and the chip to be manufactured. The chip substrate is made of a semiconductor material such as silicon and has a plate shape such as a polygon.
An insulating layer made of a silicon thermal oxide film or the like is formed on the surface of the chip substrate, and conductor wiring necessary for performance evaluation is formed on the insulating layer. Aluminum wires are usually used for the conductor wires, but wires made of other conductors may be used. The structure of the insulating layer and the conductor wiring formed on the chip substrate is set according to the structure of the semiconductor chip to be evaluated.

In the present invention, as the conductor wiring, a pair of two evaluation wirings are provided in a spiral shape from the center to the outer periphery of the chip substrate in parallel with each other at a constant interval. The spiral shape may be an arbitrary spiral shape, such as a circular spiral or other curved spiral, or a polygonal spiral in which a straight line is gradually bent to form a polygon. The line width, thickness, or spacing of the evaluation wiring is set in consideration of the wiring structure of semiconductor chips to be actually manufactured, test conditions, measurement accuracy, and the like.

The evaluation wirings arranged in a spiral shape are provided with pad portions for connecting to external wirings at a plurality of positions of each evaluation wiring. The connection pad portion is formed of a conductive material similar to that of the evaluation wiring, and is formed in a planar shape having a certain area such that bonding wires can be connected. The structure may be the same as that of the pad portion of the semiconductor chip. The connection pad portion may be provided adjacent to a predetermined position of the evaluation wiring, or the connection pad portion may be provided on the outer peripheral portion of the chip substrate, and the predetermined position of the evaluation wiring and the connection pad portion may be provided. It is also possible to connect the portions with a conductor wiring for connection. If the connection position between the connection pad and the evaluation wiring is far,
In some cases, it is necessary to arrange the connecting wiring so as to intersect with or straddle other portions of the evaluation wiring. In such a case, it is preferable that the wiring has a two-layer structure and the evaluation wiring and the connection wiring to the connection pad portion are separated. In order to form the wiring with a two-layer structure, a usual method for producing two-layer wiring in a semiconductor chip can be applied. The installation interval of the connection pad portion with respect to the evaluation wiring may be determined in consideration of conditions such as the total length of the evaluation wiring and measurement accuracy. As the installation intervals of the connection pad portions are set to be narrower at a constant interval, the distribution of leak characteristics in the entire chip substrate can be measured more finely and strictly. If connection pads are also provided at both ends of the entire evaluation wiring, leak measurement can be performed at each connection pad in the middle with a bias voltage applied to the connection pads at both ends. It is convenient because you can check the corrosion state of.

A bonding wire is connected to each connection pad portion to connect to an external wiring such as a lead frame on which a semiconductor chip is mounted. By connecting the electrodes of the measuring device to the external wiring of the lead frame, the leak current can be measured and the bias voltage can be applied. The evaluation chip, like a normal semiconductor chip,
A semiconductor package or semiconductor device for evaluation is manufactured by being sealed with a sealing resin. Therefore, if a voltage is applied to each connection pad and electrical measurement is possible while the evaluation chip is sealed with resin and a semiconductor device is manufactured, the connection pad will be sealed. As the wiring structure to the outside of the resin, the wiring structure in a normal semiconductor device can be freely applied.

[0011]

[Function] If a pair of parallel evaluation wirings are spirally provided on the surface of the chip substrate and the leak current between the pair of evaluation wirings is measured, the evaluation wirings can be located at any position. Leakage can be measured. If leak measurement is performed at a plurality of spiral evaluation wirings, the leak distribution of the entire chip substrate can be measured. If the connecting pads are provided at a plurality of positions on the evaluation wiring, the leak current between the evaluation wirings can be easily measured only by connecting the connecting pad to the external wiring.

Further, in the evaluation wirings arranged in a grid pattern, a bias voltage cannot be applied to both ends of the wirings, but in the case of the evaluation wirings arranged in a spiral shape, a bias voltage is applied to both ends of the wirings or an arbitrary place. You can apply a voltage. As a result, it is possible to easily perform various measurements that must be performed with a bias voltage applied, and for example, it is possible to satisfactorily measure the corrosion state of wiring during a bias test.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show the wiring structure of the evaluation chip 1. The evaluation chip 1 includes evaluation wirings 20 and 30 made of aluminum wiring on a surface of a rectangular substrate chip 10 made of silicon or the like, with an insulating layer (not shown) made of a thermal oxide film of silicon or the like interposed therebetween. Has been formed.

The evaluation wirings 20 and 30 have the same width and are provided in parallel at regular intervals, and are arranged so as to form a polygonal spiral from the center of the chip substrate 10 to reach the outer periphery. There is. At both ends of the center and outer circumferences of the evaluation wirings 20 and 30, connection pad portions 52 and 54,
56 and 58 are formed. A large number of connection pad portions 42 and 44 are provided side by side at positions along the outer periphery of the chip substrate 10.

As shown in FIG. 2, the pair of connection pad portions 42 and 44 are provided at appropriate positions on the evaluation wirings 20 and 30.
The evaluation wirings 20 and 30 are electrically connected to the opposing positions by a connection wiring 46. Of the connection wirings 46, at the positions intersecting with the evaluation wirings 20 and 30, the connection wirings 46 are arranged on the back surface or the inner layer of the chip substrate 10, and the evaluation wirings 20 and 30 and the connection wirings 4 are arranged.
By forming 6 in a two-layer structure, the connection wiring 4
6 and the evaluation wirings 20 and 30 are electrically separated.

Using the evaluation chip 1 having the wiring structure as described above, for example, an evaluation semiconductor device as shown in FIG. 3 is manufactured. That is, the evaluation chip 1 is placed on the lead frame 2 and fixed by die bonding or the like. Further, each connection pad portion 42 of the evaluation chip 1
, And the wiring (not shown) of the lead frame 2 are electrically connected by wire bonding with an Au wire 3 or the like. In this state, most of the evaluation chip 1 and the lead frame 2 are sealed with a sealing resin 4 such as an epoxy resin. The end portion of the lead frame 2 extends to the outside of the sealing resin 4, and if an external wiring or circuit is connected to the end portion of the lead frame 2, electrical measurement or voltage of each connection pad portion 42 ... Can be applied.

The semiconductor device thus manufactured is
After performing an environmental test such as exposure to a high-humidity environment or during the environmental test, each connection pad portion 42 ...
The leak current of the evaluation wirings 20 and 30 is measured for each set of the connection pad portions 42 and 44 by connecting the measurement electrode to the wiring connected to. A plurality of sets of connection pad portions 42, 4
If the leakage currents of the evaluation wirings 20 and 30 in 4 are measured sequentially or simultaneously, the distribution of the leakage currents on the entire surface of the chip substrate 10 can be known. In addition, the connection pad portions 52 to 58 on both ends of the evaluation wirings 20 and 30.
If a bias voltage is applied to, the leak state during the bias test and the corrosion state of the evaluation wirings 20 and 30 can be known.

[0018]

As described above, according to the resin-sealed semiconductor evaluation chip of the present invention, since the pair of parallel evaluation wirings are spirally provided on the chip substrate, the spiral evaluation is performed. By measuring the leakage current between the evaluation wirings by using the connection pad portion connected to the wiring for inspection, the leakage current at any position on the chip substrate can be known.

Further, by applying a bias voltage to both ends of the evaluation wiring or to an arbitrary section, various measurements that must be performed with the bias voltage applied can be easily performed. For example, the corrosion state of the wiring can be measured. You can do well.
As a result, the performance evaluation of the resin-encapsulated semiconductor device can be performed efficiently and economically, and the performance or reliability of the semiconductor device can be greatly improved.

[Brief description of drawings]

FIG. 1 is a plan view of an evaluation chip showing an embodiment of the present invention.

FIG. 2 Partially enlarged view of the above

FIG. 3 is a schematic schematic cross-sectional view of a resin-sealed semiconductor device.

[Explanation of symbols]

 1 Evaluation Chip 10 Chip Substrate 20, 30 Evaluation Wiring 42, 44, 52, 54, 56, 58 Connection Pad Section 46 Connection Wiring

Claims (1)

Claim: What is claimed is: 1. A performance evaluation chip for a semiconductor device, comprising a semiconductor chip encapsulated with resin, wherein a pair of parallel evaluation wirings are provided on a chip substrate from the center of the chip substrate. A resin-encapsulated semiconductor evaluation chip, which is provided in a spiral shape on the outer periphery, and each evaluation wiring is provided with a pad portion for connecting to an external wiring at a plurality of locations.