JPH05183438A - Analog digital conversion circuit - Google Patents

Abstract

PURPOSE:To allow the circuit receiving analog signals from plural input terminals and A/D-converting a signal from one selected input terminal to confirm from which terminal the converted result is inputted. CONSTITUTION:Plural analog signal are inputted from an input terminal section 1. One signal among them is selected at an input selector section 2 by using a terminal selection signal SL and the selected signal is fed to an A/D converter 3. The result of A/D conversion is stored in an A/D conversion result register 4 by using a latch signal LT. Simultaneously the terminal selection signal SL is fetched to a terminal number latch register 6 by using the same latch signal LT. Data in the registers 4, 6 are obtained via an internal bus with read signals RD1, RD2 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion circuit, and more particularly to an analog / digital conversion built in a single-chip microcomputer for selecting and converting one signal from a plurality of analog input signals. Regarding the circuit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional analog / digital conversion circuit of this type. As shown in the figure, the conventional analog-to-digital conversion circuit includes an input terminal unit 1 having a plurality of terminals to which analog signals are respectively input, and a terminal selection signal SL being input, , An input selector section 2 for selecting one terminal, an A / D converter 3 for A / D converting an input analog signal, and an A / D conversion result register 4 for holding the obtained conversion result.
, An internal bus 5, and a signal line connecting them.

One of the analog signals input to the input terminal section 1 is selected in the input selector section 2 by the terminal selection signal SL. The selected analog signal is A / D converted in the A / D converter 3. The result of the A / D conversion is transferred to the register 4 at the same time when the A / D conversion is completed.

Further, the input selector section 2 selects the next analog signal by the next terminal selection signal SL after a lapse of a fixed time, performs A / D conversion in the same manner as described above, and transfers it to the A / D conversion result register. The data in the A / D conversion result register 4 is read to the internal bus 5 by the read signal RD ₁ . In that case, which terminal the signal conversion result is read from is determined by referring to the terminal selection signal SL and recognizing which terminal is selected by which terminal selection signal.

[0005]

The conventional analog-to-digital conversion circuit described above forcibly transfers sequentially different A / D conversion results to one A / D conversion result register. If it is desired to sequentially use the A / D conversion result in this state, the A / D conversion result register must be sequentially accessed by software processing or hardware processing. However, if for some reason the A / D conversion register cannot be accessed before the next conversion operation is completed, that is, before the contents of the A / D conversion result register are rewritten, skipping occurs and this When repeated, there is a problem that it is not possible to confirm which input terminal the A / D conversion result of the signal is transferred to the A / D conversion result register.

[0006]

SUMMARY OF THE INVENTION An analog-digital conversion circuit according to the present invention comprises a plurality of input terminals to which analog signals are input, and an input selector for selecting one input terminal from the plurality of input terminals. A unit, an A / D converter that converts an analog signal input to a selected input terminal into a digital signal, an A / D conversion result register that latches a conversion result of the A / D converter by a latch signal, A terminal number latch register for fetching the number of the selected input terminal by the latch signal at the same timing as the latch signal and storing the number is stored.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention. As shown in the figure, the circuit of this embodiment is
An input terminal unit 1 having a plurality of input terminals for receiving an analog signal from the outside into the microcomputer, and one terminal (that is, one analog signal) is selected from the plurality of input terminals by a terminal selection signal SL. An input selector unit 2 to be selected, an A / D converter 3 for A / D converting the selected analog signal, and a result obtained by the A / D converter 3 being held by a latch signal LT. It comprises a D conversion result register 4, an internal bus 5, and a terminal number latch register 6 for receiving the terminal number currently selected by the latch signal LT.

Next, the operation of the circuit of this embodiment will be described. The analog signal is input from the input terminal unit 1 and input to the input selector unit 2 via the signal line. Selector unit 2
Selects one analog signal by the terminal selection signal SL from the analog signals input via the plurality of signal lines, and transmits the analog signal to the A / D converter 3 via the signal line. When the A / D converter 3 completes the A / D conversion of the analog signal, it transfers the conversion result to the A / D conversion result register 4.

The A / D conversion result register 4 takes in the A / D conversion result by the latch signal LT and holds it.
The terminal number latch register 6 latches the terminal selection signal SL by this same latch signal LT. As a result, by accessing the conversion terminal number latch register 6, the analog signal currently input from which terminal is A / D
It is possible to know if it has been converted.

In this embodiment, the read signals RD ₁ and RD ₂ are sequentially applied to the A / D conversion result register 4 and the terminal number latch register 6 and the A / D conversion result register 4 and the terminal number latch register 6 are connected to each other via the internal bus 5.
The D conversion result and the corresponding input terminal number can be obtained. In this case, when the number of signal lines of the internal bus 5 has a margin with respect to the number of bits of the registers 4 and 6, read signals of the same timing are applied to the registers 4 and 6 to read the data of these registers. Good.

FIG. 2 is a block diagram showing a second embodiment of the present invention. This embodiment is different from the embodiment of FIG.
By the read signal RD ₁ for reading the data of the D conversion result register 4, the terminal number latch register 6
A terminal number storage register 7 for taking in the data of 1 is added, but the other configuration is the same as that of the embodiment of FIG.

In this embodiment, the latch signal LT causes A
The A / D conversion result is latched in the / D conversion result register 4, and the terminal number to which the A / D converted input signal is input is latched in the terminal number latch register 6. In this state, the read signal RD ₁ is applied to the A / D conversion result register 4 to read the data in the register 4.
At the same time, the read signal RD ₁ stores the terminal number stored in the terminal number latch register 6 in the terminal number storage register 7. Then, the data in the terminal number storage register 7 is read to the internal bus 5 from the read signal RD ₂ .

In the embodiment of FIG. 1, when the data of the terminal number latch register 6 is read after reading the data of the A / D conversion result register 4, after reading the register 4 and before reading the register 6. There was a case where the next latch signal LT was input and the read A / D conversion result and the next read terminal number did not match. However, in the present embodiment, the read signal RD ₁ to the A / D conversion result register 4 Since the terminal number is stored in the terminal number storage register 7 by the following, after the A / D conversion result register 4 is read, the next latch signal is the A / D conversion result register 4
And input to the terminal number latch register 6,
The terminal number storage register 7 holds the correct terminal number corresponding to the contents read from the A / D conversion result register 4, and the above-mentioned inconvenience in the embodiment of FIG. 1 does not occur.

[0014]

As described above, the analog-to-digital conversion circuit of the present invention is one in which analog signals are input from a plurality of input terminals and the signals of the selected input terminals are A / D converted. Since the number latch register is provided and the A / D conversion result is stored in the A / D conversion result register, the selected terminal number is input at the same time. By accessing the latch register or the register to which the data of this register is transferred, it becomes possible to confirm whether or not the necessary A / D conversion result can be accessed and from which terminal the analog signal cannot be accessed. .. Therefore, when an access leakage of the A / D conversion result occurs, the analog signal from which terminal is A / D
You can know if the correct information will be obtained if you perform D conversion again.
It becomes possible to obtain a correct processing result in the processing of the microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional example.

[Explanation of symbols]

1 Input terminal section 2 Input selector section 3 A / D converter 4 A / D conversion result register 5 Internal bus 6 Terminal number latch register 7 Terminal number storage register LT Latch signal RD ₁ , RD ₂ Read signal SL terminal selection signal

Claims (2)

[Claims] 1. A plurality of input terminals to which an analog signal is respectively input, an input selector section for selecting one input terminal from the plurality of input terminals, and an analog signal input to the selected input terminal. Selected by an A / D converter for converting the signal into a digital signal, an A / D conversion result register for latching the conversion result of the A / D converter by a latch signal, and a latch signal at the same timing as the latch signal. An analog terminal equipped with a terminal number latch register that captures the input terminal number and stores it
Digital conversion circuit. 2. A plurality of input terminals to which an analog signal is input, an input selector section for selecting one input terminal from the plurality of input terminals, and an analog signal input to the selected input terminal. Selected by an A / D converter for converting the signal into a digital signal, an A / D conversion result register for latching the conversion result of the A / D converter by a latch signal, and a latch signal at the same timing as the latch signal. The number of the input terminal stored in the terminal number latch register is read at the same timing as when the number of the input terminal is fetched and stored and the data of the A / D conversion result register is read. A terminal number storage register to read and store,
Analog-to-digital conversion circuit equipped with.