JPH07240687A - Data shift circuit for a/d converter - Google Patents

Abstract

PURPOSE:To prevent firmware of a microcomputer from being increased by providing the A/D converter and a data selector so as to read data through division of each of prescribed bits from high-order bits or low-order bits of A/D-converted data in multi-bits. CONSTITUTION:The A/D converter 1 converts an analog input signal into digital mufti-bit data, and a data selector 2 sequentially provides an output of data in prescribed bits (e.g. 8-bit) from high-order bits of the converted multi-bit data and in remaining bits or an output of data in prescribed bits (e.g. 8-bit) from low-order bits of the converted multi-bit data and in remaining bits. Thus, the multi-bit data after A/D conversion are dynamically read in prescribed bits from the high-order bits or the low-order bits of the data by reading the ADD-converted multi-bit data by the A/D converter 1 for each of prescribed bits from the high-order bits or the low-order bits and the remaining bits of the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data shift circuit for extracting partial data from A / D converted data.

[0002]

2. Description of the Related Art A multi-bit (10 or more bits) A / D converter generally displays 8 bits in one register as an array of data and displays the remaining bits in another register. .

When the one-chip microcomputer uses the A / D converter to perform A / D conversion with the above 10 bits, the upper 8 bits are displayed in one register and the lower 2 bits are displayed in another register. When doing so fixedly, when the precision of 8 bits is requested, the upper 8 bits are read from the register 1 and when the precision of 10 bits is requested, the upper 8 bits are read from the register 1 by the firmware of the microcomputer. After reading the lower 2 bits from another register, they must be assembled into 10-bit data. Considering both of these, conventionally, after reading the data from one register and another register and assembling it into 10 bits, the bits of the necessary precision part (8 bits from the high order, or all 10 bits from the high order) are set. I was trying to lead.

[0004]

As described above, when A / D conversion is performed by using a multi-bit A / D converter of 8 bits or more, after 8 bits are taken out and assembled, the upper 8 bits are set. Alternatively, there is a problem in that an operation of taking out all the 10 bits from the higher order is required, and the processing of the firmware of the microcomputer increases.

The present invention solves these problems.
The multi-bit data A / D converted by the A / D converter is divided into predetermined bits from the upper bit or the lower bit and read by the newly provided data selector, thereby eliminating the increase in the firmware of the microcomputer. Has an aim.

[0006]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, an A / D converter 1 converts an analog input signal into digital multi-bit data.

The data selector 2 selects a predetermined bit (for example, 8 bits) from the upper bit of the multi-bit data converted by the A / D converter 1 and a remaining bit, or a predetermined bit (from the lower bit of the converted data). For example, every 8 bits) and the remaining bits are sequentially output.

[0008]

The present invention, as shown in FIG. 1, includes an A / D converter 1
Converts an analog input signal into digital multi-bit data, and the data selector 2 converts the converted multi-bit data every predetermined bit (for example, 8 bits) from the upper bit and the remaining bit, or from the lower bit to the predetermined bit. Each (for example, 8 bits) and the remaining bits are sequentially output.

Further, the A / D converter 1 converts an analog input signal into digital multi-bit data, and the data selector 2 requests a read for each predetermined bit (for example, 8 bits) from the upper bit of the read source. Alternatively, the multi-bit data converted by the A / D converter 1 in response to a read request for each predetermined bit (for example, 8 bits) from the lower bit, for each predetermined bit (for example, 8 bits) and the remaining bits from the higher bit. Alternatively, every predetermined bit (for example, 8 bits) from the lower bit and the remaining bit are sequentially output, and the read source reads and takes them in.

Therefore, from the multi-bit data A / D converted by the A / D converter 1, a newly provided data selector 2 reads a predetermined bit (for example, 8 bits) from the upper bit or the lower bit and the remaining bit. As a result, it becomes possible to dynamically read from the multi-bit data after A / D conversion every predetermined bit (for example, 8 bits) from the upper bit or every predetermined bit (for example, 8 bits) from the lower bit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS. Here, A
An example in which the analog input signal is converted into 10-bit data by the / D converter 1 and the higher bits are output every 8 bits and the remaining bits or the lower bits are output every 8 bits and the remaining bits are sequentially described below.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1A, an A / D converter 1 converts an analog input signal into digital multi-bit data, and converts the analog input signal into, for example, the illustrated 10-bit data. It is a thing.

The data selector 2 sequentially outputs every 8 bits from the upper bit of the multi-bit data converted by the A / D converter 1 and the remaining bits, or from the lower bit of the converted data every 8 bits and the remaining bits. It is what is output.

The data R / W buffer 3 fetches 8-bit data corresponding to a read request from the read source 4 from the data selector 2, holds the data, and sends the data to the read source 4.

The read source 4 reads the 8-bit data requested to be read and the remaining data from the data R / W buffer 3, and is an MPU or the like. FIG. 1B shows an example of the data array.

In step 1, the read source 4 writes a command in the data R / W buffer. This command includes: -bit 7 = ADST (A / D conversion start) 1 starts A / D conversion start 0 0 does not start A / D conversion-bit 6 = SIDT (shift information) 0 = upper 8 bits , Read with remaining 2 bits 1 = 8 bits from lower bit, read with remaining 2 bits to start A / D conversion, and A / D
It is a request to read either the upper 8 bits and the remaining 2 bits or the lower 8 bits and the remaining 2 bits of the converted 10-bit data.

Indicates that the read source 4 reads the first 8-bit data from the data R / W buffer when SIDT (shift information) = 0 (A type) (D9-in FIG. 4). D2 data).

Indicates that the read source 4 reads the first 8 bits from the data R / W buffer when SIDT (shift information) = 1 (B type) (D7 to D0 in FIG. 5). Represents data).

Indicates that the read source 4 reads the second (remaining) 2 bits from the data R / W buffer when SIDT (shift information) = 0 (A type) (D1 in FIG. 4). , D0 data). Here, ADEN of bit 7 represents an A / D conversion completion flag, and 1 is A
/ D Indicates conversion completion.

Indicates that the read source 4 reads the second (remaining) 2 bits from the data R / W buffer when SIDT (shift information) = 1 (B type) (D9 in FIG. 5). , D8 data). Here, ADEN of bit 7 represents an A / D conversion completion flag, and 1 is A
/ D Indicates conversion completion.

Next, the overall operation of the configuration of FIG. 1 will be described according to the order shown in the flowchart of FIG. In FIG. 2, S1 starts A / D conversion. This is because the read source 4 uses the data R / W buffer 3 as described on the right side.
Then, the following parameters are set in the command of FIG.

Address 0 (SIDT of bit 6 = address 0) ASDT = 1 (ASDT = 1 of bit 7) In response to writing this command, the A / D converter 1 performs A / D conversion. At the same time as starting, the address 0 is stored (that is, in the A mode, (b) of FIG.
Remember to do the data shift of).

In step S2, the conversion time is waited. This is S1
In response to the start of A / D conversion at step 1, the completion of A / D conversion is awaited. In S3, the data type is set. This is as described on the right. ・ In the case of A type, it is set to the default (SIDT =
0). That is, the data shift shown in FIG. 1B at SIDT = 0 is set.

For type B, set SIDT = 1. That is, the data shift shown in (1) of SIDT = 1 in FIG. 1B is set. In S4, the converted data is read. This reads the data by the addresses 1 and 2 according to the A type / B type set in S3. In the case of A type, data is read as shown in (b) of FIG.

In the case of the B type, as shown in FIG.
To read the data. As described above, the read source 4 writes the command of FIG. 1B into the data R / W buffer 3 to start A / D conversion, sets A type or B type, and completes A / D conversion. At this point, if the set type is the A type, the data in (b) of FIG. 1 is read, and if the set type is the B type, the data in (b) of FIG. 1 is read. To lead.

FIG. 3 is a conceptual explanatory view of the present invention. Figure 3
(A) represents the A type. A for A type
D9 to D2 of the data of the / D converter 1 are set to bit 7 to bit 0, then D1 to D0 are set to bit 1 to bit 0, and 2
Lead in batches.

FIG. 3B shows the B type. In the case of the B type, D7 to D0 of the data of the A / D converter 1 are set to bit 7 to bit 0, and then D9 to D8 are set to bit 1 to 1
Set to bit 0 and read in two times.

FIG. 4 shows a time chart (A type) of the present invention. In FIG. 4, in S11, the read source 4 writes A / D to the A / D converter 1 in response to writing the command “10xx, xxxx” into the data R / W buffer 3.
Start D conversion. At this time, bit 6 SIDT
Since A = 0, the A mode is stored.

In step S12, the read source 4 polls and reads ADEN (a flag indicating whether A / D conversion has been completed) from the data R / W buffer 3 by the command "1XXX, XXX". , Here, it is confirmed that the A / D conversion is completed.

In step S13, since the type A is stored in step S11, the read source 4 outputs the address 1 and the buffer (data R / W buffer 3) outputs 8 from D9 to D2 in FIG.
Read a bit.

In S14, since the A type is stored in S11, the read source 4 outputs the address 2 and the buffer (data R / W buffer 3) outputs 2 to D1 to D0 in FIG.
Read a bit.

As described above, the read source 4 stores the A / D conversion start and the A type in the data R / W buffer 3 by the command, sends the address 1 and reads D9 to D2 after confirming the completion of the A / D conversion. , Then address 2
To read D1 to D0. As a result, data can be sequentially read every 8 bits according to the A type set by the command.

FIG. 5 shows a time chart (B type) of the present invention. In FIG. 5, in S21, the read source 4 writes A / D to the A / D converter 1 in response to writing the command “11xx, xxxx” in the data R / W buffer 3.
Start D conversion. At this time, bit 6 SIDT
Since B = 1, the B mode is stored.

In step S22, the read source 4 polls and reads ADEN (a flag indicating the completion of A / D conversion) from the data R / W buffer 3 by the command "1XXX, XXX". , Here, it is confirmed that the A / D conversion is completed.

In S23, since the type B is stored in S21, the read source 4 outputs the address 1 and the buffer (data R / W buffer 3) outputs D8 to D8 of FIG.
Read a bit.

In S24, since the B type is stored in S21, the read source 4 outputs the address 2 and the buffer (data R / W buffer 3) outputs 2 to D9 to D8 in FIG.
Read a bit.

As described above, the read source 4 stores the A / D conversion start and B type in the data R / W buffer 3 by the command, sends the address 1 and reads D7 to D0 after confirming the completion of the A / D conversion. , Then address 2
To read D9 to 80. As a result, it becomes possible to sequentially read data every 8 bits according to the B type set by the command.

FIG. 6 shows a circuit example of the data selector of the present invention. This is a specific circuit example of the data selector 2 of FIG. FIG. 6A shows D9 through A / D converted.
From 10 bits of D0, the data selector 2 selects and outputs any one of D8, D2 and D0 to bit 0 of 8 bits, that is, outputs D0 to bit 0 when the address is A type and the address is 2.・ D0 is output to bit 0 when address is 1 in B type ・ D2 is output to bit 0 when address is 1 in A type ・ D8 is output to bit 0 when address is 2 in B type Output either It is a circuit to do. As a result, as shown in bit 0 of FIG. 1 (b), D / A converted D8,
Either D2 or D0 will be output as shown.

FIG. 6B shows A9-D-converted D9-
From 10 bits of D0, the data selector 2 selects and outputs any one of D9, D3, and D1 to bit 1 of the 8 bits, that is, outputs D1 to bit 1 when the address is A type and address 2・ D1 is output to bit 1 when address is 1 in B type ・ D3 is output to bit 1 when address is 1 in A type ・ D9 is output to bit 1 when address is 2 in B type Output either It is a circuit to do. As a result, as shown in bit 1 of FIG. 1B, A / D-converted D9,
Either D3 or D1 will be output as shown.

FIG. 6C shows D9 through A / D converted signals.
From 10 bits of D0, the data selector 2 selects and outputs any of D9 to D2 to bits 7 to 2 of 8 bits, that is, when the address is 1 in the B type, D7 to D2 is set to bit 7
Output to ~ 2 ・ When the address is A type and the address is 1, D9 to D4 are bit 7
It is a circuit that outputs one of the outputs to ~ 2. As a result, as shown in bits 7 and 2 of FIG.
7 to D2 or D9 to D4 are output as shown.

FIG. 7 shows a circuit example of the data R / W buffer of the present invention. FIG. 7A shows an example of the read decoder. In this, either the address 1 or the address 2 is set to "1" based on the command (AD0 line, AD1 line) notified from the read source 4 to the data R / W buffer 3. Here, when the address line AD0 is "1" and the address line AD1 is "0", the address 1 is "1".

Address 2 is "1" when address line AD0 is "0" and address line AD1 is "1". FIG. 7B shows an example of the write register. This is to set and store A type or B type based on the command (AD0 line, AD1 line, D6 of data line) notified from the read source 4 to the data R / W buffer 3. Here, the address line AD0 is “0” and the address line AD1 is “0”
When the data line D6 is "0" at this time, it is set and stored as the A type.

Address line AD0 is "0, address line A
When the data line D6 is "1" when D1 is "0",
The type B is set and stored.

[0044]

As described above, according to the present invention,
From the multi-bit data A / D converted by the A / D converter 1, a newly provided data selector 2 selects a predetermined bit (for example, 8 bits) from the upper bit or the lower bit.
Since it employs a configuration that reads each bit and the remaining bit,
It is possible to dynamically instruct and read a predetermined bit (for example, 8 bits) from the upper bit or a predetermined bit (for example, 8 bits) from the lower bit dynamically from the multi-bit data after D / D conversion. In addition to that, if the A / D converter 1 has a resolution of 10 bits, for example, the A / D converter 1 having a resolution of 8 bits or 10 bits can be dynamically set, and the A / D converter 1 can be used to select A.
/ D conversion can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart explaining the operation of the present invention.

FIG. 3 is a conceptual explanatory diagram of the present invention.

FIG. 4 is a time chart (A type) of the present invention.

FIG. 5 is a time chart (B type) of the present invention.

FIG. 6 is a circuit example of a data selector of the present invention.

FIG. 7 is a circuit example of a data R / W buffer of the present invention.

[Explanation of symbols]

 1: A / D converter 2: Data selector 3: Data R / W buffer 4: Read source (MPU)

Claims (3)

[Claims] 1. A data shift circuit for extracting partial data from A / D-converted data, comprising: an A / D converter (1) for converting an analog input signal into digital multi-bit data; A data selector (2) for sequentially outputting a predetermined bit and a remaining bit from the upper bit of the bit data, or a predetermined bit and a remaining bit from the lower bit of the converted multi-bit data. Data shift circuit of the / D converter. 2. In a data shift circuit for extracting partial data from A / D converted data, an A / D converter (1) for converting an analog input signal into digital multi-bit data, and a higher order than a read source. Corresponding to a read request for each predetermined bit from the bit or a read request for each predetermined bit from the lower bit, the upper bit of the multi-bit data converted by the A / D converter (1) and the remaining bit A data selector (2) for sequentially outputting a predetermined bit and the remaining bit from the lower bit of the bit or the converted multi-bit data.
Data shift circuit of D converter. 3. The A / A according to claim 1 or 2, wherein the predetermined bit is 8 bits.
Data shift circuit of D converter.