JPH01316845A - Image processing device - Google Patents

Abstract

PURPOSE:To output image data of arbitrary bit length by providing a bit shifter which converts a format to the data format of the image data. CONSTITUTION:An image memory access circuit 3 is constituted of a memory mapping data buffer 91 on which the mapping information of an image memory 94 is registered in advance, a 1-bit/word address conversion circuit 92 for actual addressing to the memory 94 with an image memory address, a controller 93 for the generation of the R/W signal of the memory 94 and the chip select signal of the brain of the memory 94, the memory 94 to store image data fetched from a camera, the bit shifter 95 which performs the conversion or reverse conversion of the format of data read from the memory 94 to the data format of each memory area, and a bit shifter controller to control the bit shifter 95.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device in the field of image processing, and particularly to an image processing device that can be mapped to an image memory with an arbitrary bit length and read out from an arbitrary address in an arbitrary size. The present invention relates to an image processing device capable of processing images.

(Prior Art) FIG. 7 is a schematic configuration diagram of a general image processing device. In the figure, (1) is a CPU that performs various calculation operations to control the entire device, (2) is a main memory, ( 3) is a camera for capturing images, (4) is an A/D converter that converts the analog signal image captured by the camera (3) into a digital signal, and (5) is the above camera (3).
(6) is a D/A converter (described later); (7) a monitor that displays the converted image as a digital signal processed image; (7) ) is frame memory (
5) is a D/A converter that converts the digital signal stored in the frame memory into an analog signal; (8) is the frame memory (
5) is a graphics processor that controls drawing display based on frame memory data; (9) is an image memory access circuit; and (1O) is an image processing unit that performs image processing of image data in the image memory.

Next, FIG. 8 is a block diagram of an image memory access circuit (9) in a conventional image processing device, in which the image memory access circuit (9) is connected to the CPU.
An image memory read/write controller (93) for outputting a chip select signal of the image memory (94) and a read/write signal based on the read/write signal from (see Fig. 7), and input image data. The configuration includes an image memory (94) for storing data.

Next, the operation of the image memory access circuit of the conventional device will be explained. The image memory access circuit of a conventional image processing device accesses the image memory (94) from an image of the same bit length corresponding to the image memory address and read/write signal output from the image memory read/write controller (93). Memory data was being accessed. Therefore, if the bit length of the data with respect to the image memory address is different, it cannot be mapped freely to the image memory (94), and the mapping is fixed in advance. Figure 9(a)
is an example of a conventional image memory map, which has a table data area (16 bits/word), a grayscale image area (8
For data having three types of data bit lengths: (1 bit/word) and a binary image area (1 bit/word), the mapping of the area must be fixed in advance.

However, as shown in FIG. 9(b), by setting all data to 16 bits/word, the above area can be mapped freely in the image memory, but in the case of a grayscale image, one word corresponds to 2 pixels, and 2 pixels per word. If it is a value image, 1 word is 166
Since it has pixel data, it is necessary to extract more target bits from one word.

(Problems to be Solved by the Invention) Since the conventional image processing apparatus is configured as described above, there is no flexibility in the storage mode of the image memory, and especially when performing only grayscale image processing in image processing,
The pre-fixed binary image memory area and table data area are no longer required, and problems such as the inability to use memory effectively are resolved.

Furthermore, the size of the image cannot be easily changed, and an image processing device with different mappings must be prepared for each image size. Alternatively, there is a method in which all data has a fixed bit length and the image memory is mapped arbitrarily by the user, but this requires processing to extract the target bit from the fixed bit length data, which complicates the processing operation and increases processing time. It had become.

In addition, there are methods to process pixels in units of words in order to reduce this processing, but there are problems such as the inability to handle images in units of pixels and the occurrence of word boundary restrictions.

This invention was made to solve the above problems,
The user can allocate a grayscale image memory area, a binary image memory area, and a table data area of any size to any area of the image memory.
An object of the present invention is to obtain an image processing device that can automatically output data output from an image memory as arbitrary bit length data specified by a user.

[Means to solve the problem]

The image processing device according to the present invention registers and stores mapping information of an image memory in a memory mapping data storage means in advance, and converts the mapping information of the memory mapping data storage means into an image of the image memory by using an address conversion means. The data read from the image memory is converted into a memory address, and the data read from the image memory is converted and inversely converted into the data format of each memory area by the data format shift means based on the image memory address of the address conversion means corresponding to the read/write signal of the image memory. death,
The transformed and inversely transformed data is sampled and quantized and processed into a digital signal of an image.

[Effect]

The image processing device according to the present invention can map the image memory from any address to any size by converting the image memory data into data of any bit length.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. FIG. 1 is a detailed circuit block diagram of an image memory access circuit according to the embodiment, and FIG. Figure 3 is a diagram of mapping information of memory, Figure 4 is a conceptual diagram of image memory and bit shifter, Figure 5 is a diagram of data conversion in bit shifter, and Figure 6 is a data format of image address. In each of the above figures, the image processing device according to this embodiment differs from the conventional device shown in FIG. 7 in the content of the image memory access circuit (9), and the other configurations are the same. It is.

The image memory access circuit (9) in the device of this embodiment has a memory mapping data buffer (9) in which mapping information of the image memory (94) is registered in advance.
91) and image memory (
94) into a 1 bit/word address for actual addressing, a read/write signal for the image memory (94), and a brain chip in the image memory (94) to be described later. An image memory read/write controller (93) for generating a select signal, and a camera.
(3); and a bit shifter (95) for converting or inversely converting the data read from the image memory (94) into the data format of each memory area. , and a bit shifter controller (96) that controls the bit shifter (95).

Next, the operation of the embodiment will be explained based on the above configuration.

First, as shown in the memory map of the image memory (94) in FIG. Assume that the user has mapped the image area to the binary image area (group 2) and the addresses 2A to 2F to the grayscale image area (group 3).

However, the number of data bits for each address is 16 bits for the table data area (group 0), 8 bits for the grayscale image area (group 1.3), and 1 bit for the binary image area (group 2). . The numbers marked with * in FIG. 2 are the addresses of the image memory (94), and the numbers in parentheses indicate the addresses when the image memory data is converted into one word and one bit.

In this embodiment, the image address shown to the user may have a different number of data bits for each area, but when actually accessing the image memory (94), all addresses have the same number of bits. The address structure must be 1 bit/word (address), and the correspondence relationship is shown in FIG.

The above mapping information is also set in the memory mapping data buffer (91), and if the group number (0 to 3) is input when accessing the image memory (94), the 1 word/bit address (a) of the first pixel of the group is set. , the image memory address (defined by the user) of the first pixel of the group (b), and the number of bits of the group 1 word (C).

In other words, a 1 bit/word address can be calculated from the information shown in FIG. 3 and the image memory address to be accessed, and the calculation formula is shown below.

1 word/bit address = a + (image memory address - b) xc This series of address conversion is performed by a 1 bit/word address converter (92
), which consists of an adder multiplier or shifter.

Furthermore, the read/write signal of the image memory (94) and the chip select signal for selecting the brain to be accessed are read/written from the image memory (94) based on the information of the memory mapping data buffer (91) and the read/write signal of the image memory (94). It is generated in the controller (93).

The image memory (94) is 1 as shown in FIG.
Consists of 6 brains (Brane O to Brain F),
This brane contains MS bits from the LSB bit (0) in Figure 2.
B-bit (F) 1-bit data is stored respectively. The brain chip select signal, which is the output of the image memory read/write controller (93), indicates which brain of this image memory (94) is to be selected, and any one of the 16 brains can be accessed (multiple times). For example, if you want to access the data at the IF address of the image memory (binary image area, group 2, number of bits 1), brain A is selected and the 1 bit data at 1 bit/word address 85 of this brain is accessed. is the data to be accessed.

The access data is then converted to the desired data format in a bit shifter (5). Figure 5 shows the concept. For example, when 1 bit of data in brane A of the image memory (94) is brought to the LSB so that it can be treated as binary image data, the bit shifter (95) The same holds true even when the data bit length is 8 bits, except for the LSB pit (bits 1 to F).

This bit shifter (95) is controlled by a bit shifter controller (96), and this control information is generated from memory mapping data buffer (1) white information and 1 bit/word address information.

FIG. 6 shows the image memory data format when the group number and image memory address are input.

In the above embodiment, the number of data bits in the image memory (94) is set to three types: 16 bits, 8 bits, and 1 bit, but any bit length may be used, and the maximum bit length may be set to 16 bits. You can do more than that.

Furthermore, it can be used in a similar manner not only in a dedicated image processing device but also in a computer or the like that uses memory.

〔Effect of the invention〕

As described above, according to the present invention, the data access of the memory is configured to support data of arbitrary bit length, so the user can configure the image memory arbitrarily.
The advantage of having a flexible image processing device that can be used for images of any size, store images containing mixed data of any bit length in any area, and freely output any data. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory access circuit of an image processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between data formats in the image memory and their addresses, and FIG. 3 is a memory mapping diagram. Figure 4 is a diagram showing the data structure in the data buffer, Figure 4 is a conceptual diagram of the image memory and bit shifter, Figure 5 is a diagram showing a conceptual example of data conversion performed by the bit shifter, and Figure 6 is a diagram showing the image address in Figure 2. Diagram showing an example of data format, 7th
The figure is a schematic configuration diagram of a general image processing device, FIG. 8 is a block diagram showing a memory access circuit of a conventional image processing device, and FIGS. 9(a) and (b) are data formats in a conventional image memory. FIG. (1) ...CPU, (2) ...Main memory,
(3)...Camera, (4)...A/D converter, (
5)...Monitor, (6)...D/A converter, (7)
...Frame memory, (8)...Graphic processor, (9)...Image memory access circuit, (10)...Image processing unit, (11)...Memory for external program, (91)・・・
・Memory mapping data buffer, (92)...1
Bit/word address converter, (93)...Image memory read/write controller, (94)...Image memory, (95)...Bit shifter controller, (96)...
...Bit shifter. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In an image processing device that captures an input image, stores it in an image memory, samples and quantizes the stored input image, and processes it into a digital signal of the image, the mapping information of the image memory is registered in advance and stored. memory mapping data storage means; address conversion means for converting mapping information of the memory mapping data storage means into an image memory address of the image memory; and an image memory of the address conversion means corresponding to read/write signals of the image memory. An image processing device comprising: data format shifting means for converting and inversely converting data read from an image memory based on an address into a data format of each memory area.