JPH09135460A - Semiconductor image memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively provide an image memory device using semiconductor memory cells with which the reducing operation of image is enabled in simple and compact configuration. SOLUTION: Y, R-Y and B-Y inputs are converted to 16 bits while using a serial/parallel converting circuit 1 and stored while using a general-purpose 1-word/16-bit width DRAM 3. The high-order bit of luminance data and the high-order bit of color difference data for one picture element are stored so as to generate the data of picture elements only by reading one or two column addresses of the DRAM 3, the luminance data of one picture element separated from the low-order bit of these data for two picture elements are stored in a 2nd address, two picture elements of remaining luminance data are stored in a 3rd address, and four picture elements are defined as one block. When reading all the stored three addresses but reducing the image at normal time, the data of reduced images are provided by the 1st or/and the 2nd addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to an image memory device using a semiconductor memory device.

[0002]

2. Description of the Related Art First, as a premise, a data structure for expressing an image to be stored in the memory device will be described. FIG. 3 is a conceptual diagram of the structure of the image data. In FIG. 3, t is the time axis and indicates the horizontal direction of the image, and the luminance signal Y is 4 pixels and the color difference signal R.
-Y and BY make up one block with one pixel at a time. In this example, Y (A1, A2, A3, A4), R-
Y (A1), BY (A3) is an A block, Y (B1,
B2, B3, B4), RY (B1), BY (B3)
B block is composed of. Then, writing is performed to the memory device in units of this block, and also when reading is performed, read control is performed in block units.

Conventionally, in the above data structure, image data for displaying an original image as a reduced image is generated, but an image memory device for storing the image data and control of writing and reading of the device. Various means are used. The conventional example is shown below.

FIG. 4 shows a conventional method using a memory called a multiport DRAM which can write and read image data at high speed. This memory is
This is a DRAM made for an image, in which the input line memory 4, the output line memory 5 and the DRAM 3'are integrated, and the data input to the line memory 4 at high speed is stored in the DRAM 3 during the horizontal blanking period. Transferred to ´
It is memorized. When reading the stored data, the data for one line is transferred from the DRAM 3 ′ to the output line memory 5 during the horizontal blanking period, and the memory data is displayed by reading from this line memory 5 at high speed. Here, reduced image data can be generated by increasing the read speed faster than the write speed. For example, by reading from the line memory 5 at a speed four times faster than writing, an image reduced to ¼ can be displayed.

FIG. 5 shows a conventional method in which general-purpose DRAMs are connected in parallel to increase the bit width to allocate a large number of pixels to one address. This memory has general-purpose DRAM connected in parallel, and 48 bits per address (4 pixels for luminance signal, 1 pixel for color difference signal, see FIG. 3).
Is configured to be able to store. Image data is stored in the memory in the state shown in FIG. Where Y
Axy is a luminance signal (Y) and represents the x-th y-th bit data in the A block, where the 8th bit is the MSB and the 1st bit is the LSB. Similarly, R represents an RY signal and B represents a BY signal.

The data input to the parallel / serial conversion circuit 1'is stored in the DRAM 3'for each address when 48 bits of data are prepared. When reading the stored data, the data is read from the DRAM 3'for each address, and four pixels of image data are displayed through the parallel-serial conversion circuit 2 '. Therefore, one address may be read every time four pixels are displayed. To reduce to 1/4 for display, 4
One pixel of the luminance signal and one pixel of the color difference signal within 8 bits may be selected and displayed. For example, YA28-21, RA18-11, BA38-3 of column address n shown in FIG.
1 is output, and then YB28 to 2 of column address n + 1
1, RB18 to 11, BB38 to 31 are output.

[0007]

The multi-port DRAM shown in the above-mentioned conventional example is more expensive than the general-purpose DRAM, and the reduction rate shown in the example using this multi-port DRAM is Accordingly, the read speed is increased, for example, in the case of reducing it to 1/4, it is necessary to read it at 4 times the writing speed, and to reduce it to 1/8, it is necessary to read at the speed of 8 times. In order to operate the circuit, it takes a great deal of cost to take measures against high frequency interference. When using general-purpose DRAMs connected in parallel,
In addition to increasing the area to be mounted on the printed circuit board, DRA
The number of pins of the LSI that controls M increases, and the device becomes expensive. The present invention has been made in view of such conventional problems, and it is an object of the present invention to provide at low cost an image memory device using a semiconductor memory element that enables a reduction operation of the image with a simple and small configuration. Let's take that issue.

[0008]

According to a first aspect of the present invention, a predetermined number of pixel groups, which are sequentially connected, are used as a block unit, and color data in each block and block data represented by luminance data of each pixel are connected. In a semiconductor image memory device storing a plurality of addresses as image data, the upper bits of the luminance data and the upper bits of the color difference data of the specific pixel in the block are stored at a specific address of the set, and stored at the specific address. The lower bit of the luminance data and the color difference data and the luminance data of the pixels other than the specific pixel are stored in an address other than the specific address forming a set, and the image data is stored by repeating the configuration of the data in a sequential block. So that the data for reduced image display can be output by reading the data at the specific address in However, by reading all the data of the addresses forming the set, the normal operation of displaying the stored image as it is is performed, and by sequentially reading the data of only the specific address in the addresses forming the set for each block, The reduced image data can be generated.

According to a second aspect of the present invention, in the first aspect of the invention, an address other than the specific address is set as a plurality of addresses, and the pixel unit data stored at the plurality of addresses is stored in one address. An image having a reduction rate different from that of claim 1 is constructed by adding a configuration for selecting an address from the plurality of addresses and reading data, and reading the data by further adding an address selected from the plurality of addresses to the specific address. It makes it possible to generate data.

According to a third aspect of the present invention, in the above second aspect, the number of the plurality of addresses included in the set is three,
Using the specific address as the start address, the second address stores the lower bits of the brightness data and the color difference data stored at the start address and the brightness data two pixels away from the start pixel, and the remaining two pixels at the third address. Is stored, and specifically shows the conditions that can be implemented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically illustrates an embodiment of the present invention. The example shown in FIG. 1 is a configuration using a general-purpose DRAM having a word width of 16 bits, and 16 bits of data are stored in one address.
The data of the image block of 4 pixels for the luminance signal and 1 pixel for the color difference signal is stored in 3 addresses with one set of address. FIG. 2 conceptually shows the storage state of image data in the DRAM 3, in which image block data is stored at each address (n to n + 2) as shown in FIG.
3 is the same as that shown in FIG. 3). Specifically, for the column address n, Y of the pixel A2
Data, R-Y data of pixel A1, and B- of pixel A3
Each upper bit of the Y data is also the column address n +
1 stores the remaining lower bits of each data of the column address n and all bits of Y data of the pixel A4, and column address n + 2 stores all bits of Y data of pixels A1 and A3. . Series-parallel conversion circuit 1
As shown in FIG. 2, when the 48-bit data is prepared, the data input to the DRAM 3 is input to the DRAM 3 every 3 addresses.
Is stored. When reading this, normally, all the data is read from the DRAM 3 at every 3 addresses, and 4 pixels of image data are displayed through the parallel / serial conversion circuit 2. Therefore, it is sufficient to read 3 addresses every time 4 pixels are displayed.

To reduce and display, the first address (the first address of the first set) out of the three addresses is D
The data is read from the RAM 3 and the parallel-serial conversion circuit 2 converts this data into a 6-bit luminance signal 1 pixel and a 5-bit color difference signal 1
It is decomposed into pixels and output. Next, an address three addresses ahead (first address of the second set) is read from the DRAM 3, and similarly, one pixel of the luminance signal and one pixel of the color difference signal are displayed, and by repeating this, reduced image data is generated. can do. In this case, since the image data for one pixel is only contained in the first address of each set, in this example in which a block is composed of image data for four pixels, the image reduced to ¼ It becomes data. More specifically, referring to FIG. 2, first, the data of the column address n is read from the DRAM 3, and YA28 to 23 and RA18 to
14, BA38-34 are output. Next, the data at the column address n + 3 is read from the DRAM 3 and YB28
-23, RB18-14, and BB38-34 are output.
In this case, the luminance signal is 6 bits and the color difference signal is 5 bits, and these become 1/4 reduced image data. Also,
In this embodiment, when reducing to ⅛, 1
After the data of the first address of the set, the data of the second set may be skipped and the data of the first address of the third set may be read. Further, in the present embodiment, in the case of reducing to 1/2, by reading out the first set of first and second addresses and the second set of first and second addresses, the luminance signal,
Both color difference signals can be reduced and displayed with 8-bit image data. Specifically, the Y data of the pixels A2 and A4 and the pixel A
All 8 of RY data and BY data of 1 and A3 respectively
The bits are read to create 1/2 reduced image data, and the pixels A1 and A3 are skipped.

[0013]

According to the first aspect of the present invention, a general-purpose DRAM can be used, which is simpler than a conventional multi-port DRAM that operates at high speed, and has a large bit width. Compared to those using DRAM,
Since the mounting area on the board is small and the board can be made compact, the cost can be reduced. Further, since the method of accommodating the image data at the specific address is devised as described above, the reduced image data can be generated by a simple operation by reading only the data of the specific address at the time of reading.

Advantageous effect of claim 2: In addition to the advantageous effect of claim 1, a method for accommodating image data at a plurality of addresses other than the specific address is further devised. By reading the data of the address selected from the inside, it is possible to generate image data having a reduction rate different from the reduction rate according to the first aspect.

Effect of claim 3 In addition to the effects of claims 1 and 2, the number of addresses in the memory is set to 3, and the method of accommodating image data at each address is specifically determined. Thus, it is possible to provide a device that generates reduced image data that does not deteriorate the image quality and that is easy to implement and that functions more effectively in terms of the device configuration.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment of the present invention as a schematic diagram.

FIG. 2 conceptually shows a storage state of image data in a DRAM 3.

FIG. 3 is a conceptual diagram of a data structure for expressing an image targeted by the memory device.

FIG. 4 is a diagram showing a conventional method using a memory called a multiport DRAM that can write and read image data at high speed.

FIG. 5 shows a conventional method in which general-purpose DRAMs are connected in parallel to increase a bit width to allocate many pixels to one address.

FIG. 6 is a conceptual diagram showing a storage state of image data in a memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Serial / parallel conversion circuit, 1 ', 2, 2' ... Parallel / serial conversion circuit, 3, 3 '... DRAM, 4 ... Input line memory,
5 ... Output line memory.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/60 H04N 1/40 D 5/907

Claims (3)

[Claims] 1. A semiconductor image memory device for storing, as image data, a series of block data represented by color difference data in each block and luminance data of each pixel, with a predetermined number of pixel groups sequentially connected as a block unit. , A plurality of addresses are stored as a set, the upper bit of the luminance data and the upper bit of the color difference data of a specific pixel in the block are stored at a specific address of the set, and the lower bit of the luminance data and the color difference data stored at the specific address and the identification A reduced image by storing the image data by repeating the data structure of storing the luminance data of pixels other than the pixels at addresses other than the specific address forming the set, and reading the data of the specific address in the set. A semiconductor image memory characterized by being capable of outputting display data. Moly equipment. 2. An address other than the specific address is set as a plurality of addresses, data of a pixel unit stored in the plurality of addresses is stored in one address, and an address is selected from the plurality of addresses to read the data. 2. A structure is added to claim 1.
A semiconductor image memory device as described. 3. The number of a plurality of addresses included in the set is 3
With the specific address as the start address, the lower bits of the brightness data and the color difference data stored at the start address and the brightness data two pixels away from the start pixel are stored in the second address, and are stored in the third address. Two
3. The semiconductor image memory device according to claim 2, wherein the brightness data of the pixel is stored.