JPH05181813A - Exclusive control bit control system - Google Patents

Abstract

PURPOSE:To prevent the running stop of the system caused by a fact that an exclusive control bit cannot be reset by setting the exclusive control bit by other processor even in the case the reset processing of the bit cannot be executed due to a fault, etc., of the processor for which the exclusive control bit is set, in a system in which one memory is shared by plural processors and exclusive control is executed. CONSTITUTION:When a processor 11 makes access to a shared memory 40, a timer circuit 21 starts counting. Subsequently, a bit in a position corresponding to the processor 11 of the shared memory 40 is set. In the case a fault, etc., are generated in the processor 11 and the bit cannot be reset, the timer circuit 21 outputs an access time-over detecting signal 201 and the output of a lock bit AND circuit 31 goes to '0'. Thus, a signal inputted to a '1' detecting circuit goes to '0' and an in-locking signal of a detecting circuit 50 becomes '0', and the exclusive control bit of other processor can be set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls an exclusive control bit so that a plurality of processors share one memory, and while one processor is accessing the memory, access of another processor is prohibited. More specifically, the present invention relates to an exclusive control bit control method that considers resetting an exclusive control bit indicating that the processor is being used when a failure occurs in a processor being accessed.

[0002]

2. Description of the Related Art A conventional exclusive control system of this type is a circuit for determining which processor is accessing by determining a plurality of processors, a shared memory used for exclusive control, and a shared memory output. It consisted of When a processor of a plurality of processors uses the shared memory, an exclusive control bit corresponding to the processor is set, and reset when the use is completed to enable access from another processor.

[0003]

By the way, in the conventional exclusive control system, when the processor which sets the exclusive control bit for use cannot execute the subsequent reset operation of the exclusive control bit due to a failure or the like, the other exclusive control system is operated. Will continue to wait for this reset.
Therefore, there is a problem that a serious accident such as the operation of the system may be stopped. An object of the present invention is to solve the above-mentioned problem. Even when a processor being accessed fails and the exclusive control bit cannot be reset, the exclusive control bit is reset by detecting it and resetting it. An object of the present invention is to provide a control method of an exclusive control bit that can prevent the system from stopping due to a failure.

[0004]

In order to achieve the above object, a control system of an exclusive control bit according to the present invention has a plurality of processors, a memory shared by the plurality of processors, and data of a specific address of the shared memory. In the exclusive control method for controlling the exclusive state of the resource by using, access is started when the corresponding processor starts counting from the time when the corresponding processor accesses the shared memory and the access signal is not continuously input until a certain time elapses. A timer circuit provided for each processor that outputs a time-over detection signal, and each processor sets a bit indicating an exclusive state at a different bit position when data is set at a specific address of the shared memory, and outputs the bit and Provided for each timer circuit that takes the logical product of access time over detection signals Including a lock bit AND circuit and a lock signal generation circuit that takes the logical sum of the outputs of the lock bit AND circuits and feeds a lock signal back to the processors, even if the processor accessing the shared memory has passed a certain time. When the bit indicating the exclusive state is not reset, the lock-in signal of the lock-in signal generation circuit is set to a signal released from the exclusive state by the access time-over detection signal of the corresponding timer circuit,
It is configured so that another processor can know the release of the exclusive state.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a circuit block diagram showing an embodiment of an exclusive control bit control system according to the present invention. The processors (1) 11 to (n) 1n are a plurality of processors that configure the system, and each processor accesses the shared memory 40. The shared memory access signals 101 to 10n are signals which become active when reading / writing from / to the shared memory 40 from the processors 11 to 1n. Timers (0) 21 to (n) 2n are shared memory access signals 10
Counting starts when 1 to 10n becomes active,
When the shared memory access signals 101 to 10n are not received for a certain period of time, the access time over detection signal 20
It is a counting circuit that sets 1 to 20n to "0". The lock bit AND circuits 31 to 3n are AND circuits that perform a logical product of the output bit of the shared memory 40 and the access time over detection signals 201 to 20n. The "1" detection circuit 50, which is a locked signal generation circuit, is a circuit that outputs the OR of the lock bit AND circuits 31 to 3n as an input, and the locked signal 301 output of this circuit is the processor (1).
11- (n) 1n.

The processors (1) 11 to (n) 1n use the shared memory 40 to manage the resources they want to occupy, and this is done by setting data at a specific address in the shared memory 40. That is, if any bit of the data at a particular address is "1", the other processor considers that resource to be used. As a result, exclusive control is performed. When setting data at a specific address of the shared memory 40, the processor (1) 11 performs exclusive control by setting bit position 0. Similarly, processor (2) 12 uses bit position 1, and sequentially using bit positions in this manner causes processor (n) 1n to use bit position n-1 for exclusive control.

Further, each processor (1) 11 to (n) 1
The n accesses the shared memory 40 at a certain time interval to indicate its normal operation. In the normal state, the processors (1) 11 to (n) 1n first share the shared memory 40.
Of the specified address, the output locked signal 301 of the "1" detection circuit 50 is input, and when the signal is "0", the bit corresponding to itself is set. On the other hand, when the locked signal 301 is "1", it is determined that another processor is occupying the shared memory 40 and waits until it becomes "0". Next, the processor (1) 11 uses the shared memory 40.
A case will be described in which the exclusive control bit of 1 is set to "1" and then the traveling is stopped due to a failure or the like. Processor (1) 1
Since 1 does not access the shared memory 40 after the fixed time, the timer circuit (0) 21 sets the access time over detection signal 201 to "0" after the fixed time.

When the processor (2) 12 reads the data of the shared memory 40 in this state, the bit 0 of the shared memory 40 is "1", but the access time over detection signal 201 is "0". Therefore, the output of the lock bit AND circuit 31 becomes "0". for that reason,
The output locked signal 301 of the "1" detection circuit 50 is "0".
Becomes This allows processor (2) 12 to determine that it is not locked and set its own lock bit.

[0009]

As described above, according to the present invention, each processor is provided with a timer circuit for starting counting when the shared memory is accessed, and the bit output corresponding to each processor of the exclusive control shared memory and its output are provided. An AND circuit that takes the logical product of the timer circuit outputs corresponding to the processors is provided, and the outputs are input, the logical sum is obtained, and the output is fed back to each processor. Therefore, the processor with the exclusive control bit set Even when the reset processing of the bit cannot be executed due to a failure or the like, it is possible to set the exclusive control bit by another processor, and it is possible to prevent the system from stopping due to the inability to reset the exclusive control bit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of an exclusive control bit control system according to the present invention.

[Explanation of symbols]

 11 ... Processor (1) 12 ... Processor (2) 1n ... Processor (n) 21 ... Timer (1) 22 ... Timer (2) 2n ... Timer (n) 40 ... Shared memory 31-3n ... Lock bit and circuit 50 ... “1” detection circuit 101 to 10n ... Shared memory access signal 201 to 20n ... Access time over detection signal 301 ... Locking signal

Claims (1)

[Claims] 1. An exclusive control method for controlling an exclusive state of a resource by using a plurality of processors, a memory shared by the plurality of processors, and data at a specific address of the shared memory, A timer circuit provided for each processor, which starts counting from the time when the shared memory is accessed, and outputs an access time over detection signal when the access signal is not continuously input until a fixed time elapses; Is a lock bit and circuit provided for each timer circuit that sets a bit indicating an exclusive state at a different bit position when data is set at a specific address in the shared memory and logically ANDs the bit output with the access time over detection signal. And taking the logical sum of the outputs of the respective lock bit and circuits,
A lock-in signal generation circuit that feeds back a lock-in signal to each of the processors, and when the processor accessing the shared memory does not reset the bit indicating the exclusive state even after a certain time has elapsed
It is configured such that the in-lock signal of the in-lock signal generation circuit is set to a signal released from the exclusive state by the access time-over detection signal of the corresponding timer circuit, and another processor can know the release of the exclusive state. Characteristic exclusive control bit control method.