JPH01187665A - Interruption system among processors - Google Patents

Abstract

PURPOSE:To execute a sure interruption control by preventing a state which cannot be distinguished from an incorrect interruption from occurring in a circuit where respective processors operate by one interruption register. CONSTITUTION:Respective processors 1-N operate by one interruption register j-2. A request source processor (i) from which an interruption to another processor is generated locks a main storage M so that the other processors cannot use it, sets the interruption control table of the main storage M, sends an interruption signal S1 and then, cancels the lock state of the main storage M. When a execution destination processor to which the requested interruption processing is executed reads out the interruption control table of the main storage M and resets it, the interruption signal S1 already comes and the interruption control table of the main storage M is not reset before before the interruption signal S1 comes. Consequently, the set state of the interruption register j-2 which cannot be distinguished from the incorrect interruption does not occur. Thus, the sure interruption control can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method between processors, and particularly to an interrupt control method between processors of an information processing apparatus having a plurality of processors.

[Conventional technology]

In an information processing apparatus having N processors, the following two methods have been implemented as conventional interrupt control methods between processors.

First, the first method is to provide each processor with N interrupt registers corresponding to each of the N processors.

In this case, when the requesting processor that has generated an interrupt request to another processor sends an interrupt signal to the execution destination processor that executes the requested interrupt processing, the N interrupt registers in the execution destination processor are The interrupt register connected to the requesting processor is set.

Therefore, the execution destination processor can identify which processor has requested an interrupt based on which interrupt register among the N interrupt registers is in the set state.

In addition, in the second method, N bits indicating an interrupt request of each processor are used as interrupt management data, and N bits of interrupt management data stored in the main memory for each processor that executes the requested interrupt processing are used. In this system, an interrupt management table is provided, and each processor is provided with one interrupt register that receives interrupt signals from N processors by ORing.

In this case, the requesting processor that has issued an interrupt request to another processor sets a bit indicating the interrupt request of the requesting processor in the interrupt management data related to the execution target processor in the interrupt management table in main memory. and sends an interrupt signal to the executing processor.

Therefore, when the interrupt register receives an interrupt signal and enters the set state, the target processor can determine which processor requested the interrupt by checking the interrupt management data related to the target processor in the interrupt management table in main memory. It can be identified by reading out.

[Problem that the invention seeks to solve]

The first method in the conventional inter-processor interrupt control method described above requires N interrupt registers for each processor, which increases the amount of hardware circuitry and increases the cost.

In the second method of the conventional inter-processor interrupt control method described above, the requesting processor changes the interrupt management table in the main memory and then sends an interrupt signal to the execution destination processor.

Therefore, the interrupt management data related to the execution target processor read by the execution target processor whose interrupt register has been set in response to an interrupt signal will have bits indicating interrupt requests of multiple requesting processors set. There may be cases.

In this case, a certain bit of the request source processor may be in the state before the interrupt signal arrives, simply because the bit of the interrupt management data is set.

However, when the execution destination processor learns of each requesting processor whose corresponding interrupt request bit is set, it resets each bit of its interrupt management data and resets the interrupt register. There are cases where an interrupt signal comes after that and only the interrupt register is set.

Although this set state of the interrupt register must be canceled, there is a problem in that such a state cannot be distinguished from an illegal interrupt caused by a hardware malfunction.

An object of the present invention is to provide an interrupt control method between processors that can perform reliable interrupt control without causing a state indistinguishable from an unauthorized interrupt using an inexpensive circuit that operates with one interrupt register for each processor. The goal is to provide the following.

[Means for solving problems]

The inter-processor interrupt control method of the present invention is provided in an information processing device having N processors and a main memory common to these processors. The first step is to lock the main memory so that processors other than the requesting processor cannot use it.
(B) Management of N interrupts stored in the main memory for each processor that executes the requested interrupt processing, using N bits indicating interrupt requests of each processor as interrupt management data. Regarding an interrupt management table configured of data, the interrupt request of the requesting processor is shown in the interrupt management data regarding the execution destination processor that operates on the requesting processor and is requested by the requesting processor to execute an interrupt. an interrupt management table setting procedure for setting a bit in a set state; (C) an interrupt signal generation procedure for operating in the request source processor and transmitting an interrupt signal for transmitting the generated interrupt request to the execution destination processor; After a sufficient period of time has elapsed for the requesting processor to operate on the requesting processor and set the interrupt register in the execution target processor with the interrupt signal, the main memory locked in the first main memory locking procedure a first main memory unlocking procedure for releasing memory; (E) operating on the execution destination processor when the interrupt register that receives interrupt signals from N processors by ORing in the execution destination processor is in a set state; do,
a second main memory locking procedure that puts the main memory into a locked state in which processors other than the execution destination processor cannot use it; (F) interrupt management data regarding the execution destination processor that operates on the execution destination processor and is in an interrupt management table; An interrupt management table reset procedure that reads the information from the main memory, learns each request source processor whose bit indicating the corresponding interrupt request is in the sent state, and resets each bit of the interrupt management data regarding the execution destination processor. , (G) an interrupt register reset procedure that operates on the execution destination processor to reset the interrupt register of the execution destination processor; (■ () operates on the execution destination processor to reset the interrupt register of the execution destination processor; a second main memory unlocking procedure for releasing the main memory locked in the locking procedure; and an interrupt processing procedure for executing interrupt processing for each request source processor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the inter-processor interrupt control method of the present invention.

Further, FIG. 2 is a block diagram showing an example of an information processing apparatus to which this embodiment is applied.

The information processing apparatus in FIG. 2 includes N processors 1.2.・
. . . N and a main memory M common to these.

In FIG. 1, first, processors 1, 2, . ......-N, one of the requesting processors i operates, and in the first main memory lock procedure A, a processor other than the requesting processor i uses the main memory M. Lock state that cannot be used.

On the other hand, FIG. 3 is an information configuration diagram for explaining the contents of the interrupt management table.

In FIG. 3, an interrupt management table P is stored on the main memory M and is stored in N processors 1, 2, . . . that execute requested interrupt processing.・・・・・・・・・Separate management data Ql + Q2 +・・・・・・QN for each N
have.

Also, one of them, interrupt management data Q, is N
processors 1, 2 . ......N bits RJl indicating N respective interrupt requests.

RJ2. ......has RJN.

Processors 1, 2, . ......If one of N is the execution destination processor j, the request source processor i operates in the interrupt management table setting procedure B in FIG. Bit R1- in data QJ indicating an interrupt request from requesting processor i is set.

Further, in interrupt signal generation procedure C, the requesting processor i operates and sends an interrupt signal for transmitting the generated interrupt request from the requesting processor i to the execution destination processor j.

FIG. 4 is a block diagram showing a route through which an interrupt signal is transmitted in this embodiment.

In FIG. 4, an interrupt signal S+ is sent from the requesting processor i to the OR circuit j-1 of the executing processor j.

Next, in the first main memory unlocking procedure, the requesting processor i operates and enough time has elapsed for the interrupt signal S1 to set the interrupt register j-2 in the execution destination processor j. After that, the main memory M locked in the first main memory lock procedure A is released.

Next, an interrupt register j receives the interrupt signals from the execution target processor j″cN processors in FIG.
~ When 2 is in the set state, its output is sent to the control circuit j
-3, the execution destination processor j operates, and in the second main memory locking procedure E, the execution destination processor j
The main memory M is locked so that other processors cannot use it.

Next, in the interrupt management table reset procedure F, the execution destination processor j operates, reads out the interrupt management data QJ related to the execution destination processor j in the interrupt management table P from the main memory M, and sets the bit R indicating the corresponding interrupt request.
The request source processor i whose jI etc. are in the set state is known, and each bit of the interrupt management data regarding the execution destination processor is reset.

Further, in the interrupt register reset procedure G, the execution destination processor j operates, and the execution destination processor j in FIG. 4 puts the interrupt register j-2 into the reset state by the output from the control circuit j-3.

Next, in a second main memory lock release procedure H, the execution destination processor j operates to release the main memory M that was locked in the second main memory lock procedure E.

Thereafter, in the interrupt processing procedure I, the execution destination processor j operates and executes the interrupt processing for each requesting processor i, etc., which was found to have requested an interrupt in the interrupt management table reset procedure F.

FIG. 5 is a timing diagram showing the operation of this embodiment.

Referring to FIG. 5, an explanation will be given of the operation in this embodiment when interrupt signals from request source processors i and k are sent to execution destination processor j.

First, when a requesting processor i issues an interrupt request to the execution destination processor j, the requesting processor

Since processor i sends a main memory lock instruction to main memory M at time 1° in the first main memory locking procedure, main memory M is in a locked state in which processors other than requesting processor i cannot use main memory M. Become.

Next, the requesting processor i sends an interrupt management table setting instruction to the main memory M at time t2 in the interrupt management table setting procedure, so the contents of the interrupt management table in the main memory M are updated, and the interrupt related to the execution target processor j is Bit RjI in management data QJ indicating an interrupt request from requesting processor i is set.

Next, the requesting processor i sends an interrupt signal to the execution destination processor j at time t3 in the interrupt signal generation procedure.
The interrupt register of execution destination processor j is set.

Next, in the first main memory lock release procedure, the requesting processor i sends a main memory lock release instruction at time t4 after the interrupt register of the execution destination processor j is set, so that the main memory M is locked. will be released from the state.

Immediately thereafter, if the requesting processor issues an interrupt request to the execution destination processor j, the requesting processor k
is the first main memory lock procedure and sends a main memory lock instruction to the main memory M at time t, so the main memory M becomes locked so that no processor other than the requesting processor can use the main memory M.

Next, the requesting processor k sends an interrupt management table setting instruction to the main memory M at time t6 in the interrupt management table setting procedure, so the contents of the interrupt management table in the main memory M are updated, and the interrupt related to the execution target processor j is The bit RJk in the management data Q, which indicates an interrupt request to the requesting processor, is set.

Next, in the interrupt signal generation procedure, the requesting processor k sends an interrupt signal to the execution destination processor j at time t7, but since the interrupt register of the execution destination processor j has already been set, it remains in that state. .

Next, the requesting processor k sends a main memory lock release instruction at time 8 in the first main memory lock release procedure, so that the main memory M is released from the locked state.

When the interrupt register is in the set state and the main memory M is released from the locked state, the execution destination processor j issues a main memory lock instruction to the main memory at time t9 in the second main memory lock procedure E. Since the main memory M is sent to M, the main memory M becomes locked so that processors other than the execution destination processor j cannot use the main memory M.

Next, in the interrupt management table reset procedure, the execution destination processor j sends an interrupt management table reset instruction to the main memory M at time tto, and indicates an interrupt request by reading the interrupt management data Q from the interrupt management table P. Since it detects that bits RJI and Rlk are set, it knows which requesting processors i and k are requesting the interrupt, and also resets this interrupt management data Q, so bit RJI indicating an interrupt request is set.
Each bit of the interrupt management data QJ including Rjk and Rjk is reset.

Next, execution destination processor j sends an interrupt register reset instruction to the interrupt register of execution destination processor j at time 111 in an interrupt register reset procedure, so that the interrupt register becomes a reset state.

Next, execution target processor j sends a main memory lock release instruction at time t1□ in the second main memory lock release procedure, so
Main memory M is released from the locked state.

Thereafter, in the interrupt processing procedure, the execution destination processor j executes the interrupt processing of the requesting processors i and k, which have learned that they have requested an interrupt in the interrupt management table reset procedure.

As described above, the inter-processor interrupt control method of the present invention operates with one interrupt register for each processor.

In addition, the requesting processor that has issued an interrupt request to another processor locks its main memory so that other processors cannot use it, sets the interrupt management table in the main memory, and sends an interrupt signal to the main memory. Since the memory lock state is released, by the time the execution destination processor that executes the requested interrupt processing reads the interrupt management table in main memory and resets it, the interrupt signal has already been received and the interrupt signal has already arrived. The interrupt management table in main memory is never reset.

For this reason, unlike the second conventional inter-processor interrupt control method, an interrupt register set state that is indistinguishable from an unauthorized interrupt 7 due to a hardware malfunction does not occur.

〔Effect of the invention〕

As explained above, the inter-processor interrupt control method of the present invention is an inexpensive circuit that operates with one interrupt register for each processor, and is reliable in that a state indistinguishable from an unauthorized interrupt does not occur. This has the effect that interrupt control can be executed.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an embodiment of the interrupt control method between processors of the present invention, FIG. 2 is a block diagram showing an example of an information processing device to which this embodiment is applied, and FIG. 3 is the contents of an interrupt management table. FIG. 4 is a block diagram showing a route through which an interrupt signal is transmitted in this embodiment, and FIG. 5 is a timing diagram showing the operation of this embodiment. 1.2. ~N... Processor, A...
First main memory locking procedure, B... Interrupt management table setting procedure, C... Interrupt signal generation procedure, D... First main memory unlocking procedure, E・・・
...Second main memory lock procedure, F...Interrupt management table reset procedure, G...Interrupt register reset procedure, H...Second main memory lock Release procedure, ■... Interrupt processing procedure, i...
...Request source processor, j...Execution destination processor, j-1...OR circuit, j-2...
...Interrupt register, j-3...Music/control circuit, M...
...Main memory, P...Interrupt management table,
Ql, Q2.

Claims (1)

[Scope of Claims] In an information processing device having N processors and a main memory common to these processors, (A) a requesting processor that has generated an interrupt request to another processor operates to process the request; The first step is to lock the main memory so that processors other than the original processor cannot use it.
(B) Management of N interrupts stored in the main memory for each processor that executes the requested interrupt processing, using N bits indicating interrupt requests of each processor as interrupt management data. Regarding an interrupt management table configured of data, the interrupt request of the requesting processor is shown in the interrupt management data regarding the execution destination processor that operates on the requesting processor and is requested by the requesting processor to execute an interrupt. an interrupt management table setting procedure for setting a bit in a set state; (C) an interrupt signal generation procedure for operating in the request source processor and transmitting an interrupt signal to the execution target processor to transmit the generated interrupt request; (D) an interrupt signal generation procedure for transmitting the generated interrupt request; The main memory that is activated in the original processor and is locked in the first main memory locking procedure after a sufficient time has elapsed for the interrupt signal to set the interrupt register in the target processor. (E) When the interrupt register that receives interrupt signals from N processors in the execution target processor by ORing is in a set state, hand,
a second main memory locking procedure that puts the main memory into a locked state in which processors other than the execution destination processor cannot use it; (F) interrupt management data regarding the execution destination processor that operates on the execution destination processor and is in an interrupt management table; An interrupt management table reset procedure that reads the information from the main memory, learns each request source processor whose bit indicating the corresponding interrupt request is set, and resets each bit of the interrupt management data regarding the execution target processor; G) an interrupt register reset procedure that operates on the execution destination processor to reset the interrupt register of the execution destination processor; (H) an interrupt register reset procedure that operates on the execution destination processor and sets the interrupt register of the execution destination processor to a reset state; a second main memory unlocking procedure for releasing the locked main memory; (I) each request that operates in the execution target processor and that is found to be requesting an interrupt in the interrupt management table reset procedure; An interrupt control method between processors, comprising: an interrupt processing procedure for respectively executing interrupt processing of a source processor.