JPH0517748U - Parallel computer - Google Patents

Abstract

(57) [Summary] [Object] The present invention aims to provide a parallel computer capable of reliably maintaining synchronization even during a branch operation. In a parallel computer having a plurality of processors 1 to 4 and a control memory 6 for controlling the processors, a branch control unit 5 is provided to receive status signals of execution results of the processors 1 to 4. Then
It is characterized in that a corresponding cancel signal is created and outputted to each of the processors 1 to 4 by the control code which is periodically called from the control memory 6 and the subsequent execution instruction is abandoned for each processor.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a parallel computer capable of branching quickly.

[0002]

[Prior Art]

 Conventionally, as a branching method for computers, branching is performed by dynamically changing the order of control codes output from the control memory based on the execution result. Note that branching is a condition in which if is executed, for example, when the calculation result is a or more, it goes to instruction A, and when it is less than a, it goes to instruction B. Is.

[0003]

[Problems to be solved by the device]

 In the conventional method, if the pipeline processing, that is, the instruction is loaded in advance so that the next processing can be performed immediately after the previous operation is completed, the subsequent instruction is executed at the time of branching. The other part of the instruction already fetched (read) into the pipeline has to be abandoned and fetched again, which takes several cycles, so that the part of is not accidentally executed. In a parallel computer in which a plurality of processors operate synchronously, it is difficult to synchronize the processors because the execution cycle changes depending on the branch in this method.

[0004]

[Means for Solving the Problems]

 The present invention creates a cancel signal corresponding to each processor by a status signal indicating the operation result of a plurality of processors forming a computer and a control code periodically called from the control memory, and executes subsequent execution instructions for each processor. Branch by abandoning.

[0005]

[Action]

 Since an instruction is abandoned at each processor at the time of execution, by pre-coding so that the abandonment of an instruction does not affect other processors, the processing can proceed without changing the order of control codes. This allows branching to be easily performed in a parallel computer in which multiple processors operate in synchronization.

[0006]

【Example】

 An example is shown in FIG. In this system, each unit 1, 2, 3, 4, 5 is controlled by control codes 9, 10, 11, 12, 13 which are periodically called from the control memory 6. A status signal 7 is output to each processor 1, 2, 3, 4 based on the execution result, and an instruction cancel signal 8 corresponding to each processor is created and supplied in the branch control unit 5 by the signal and the control code. It is possible to abandon an instruction when executing in processor units. As a result, the control code can be branched without changing the order.

[0007]

[Effect of the device]

 In this way, by abandoning instructions at the time of execution on a processor-by-processor basis, conditional branching is possible without changing the order of control codes, and branching can be easily performed on parallel computers in which multiple processors operate in synchronization. become.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel computer according to the present invention.

[Explanation of symbols]

5 ... Branch control unit, 6 ... Control memory, 7 ...
Status signal of each processor, 8 ... Instruction cancel signal, 9, 10, 11, 12, 13 ... Control code.

Claims (1)

[Scope of utility model registration request] 1. A parallel computer having a plurality of processors and a control memory for controlling the processors, receives a status signal of an execution result of each processor, and creates and outputs an instruction cancel signal to the processor based on the status signal. A parallel computer having a branch control unit.