JPH0517572B2 - - Google Patents
Info
- Publication number
- JPH0517572B2 JPH0517572B2 JP62238160A JP23816087A JPH0517572B2 JP H0517572 B2 JPH0517572 B2 JP H0517572B2 JP 62238160 A JP62238160 A JP 62238160A JP 23816087 A JP23816087 A JP 23816087A JP H0517572 B2 JPH0517572 B2 JP H0517572B2
- Authority
- JP
- Japan
- Prior art keywords
- programmable
- input
- circuit
- bus line
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000006870 function Effects 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62238160A JPS6480128A (en) | 1987-09-22 | 1987-09-22 | Programmable logic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62238160A JPS6480128A (en) | 1987-09-22 | 1987-09-22 | Programmable logic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6480128A JPS6480128A (en) | 1989-03-27 |
JPH0517572B2 true JPH0517572B2 (en, 2012) | 1993-03-09 |
Family
ID=17026078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62238160A Granted JPS6480128A (en) | 1987-09-22 | 1987-09-22 | Programmable logic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6480128A (en, 2012) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2887825B2 (ja) * | 1991-10-07 | 1999-05-10 | 日本電信電話株式会社 | ディジタル処理回路 |
-
1987
- 1987-09-22 JP JP62238160A patent/JPS6480128A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6480128A (en) | 1989-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6467017B1 (en) | Programmable logic device having embedded dual-port random access memory configurable as single-port memory | |
US6002638A (en) | Memory device having a switchable clock output and method therefor | |
US5003200A (en) | Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station | |
US4807184A (en) | Modular multiple processor architecture using distributed cross-point switch | |
CA1189978A (en) | Interchangeable interface circuitry arrangements for use with a data processing system | |
US7243175B2 (en) | I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures | |
US9018979B2 (en) | Universal digital block interconnection and channel routing | |
US5321652A (en) | Microcomputer having a dual port memory of supplying write data directly to an output | |
EP0062431B1 (en) | A one chip microcomputer | |
WO1996014619A1 (en) | Hierarchical crossbar switch | |
US4219875A (en) | Digital event input circuit for a computer based process control system | |
US6344989B1 (en) | Programmable logic devices with improved content addressable memory capabilities | |
JP3309361B2 (ja) | 高速カウンター回路 | |
KR19990035856A (ko) | I/O 핀이 n 이하인 n-비트 데이타 버스폭을 갖는 마이크로 콘트롤러와 그 방법 | |
US5113093A (en) | Semiconductor integrated circuit with multiple operation | |
JP2514365B2 (ja) | 機能ブロックのアドレスデコ−ド装置 | |
JP2953737B2 (ja) | 複数ビット並列テスト回路を具備する半導体メモリ | |
JPH0517572B2 (en, 2012) | ||
EP0105755A2 (en) | Selective accessing in data processing systems | |
JPH0393098A (ja) | 集積回路 | |
US5307475A (en) | Slave controller utilizing eight least/most significant bits for accessing sixteen bit data words | |
JPH0279294A (ja) | データ長変更可能メモリ | |
JPH02208897A (ja) | 半導体記憶装置 | |
JPS62229452A (ja) | 周辺モジユ−ルアクセス方式 | |
JP3117984B2 (ja) | 半導体不揮発性メモリ装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term | ||
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080309 Year of fee payment: 15 |