JPH05175497A - Semiconductor transistor chip - Google Patents

Abstract

PURPOSE:To cope with one type of transistor chip for various types of product line-up for respective outputs by independently disposing transistor cells having different gate widths on one transistor chip, and selecting an arbitrary cell by bonding. CONSTITUTION:Transistor cells T1-T5 have a common source electrode pad S but separate drain electrode pads D and gate electrode pads G, which are not connected by plating wirings on a transistor chip, and the cells are independently disposed. In the case of assembling a product, transistors to be used are selected according to presence or absence of bonding. Thus, products having various outputs can be coped by using one transistor chip.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a semiconductor transistor chip in a gallium arsenide field effect transistor.

[0002]

2. Description of the Related Art A conventional gallium arsenide field effect transistor (GaAs field effect transistor).
The system (hereinafter referred to as GaAsFET) has a comb structure as shown in FIG. The gates, the sources, and the drains that are electrodes are connected to each other's pads,
One transistor is formed on one pellet. The output of a comb-type transistor increases as the length of the gate fingers, in other words, the length of the combs, or the number of gate fingers (also the number of combs) increases. Since the gate finger length is about 100 μm, when transistor chips of various output product lineups are manufactured, separate transistor chips having different numbers of fingers are manufactured.

[0003]

The power transistors normally used in the microwave band are often in small quantities and in many types,
Since it is difficult to control the wafer loading and the product assembly loading, the immobilization inventory of transistor chips and the shortage of transistor chips to be loaded are likely to occur, and the following problems have been encountered when assembling conventional transistor chips into products. Since the same number of types of transistor chips as the number of products lined up for each output are required, the number of mask types increases. Transistor chips created for each output are incompatible dedicated chips with respect to required product variations, and therefore cannot be distributed to each other, and chips are likely to run short or excessive. For special custom specifications that require high output, it will be selected and assembled from the dedicated transistor chip, or it will be selected and screened after assembly,
It is easy to cause shortage of input chips or increase of immovable inventory of out-of-specification products. Since the transistor chips used in products lined up by output have different sizes, there are many types of assembling members such as mount members and packages, which complicates member management and tends to result in immobile inventory.

Therefore, in view of the above-mentioned drawbacks, a technical object of the present invention is to provide a semiconductor transistor chip in which a transistor chip used for Ga.As.FET is realized by one kind of chip.

[0005]

According to the present invention, a plurality of transistors having different gate widths are formed on a semiconductor chip, and electrodes of the transistors are insulated and arranged independently of each other. Chips are obtained. Further, according to the present invention, in the semiconductor transistor chip according to claim 1, there is obtained a semiconductor transistor chip characterized in that the transistor is a gallium arsenide field effect transistor.

That is, the transistor chip of the present invention has a structure in which several transistors having different gate widths (that is, the number of combs) are formed on the transistor chip and the electrodes of the respective transistors are arranged without being connected to each other.

[0007]

[Function] Since the transistor output increases as the gate width increases, a transistor chip with several transistors with different gate widths (hereinafter referred to as transistor cells) arranged is created, and the transistor cell is used depending on whether bonding is performed during product assembly. If is selected, one transistor chip operates as the sum of the gate widths of the respective transistor cells. Therefore, by using only one transistor chip, by changing the transistor cell to be used for bonding, various output values can be obtained. It can be adapted to the product.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a top view of a GaAsFET transistor chip according to an embodiment of the present invention. The transistor cells T _{1 to} T ₅ formed on this transistor chip are
The source electrode pad S is common, but the drain electrode pad D and the gate electrode pad G are separate from each other, and are not connected by plating wiring on the transistor chip or the like, and the transistor cells are arranged independently. .

Table 1 shows data of each transistor cell.

[0011]

[Table 1]

Only the transistor cell T ₃ has a gate width of 60.
It is 0 μm and the others are 1400 μm. Therefore, by connecting the gate electrode pad and the drain electrode pad of the transistor cell T _{3 to} the package lead by bonding, a product of 0.2 W output can be obtained, and the gate electrode pad G and the drain electrode of the transistor cells T ₂ and T ₄ can be obtained. 0.8W when pad D is bonded to the package lead
An output product is obtained, and the transistor cells T ₁ , T ₂ , T
_By bonding the gate electrode G of ₄ and T ₅ and the drain electrode pad D to the package lead, a product of 1.6 W output can be obtained. Conventionally, the product corresponding to the above three kinds of output is 3
Whereas different types of transistor chips are required, the transistor chip of the present invention can be realized with one type of transistor chip.

FIG. 2 shows a second embodiment of the GaAsFET transistor chip of the present invention. Four independent transistor cells T _{1 to} T ₄ are formed on this transistor chip, and their data are shown in Table 2.

[0014]

[Table 2]

The gate width of the transistor cell used in this transistor chip is 0.1 W by selecting an arbitrary transistor cell by bonding.
To 1.5 W, it is determined so that an arbitrary output can be obtained at 0.1 W intervals. For example, if transistor cells T ₂ , T ₄ are selected, a product of 0.6 W can be obtained, and if transistor cells T ₁ , T ₂ , T ₄ are selected, a product of 0.7 W can be obtained. Therefore, it becomes possible to deal with 15 kinds of product outputs within the range of 0.1 W to 1.5 W with one transistor chip.

[0016]

As described above, according to the present invention, the transistor cells having different gate widths are independently arranged on one transistor chip, and an arbitrary transistor cell is selected by bonding, so that the lineup is made for each output. Since one type of transistor chip can be used for several types of products, it is possible to solve the problems (1) to (3) described in the section “Problems to be solved by the invention”.

[Brief description of drawings]

FIG. 1 is a top external view of a first embodiment of a transistor chip of the present invention.

FIG. 2 is a top view of a transistor chip according to a second embodiment of the present invention.

FIG. 3 is an example of a conventional transistor chip.

[Explanation of symbols]

D drain electrode pad G gate electrode pad S source electrode pad T _{1 to} T ₅ transistor cell

Claims (2)

[Claims] 1. A semiconductor transistor chip, wherein a plurality of transistors having different gate widths are formed on a semiconductor chip and electrodes of the transistors are insulated from each other and arranged independently of each other. 2. The semiconductor transistor chip according to claim 1, wherein the transistor is a gallium arsenide field effect transistor.