JPH05175492A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05175492A JPH05175492A JP3355790A JP35579091A JPH05175492A JP H05175492 A JPH05175492 A JP H05175492A JP 3355790 A JP3355790 A JP 3355790A JP 35579091 A JP35579091 A JP 35579091A JP H05175492 A JPH05175492 A JP H05175492A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- conductive film
- polycrystalline
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置、特に、イ
ンバースT型トランジスタの製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing an inverse T-type transistor.
【0002】[0002]
【従来の技術】ドレイン電界を緩和してホットキャリア
効果を低減させるトランジスタとして、LDD構造のト
ランジスタが従来から知られている。ところが、絶縁膜
でゲート電極の側壁が形成されており且つこの側壁が低
濃度拡散層上に位置しているLDD構造では、側壁に注
入されたホットキャリアのために相互コンダクタンスが
通常のトランジスタよりも却って早期に劣化することが
知られてきた。2. Description of the Related Art As a transistor for relaxing a drain electric field and reducing a hot carrier effect, an LDD structure transistor has been conventionally known. However, in the LDD structure in which the sidewall of the gate electrode is formed of the insulating film and the sidewall is located on the low-concentration diffusion layer, the mutual conductance is higher than that of a normal transistor due to the hot carriers injected into the sidewall. On the contrary, it has been known to deteriorate early.
【0003】このため、この様な相互コンダクタンスの
早期劣化を防止するために、ゲート電極を低濃度拡散層
上にオーバラップさせたGOLD構造が考え出された。
しかし、このGOLD構造には、ゲートオーバラップ容
量がLDD構造よりも増加するという欠点が構造上から
存在している。Therefore, in order to prevent such early deterioration of mutual conductance, a GOLD structure has been devised in which a gate electrode is overlapped with a low concentration diffusion layer.
However, this GOLD structure has a structural defect that the gate overlap capacitance is increased as compared with the LDD structure.
【0004】そこで、図2に示す様に、ゲート電極11
を低濃度拡散層12上にオーバラップさせるが、チャネ
ル領域上のゲート絶縁膜13よりも低濃度拡散層12上
のゲート絶縁膜14の方を若干厚くすることによって、
ゲートオーバラップ容量を低減させたインバースT型ト
ランジスタが提案されている(例えば、平成2年秋季第
51回応用物理学会学術講演会予稿集pp575 26
p−G−5「インバースT型トランジスタのゲート・オ
ーバラップ容量の低減化」)。Therefore, as shown in FIG. 2, the gate electrode 11
Are overlapped on the low concentration diffusion layer 12, but the gate insulating film 14 on the low concentration diffusion layer 12 is made slightly thicker than the gate insulating film 13 on the channel region.
An inverse T-type transistor with a reduced gate overlap capacitance has been proposed (for example, Proceedings of the 51st Annual Meeting of the Society of Applied Physics, Autumn 1990, pp 575 26).
p-G-5 "Reduction of gate overlap capacitance of inverse T-type transistor").
【0005】[0005]
【発明が解決しようとする課題】ところが、上記の文献
からも明らかな様に、インバースT型トランジスタにつ
いては、未だその製造方法が確立されておらず、シミュ
レーションによって検討されるに止まっている。従って
本発明は、インバースT型トランジスタを再現性よく製
造することができる方法を提供することを目的としてい
る。However, as is clear from the above-mentioned documents, the manufacturing method of the inverse T-type transistor has not been established yet, and it is only studied by simulation. Therefore, it is an object of the present invention to provide a method capable of manufacturing an inverse T-type transistor with good reproducibility.
【0006】[0006]
【課題を解決するための手段】本発明による半導体装置
の製造方法では、半導体基板の第1導電型の活性領域上
に第1の絶縁膜と第1の導電膜と第2の絶縁膜とを順次
に積層させ、ゲート電極を形成すべき領域における前記
第2の絶縁膜と前記第1の導電膜と前記第1の絶縁膜と
を除去して溝部を形成し、この溝部の底部に前記第1の
絶縁膜よりも薄い第3の絶縁膜を形成し、前記溝部を第
2の導電膜で埋めた後に前記第2の絶縁膜を除去し、不
純物濃度が相対的に低い第2導電型の第1の拡散層を、
前記第2の導電膜をマスクにして前記活性領域に形成
し、前記第1の絶縁膜と前記第1の導電膜とこの第1の
導電膜上の第4の絶縁膜とから成る側壁を前記第2の導
電膜の側面に形成し、不純物濃度が相対的に高い第2導
電型の第2の拡散層を、前記第2の導電膜と前記側壁と
をマスクにして前記活性領域に形成する。In a method of manufacturing a semiconductor device according to the present invention, a first insulating film, a first conductive film and a second insulating film are formed on a first conductivity type active region of a semiconductor substrate. The second insulating film, the first conductive film, and the first insulating film in the region where the gate electrode is to be formed are sequentially removed to form a groove, and the groove is formed at the bottom of the groove. A third insulating film thinner than the first insulating film is formed, and the second insulating film is removed after filling the groove portion with the second conductive film. The first diffusion layer,
The second conductive film is used as a mask to form in the active region, and a sidewall formed of the first insulating film, the first conductive film, and a fourth insulating film on the first conductive film is formed. A second diffusion layer of the second conductivity type, which is formed on the side surface of the second conductive film and has a relatively high impurity concentration, is formed in the active region by using the second conductive film and the sidewall as a mask. ..
【0007】[0007]
【作用】本発明による半導体装置の製造方法では、第2
の導電膜とこの第2の導電膜の側面の一部にコンタクト
する第1の導電膜とでゲート電極を形成し、第2の導電
膜下の第3の絶縁膜と第1の導電膜下の第1の絶縁膜と
でゲート絶縁膜を形成し、第1の絶縁膜下の低不純物濃
度の第1の拡散層とその外側の高不純物濃度の第2の拡
散層とでソース・ドレインを形成する。そして、第3の
絶縁膜よりも第1の絶縁膜の方が厚いので、チャネル領
域上のゲート絶縁膜よりも低不純物濃度の第1の拡散層
上のゲート絶縁膜の方が厚くなる。In the method of manufacturing a semiconductor device according to the present invention, the second
Forming a gate electrode with the conductive film of the second conductive film and the first conductive film contacting a part of the side surface of the second conductive film, and the third insulating film below the second conductive film and the first conductive film below the first conductive film. Forming a gate insulating film with the first insulating film, and forming the source / drain with the first diffusion layer having a low impurity concentration under the first insulating film and the second diffusion layer having a high impurity concentration outside thereof. Form. Since the first insulating film is thicker than the third insulating film, the gate insulating film on the first diffusion layer having a low impurity concentration is thicker than the gate insulating film on the channel region.
【0008】[0008]
【実施例】以下、インバースT型トランジスタの製造に
適用した本発明の一実施例を、図1を参照しながら説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention applied to the manufacture of an inverse T-type transistor will be described below with reference to FIG.
【0009】本実施例では、図1(a)に示す様に、L
OCOS法等の従来公知の方法によってSi基板21に
活性領域22を形成し、活性領域22の表面を熱酸化し
てこの表面に厚さ400Å程度のSiO2 膜23を形成
する。In this embodiment, as shown in FIG.
The active region 22 is formed on the Si substrate 21 by a conventionally known method such as the OCOS method, and the surface of the active region 22 is thermally oxidized to form the SiO 2 film 23 having a thickness of about 400 Å on this surface.
【0010】その後、厚さ500Å程度の多結晶Si膜
24と厚さ3000Å程度のSiO2 膜25とを、CV
D法で全面に順次に堆積させる。そして、SiO2 膜2
5上でフォトレジスト26をゲート電極のパターンに加
工する。Then, a polycrystalline Si film 24 having a thickness of about 500Å and a SiO 2 film 25 having a thickness of about 3000Å are CV
The entire surface is sequentially deposited by the D method. Then, the SiO 2 film 2
The photoresist 26 is processed into a pattern of the gate electrode on 5.
【0011】次に、図1(b)に示す様に、フォトレジ
スト26をマスクにして、SiO2 膜25と多結晶Si
膜24とSiO2 膜23とを順次にエッチングし、これ
らの膜を除去することによって、ゲート電極のパターン
の溝部27を形成する。Next, as shown in FIG. 1B, with the photoresist 26 as a mask, the SiO 2 film 25 and the polycrystalline Si are formed.
The film 24 and the SiO 2 film 23 are sequentially etched, and these films are removed to form the groove 27 of the pattern of the gate electrode.
【0012】その後、フォトレジスト26を除去し、溝
部27の底部に露出した活性領域22の表面を熱酸化し
て、溝部27の底部に厚さ200Å程度のSiO2 膜3
1を形成する。そして、厚さ5000Å程度の多結晶S
i膜32をCVD法で全面に堆積させ、この多結晶Si
膜32に不純物を導入する。従って、多結晶Si膜32
と多結晶Si膜24とが、溝部27の内側面で互いにコ
ンタクトする。After that, the photoresist 26 is removed, and the surface of the active region 22 exposed at the bottom of the groove 27 is thermally oxidized to form the SiO 2 film 3 having a thickness of about 200Å at the bottom of the groove 27.
1 is formed. And, a polycrystalline S having a thickness of about 5000Å
The i film 32 is deposited on the entire surface by the CVD method, and the polycrystalline Si
Impurities are introduced into the film 32. Therefore, the polycrystalline Si film 32
And the polycrystalline Si film 24 contact each other on the inner surface of the groove 27.
【0013】次に、多結晶Si膜32の全面をエッチバ
ックすることによって、溝部27のみを多結晶Si膜3
2で埋める。そして、SiO2 膜25を弗酸でエッチン
グすることによって、図1(c)に示す様に、このSi
O2 膜25を除去する。この結果、多結晶Si膜32が
多結晶Si膜24から突出する。Next, by etching back the entire surface of the polycrystalline Si film 32, only the groove 27 is formed in the polycrystalline Si film 3.
Fill with 2. Then, by etching the SiO 2 film 25 with hydrofluoric acid, as shown in FIG.
The O 2 film 25 is removed. As a result, the polycrystalline Si film 32 projects from the polycrystalline Si film 24.
【0014】その後、多結晶Si膜24とSiO2 膜2
3とを透過することができる程度のエネルギで、多結晶
Si膜32をマスクにして、活性領域22とは反対導電
型の不純物33を、活性領域22に低濃度にイオン注入
する。この結果、活性領域22に低濃度拡散層34が形
成される。After that, the polycrystalline Si film 24 and the SiO 2 film 2 are formed.
Using the polycrystalline Si film 32 as a mask, an impurity 33 having a conductivity type opposite to that of the active region 22 is ion-implanted into the active region 22 at a low concentration with an energy that can pass through 3 and 3. As a result, the low concentration diffusion layer 34 is formed in the active region 22.
【0015】次に、厚さ2000Å程度のSiO2 膜3
5をCVD法で全面に堆積させ、このSiO2 膜35の
全面をエッチバックすることによって、図1(d)に示
す様に、SiO2 膜35から成る側壁を多結晶Si膜3
2の側面に形成する。Next, the SiO 2 film 3 having a thickness of about 2000Å
5 is deposited on the entire surface by the CVD method and the entire surface of the SiO 2 film 35 is etched back, so that the side wall of the SiO 2 film 35 is covered with the polycrystalline Si film 3 as shown in FIG.
It is formed on the side surface of 2.
【0016】そして、SiO2 膜35から成る側壁をマ
スクにして、多結晶Si膜24とSiO2 膜23とをエ
ッチングする。この結果、SiO2 膜23と多結晶Si
膜24とSiO2 膜35とから成る側壁が、多結晶Si
膜32の側面に形成される。Then, the polycrystalline Si film 24 and the SiO 2 film 23 are etched by using the side wall made of the SiO 2 film 35 as a mask. As a result, the SiO 2 film 23 and the polycrystalline Si
The side wall composed of the film 24 and the SiO 2 film 35 is made of polycrystalline Si.
It is formed on the side surface of the film 32.
【0017】その後、多結晶Si膜32とSiO2 膜2
3、多結晶Si膜24及びSiO2 膜35から成る側壁
とをマスクにして、不純物33と同一導電型の不純物3
6を、活性領域22に高濃度にイオン注入する。この結
果、活性領域22に高濃度拡散層37が形成される。After that, the polycrystalline Si film 32 and the SiO 2 film 2 are formed.
3, the side wall composed of the polycrystalline Si film 24 and the SiO 2 film 35 is used as a mask, and the impurity 3 having the same conductivity type as the impurity 33 is used.
6 is ion-implanted into the active region 22 at a high concentration. As a result, the high concentration diffusion layer 37 is formed in the active region 22.
【0018】以上の様な実施例で、多結晶Si膜32、
24をゲート電極とし、SiO2 膜31、23をゲート
絶縁膜とし、高濃度拡散層37及び低濃度拡散層34を
ソース・ドレインとするインバースT型トランジスタが
製造された。In the above embodiment, the polycrystalline Si film 32,
An inverse T-type transistor having 24 as a gate electrode, SiO 2 films 31 and 23 as a gate insulating film, and a high concentration diffusion layer 37 and a low concentration diffusion layer 34 as a source / drain was manufactured.
【0019】[0019]
【発明の効果】本発明による半導体装置の製造方法で
は、チャネル領域上のゲート絶縁膜よりも低不純物濃度
の第1の拡散層上のゲート絶縁膜の方が厚くなるので、
インバースT型トランジスタを再現性よく製造すること
ができる。In the method of manufacturing a semiconductor device according to the present invention, the gate insulating film on the first diffusion layer having a low impurity concentration is thicker than the gate insulating film on the channel region.
The inverse T-type transistor can be manufactured with good reproducibility.
【図1】本発明の一実施例を順次に示す側断面図であ
る。FIG. 1 is a side sectional view sequentially showing an embodiment of the present invention.
【図2】本発明を適用し得るインバースT型トランジス
タの模式的な側断面図である。FIG. 2 is a schematic side sectional view of an inverse T-type transistor to which the present invention can be applied.
21 Si基板 22 活性領域 23 SiO2 膜 24 多結晶Si膜 25 SiO2 膜 27 溝部 31 SiO2 膜 32 多結晶Si膜 34 低濃度拡散層 35 SiO2 膜 37 高濃度拡散層21 Si substrate 22 Active region 23 SiO 2 film 24 Polycrystalline Si film 25 SiO 2 film 27 Groove portion 31 SiO 2 film 32 Polycrystalline Si film 34 Low concentration diffusion layer 35 SiO 2 film 37 High concentration diffusion layer
Claims (1)
第1の絶縁膜と第1の導電膜と第2の絶縁膜とを順次に
積層させ、 ゲート電極を形成すべき領域における前記第2の絶縁膜
と前記第1の導電膜と前記第1の絶縁膜とを除去して溝
部を形成し、 この溝部の底部に前記第1の絶縁膜よりも薄い第3の絶
縁膜を形成し、 前記溝部を第2の導電膜で埋めた後に前記第2の絶縁膜
を除去し、 不純物濃度が相対的に低い第2導電型の第1の拡散層
を、前記第2の導電膜をマスクにして前記活性領域に形
成し、 前記第1の絶縁膜と前記第1の導電膜とこの第1の導電
膜上の第4の絶縁膜とから成る側壁を前記第2の導電膜
の側面に形成し、 不純物濃度が相対的に高い第2導電型の第2の拡散層
を、前記第2の導電膜と前記側壁とをマスクにして前記
活性領域に形成する半導体装置の製造方法。1. A first insulating film, a first conductive film, and a second insulating film are sequentially stacked on an active region of the first conductivity type of a semiconductor substrate, and the gate electrode is formed in a region where the gate electrode is to be formed. A groove is formed by removing the second insulating film, the first conductive film, and the first insulating film, and a third insulating film thinner than the first insulating film is formed at the bottom of the groove. Then, after filling the groove portion with the second conductive film, the second insulating film is removed, and the second conductive type first diffusion layer having a relatively low impurity concentration is formed on the second conductive film. The side wall of the first conductive film, the first conductive film, and the fourth insulating film on the first conductive film is formed on the active region by using a mask as a side surface of the second conductive film. And forming a second diffusion layer of the second conductivity type having a relatively high impurity concentration by using the second conductive film and the sidewall as a mask. A method of manufacturing a semiconductor device formed in an active region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3355790A JPH05175492A (en) | 1991-12-20 | 1991-12-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3355790A JPH05175492A (en) | 1991-12-20 | 1991-12-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05175492A true JPH05175492A (en) | 1993-07-13 |
Family
ID=18445766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3355790A Withdrawn JPH05175492A (en) | 1991-12-20 | 1991-12-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05175492A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007524984A (en) * | 2003-01-15 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Low GIDLMOSFET structure and manufacturing method |
-
1991
- 1991-12-20 JP JP3355790A patent/JPH05175492A/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007524984A (en) * | 2003-01-15 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Low GIDLMOSFET structure and manufacturing method |
JP4678875B2 (en) * | 2003-01-15 | 2011-04-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | MOSFET device with low gate induced drain leakage (GIDL) current |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |