JPH0516618B2 - - Google Patents

Info

Publication number
JPH0516618B2
JPH0516618B2 JP58125345A JP12534583A JPH0516618B2 JP H0516618 B2 JPH0516618 B2 JP H0516618B2 JP 58125345 A JP58125345 A JP 58125345A JP 12534583 A JP12534583 A JP 12534583A JP H0516618 B2 JPH0516618 B2 JP H0516618B2
Authority
JP
Japan
Prior art keywords
data
address
register
butterfly
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58125345A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6017563A (ja
Inventor
Ryohei Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP58125345A priority Critical patent/JPS6017563A/ja
Publication of JPS6017563A publication Critical patent/JPS6017563A/ja
Publication of JPH0516618B2 publication Critical patent/JPH0516618B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP58125345A 1983-07-09 1983-07-09 バタフライ演算回路 Granted JPS6017563A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58125345A JPS6017563A (ja) 1983-07-09 1983-07-09 バタフライ演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58125345A JPS6017563A (ja) 1983-07-09 1983-07-09 バタフライ演算回路

Publications (2)

Publication Number Publication Date
JPS6017563A JPS6017563A (ja) 1985-01-29
JPH0516618B2 true JPH0516618B2 (enrdf_load_html_response) 1993-03-04

Family

ID=14907814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58125345A Granted JPS6017563A (ja) 1983-07-09 1983-07-09 バタフライ演算回路

Country Status (1)

Country Link
JP (1) JPS6017563A (enrdf_load_html_response)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378744A (en) * 1976-12-23 1978-07-12 Fujitsu Ltd Arithmetic system for complex number

Also Published As

Publication number Publication date
JPS6017563A (ja) 1985-01-29

Similar Documents

Publication Publication Date Title
JP7074363B2 (ja) 準同型暗号下での安全な計算を加速するための準同型処理ユニット（ｈｐｕ）
US6629117B2 (en) Method for computing a fast fourier transform and associated circuit for addressing a data memory
US4689762A (en) Dynamically configurable fast Fourier transform butterfly circuit
US6366936B1 (en) Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm
US5457805A (en) Microcomputer enabling high speed execution of product-sum operation
JP2002152014A (ja) 正規最小平均二乗アルゴリズムに基づいた係数適応用ハードウエアアクセリレータ
US6463451B2 (en) High speed digital signal processor
EP0588726A2 (en) Discrete cosine transformation system and inverse discrete cosine transformation system, having simple structure and operable at high speed
CA1321838C (en) Apparatus and method for flexible control of digital signal processing devices
US6549925B1 (en) Circuit for computing a fast fourier transform
US20040128335A1 (en) Fast fourier transform (FFT) butterfly calculations in two cycles
JPH0516618B2 (enrdf_load_html_response)
KR0147758B1 (ko) Mpeg-2 오디오 복호화기의 합성 필터
US5204962A (en) Processor with preceding operation circuit connected to output of data register
KR19990077845A (ko) 파이프라인된 고속 푸리에 변환 프로세서
KR101100753B1 (ko) 부스 곱셈기
Bowlyn et al. A novel distributed arithmetic approach for computing a radix-2 FFT butterfly implementation
JPS6243774A (ja) デ−タ処理装置
JP2697619B2 (ja) Ｎポイントｆｆｔ専用プロセッサ
JPS60129890A (ja) デイジタル信号処理装置
JP3654622B2 (ja) Ｄｃｔ演算装置及びｉｄｃｔ演算装置
JP3428334B2 (ja) デジタル信号処理装置
JPH026089B2 (enrdf_load_html_response)
KR940007569B1 (ko) 행렬 곱셈 회로
JPS60164868A (ja) 高速フ−リエ変換装置