JPH05165638A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate a processing by advancing the processing while decoding a stored instruction at a branching destination when new instruction address information is matching to the address information of the stored branching instruction. CONSTITUTION:A comparator 15 detects whether the new instruction address information this time is same as the instruction address information of the branching instruction executed in the past or not by comparing the branching instruction address information read from a storage device 12 with high-order address information inputted from an instruction address control part 11. When a matching detecting signal is outputted from the comparator 15 and the new address information this time shows the instruction address of the branching instruction executed in the past, a control circuit 19 instructs it to an instruction fetch unit 2 to fetch the instruction of an address shown by the branching destination address information read from a branching destination address storage device 13 and held in a register 16, namely, to fetch the branching destination instruction as prediction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for processing instructions one after another by a pipeline control method, and more particularly to an instruction at a branch destination of a branch instruction which causes disturbance of the pipeline. The present invention relates to a preemptive information processing apparatus.

[0002]

2. Description of the Related Art Conventionally, as one of the methods for rapidly processing branch instructions in an information processing apparatus that processes data one after another by a pipeline control method, address information of branch instructions executed in the past and the branch information thereof are used. When the branch instruction is decoded by the preceding operation unit by storing it as a pair with the preceding address information, it is determined whether the branch address information paired with the instruction address information of the branch instruction is registered. , If it is registered, the branch destination address information is used to calculate the branch destination instruction before the effective address information of the branch destination calculated using the address part in the branch instruction word is obtained. Read request, the branch destination instruction is read one cycle earlier than the read timing based on the calculated effective address information of the branch destination instruction, and then the effective address information is registered. The address information of the registered branch destination is compared to verify whether the registered address information of the branch destination was correct. If it is correct, the branch destination instruction read from the storage device is regarded as valid. There is a method in which a branch destination instruction that is decoded and read out with effective address information if it is not correct is decoded after one cycle, and the process proceeds according to the decoding result.

As an information processing apparatus for prefetching a branch target instruction of such a branch instruction, for example, Japanese Patent Laid-Open No. 3-4272.
There is one disclosed in Japanese Patent Publication No.

[0004]

However, in the above-mentioned conventional technique, since the address information of the branch instruction executed in the past and the address information of the branch destination are only registered, the effective address of the branch destination is registered. However, there is a problem in that the overhead to the storage device storing various instructions cannot be reduced.

That is, as shown in the time chart of FIG. 5, when the instruction decoding cycle is D, the address calculation cycle is A, the memory read cycle is B, the data transfer cycle is L, and the operation cycle is E, When a new branch instruction is read, if the same branch instruction has not been executed in the past, as shown in FIG. 3A, the branch destination instruction is the address calculation cycle A, the memory after the branch instruction is decoded. Decoding is performed after three cycles of a read cycle B and a data transfer cycle L have passed. On the other hand, when the same branch instruction has been executed in the past, the branch destination instruction is read by the registered branch destination address information, so that the branch instruction is decoded as shown in FIG. 3B. Then, it is decoded after one cycle of the address calculation cycle A.

From the above, the overhead of calculating the effective address of the branch destination can be eliminated, but
It is not possible to reduce the overhead on the storage device that stores various instructions.

An object of the present invention is to use a pipeline type data
An object of the present invention is to provide an information processing device capable of reducing overhead to a storage device storing various instructions in a device that performs data processing.

[0008]

In order to achieve the above object, the present invention stores the address information of a branch instruction executed in the past and the address information of the branch destination as a pair, and stores new instruction address information. When the address information of the stored branch instruction matches, the information processing apparatus that reads the branch destination instruction using the stored branch destination address information stores the branch destination instruction in pair with the branch destination address information. When the new instruction address information coincides with the address information of the stored branch instruction, the instruction of the branch destination stored in the storage means is decoded to proceed the processing.

[0009]

According to the above means, when the new instruction address information coincides with the address information of the branch instruction executed in the past, the instruction of the branch destination stored in the storage means is decoded and the processing is advanced. Overhead can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an embodiment of an information processing apparatus according to the present invention. In the figure, 1 is a storage device for storing various instructions, 2 is a read request to the storage device 1 through a signal line 50, a required instruction is read out through a signal line 51, and is stored in an internal instruction buffer 3. It is an instruction fetch unit. The instruction fetch unit 2 is an instruction fetch unit capable of reading a preceding instruction having an instruction buffer 3 in the unit, and an instruction word sent from the storage device 1 via the signal line 51 is distinguished according to its purpose. The instruction buffer 3 is successively stacked.

4 is a selector, 5 is a register, the selector 4 normally selects the instruction fetch unit 2 side, and the signal line 52 from the instruction buffer 3 of the instruction fetch unit 2 is selected.
The instruction word output through is stored in the register 5. In this case, the command word is composed of a command part and an address part, and the address part represents the effective address by a relative address value. The branch instruction is composed of a branch instruction code 60, a branch condition section 61, and an address section 62, as shown in FIG.

Reference numeral 6 is an instruction decoder for decoding the instruction word held in the register 5. In the case of a branch instruction, a signal indicating this is input to the branch determination circuit 7 through the signal line 53.

The branch judging circuit 7 judges whether or not the branch is prohibited by the branch condition part when the instruction word held in the register 5 is a branch instruction.
If the branch instruction is not prohibited by the branch condition part, a signal indicating that is input to the control circuit 19, the branch instruction address storage device 12, and the branch destination address storage device 13 described later through the signal line 54.

Reference numeral 8 denotes an address calculator for calculating the address of the branch destination based on the address part when the branch instruction is held in the register 5, and the calculated address information of the branch destination is held in the register 9. After that, it is input to the instruction fetch unit 2 and the branch destination address storage device 12 described later via the signal line 55. The instruction fetch unit 2 fetches the branch destination instruction indicated by the branch destination address information input from the register 9 only when the fetch instruction signal is given from the control circuit 19. Further, the branch destination address storage device 12 stores the branch destination address information input from the register 9 as the branch destination address information of the branch instruction executed in the past only when the branch instruction satisfies the branch condition.

Reference numeral 10 indicates whether or not the past branch destination address information read from the branch destination address storage device 13 matches the partial branch destination address information calculated by the address calculator 8 and held in the register 9. If it does not match, the control circuit 19 is instructed via the signal line 56 to invalidate the branch destination address information read from the branch destination address storage device 13 prior to the address calculation of the address calculator 8. Give instructions.

Reference numeral 11 is an instruction address which is divided into upper and lower instruction address information for sequentially reading various instructions from the storage device 1 and is input to a branch instruction address storage device 12, a branch destination address storage device 13 and a comparator 15. This is a control unit, and higher order instruction address information is input to the comparator 15 and also to the branch instruction address storage device 12 as storage information. The lower instruction address information is input to the branch instruction address storage device 12, the branch destination address storage device 13 and the branch destination instruction storage device 14 as a write address designation signal.

Reference numeral 12 is a branch instruction address storage device for storing instruction address information of a branch instruction executed in the past, more specifically, upper address information thereof. The upper address information AA is lower address information BB as shown in FIG. It is written to the specified storage address. Therefore, this branch instruction address storage device 12 can store the same number of address information of the branch instructions executed in the past as the number of addresses that can be designated by the lower address information of the instruction address information.

Reference numeral 13 denotes a branch destination address storage device for storing the branch destination address information of the branch instruction executed in the past. The storage information is input from the register 9 and the write address is designated by the lower address information of the instruction address information. To be done. Like the storage device 12, the branch destination address storage device 13 can store the same number of past branch destination address information items as the number of addresses that can be designated by the lower address information of the instruction address information, as shown in FIG. Moreover, the stored high-order address information and the branch destination address information are in a one-to-one relationship.
It corresponds to.

Reference numeral 14 denotes a branch destination instruction storage device that stores a branch destination instruction in a branch instruction that has been executed in the past. The stored branch destination instruction is input from the instruction fetch unit 2 via the signal line 57, and its writing is performed. The address is specified by the lower address information of the instruction address information. Like the storage device 12, the branch destination instruction storage device 14 can store the same number of past branch destination instruction information as the number of addresses that can be designated by the lower address information of the instruction address information, as shown in FIG. Moreover, the stored information and the branch destination address information have a one-to-one correspondence.

Reference numeral 15 indicates whether or not the new instruction address information matches the instruction address information of the branch instruction that has been executed in the past, in other words, whether the instruction currently being executed has executed in the past. It is a comparator that detects whether it is the same as a branch instruction. That is,
In the branch instruction address storage device 12, as shown in FIG. 4, the upper address information AA of the instruction address information is written in the BB address designated by the lower address information BB. Therefore, when new instruction address information is given this time, the lower address information BB is the same, and "A" is added from the storage address specified by the lower address information BB in the past.
When the information "A" is read, it can be considered that the instruction to be executed this time is the same as the branch instruction that has been executed in the past. The comparator 15 detects this, and the coincidence detection signal in the case of coincidence is input to the control circuit 19 via the signal line 58.

Reference numeral 16 is a register for holding past branch destination address information read from the branch destination address storage device 13 as a prediction of the branch destination of the present branch instruction. The held branch destination address information is compared. Input to the container 10.

Reference numeral 17 is a register for holding the branch destination instruction read out earlier as the predicted branch destination instruction from the branch destination instruction storage device 14 before reading the instruction of the branch destination address of the present branch instruction from the storage device 1. , 18 are comparators that detect whether the predicted branch destination instruction held in the register 17 is the same as the branch destination instruction that actually accessed the memory device 1 and read it. If the two do not match, the control circuit 19 is notified through the signal line 59, and the control circuit 19 cancels the predicted branch destination instruction.

Reference numeral 19 indicates that when the new instruction this time is the same as the branch instruction executed in the past, the instruction at the branch destination of the new instruction is fetched, or the selector 4 stores the branch destination instruction. It is a control circuit that performs control such as switching to the device 14 side or instructing the instruction buffer 3 to cancel the fetched instruction when the predicted branch destination instruction is different.

Next, the operation of the above configuration will be described with reference to FIG.
The time chart will be described.

First, when new instruction address information is input and the branch instruction and the instruction at the subsequent branch destination are fetched into the instruction buffer 3 of the instruction fetch unit 2, the instruction fetch unit 2 first signals the branch instruction. Line 52,
Input to the register 5 through the selector 4. Register 5
Fetches and holds the input branch instruction, and
Type in da 6. The instruction decoder 6 decodes the input instruction and inputs a signal indicating a branch instruction to the branch determination circuit 7 through the signal line 53. The branch determination circuit 7 checks whether or not the branch condition described in the branch condition part of the branch instruction is satisfied, and if the branch instruction is not prohibited, inputs a signal indicating that to the control circuit 19. To do.

The branch instruction held in the register 5 is also input to the address calculator 8 in parallel with the instruction decoder 6. Therefore, the address calculator 8 calculates the effective address based on the address portion of the input branch instruction and stores it in the register 9.

On the other hand, the instruction address control unit 11 inputs the higher-order address information of the newly input instruction address information to the comparator 115 and the branch instruction address storage device 12. Further, the lower address information is stored in the storage devices 12, 13,
It is inputted as a read address signal to 14. As a result, the address information of the branch instruction executed in the past, the address information of the branch destination, and the instruction of the branch destination are read from the storage devices 12, 13, and 14, respectively.

Therefore, the comparator 15 determines whether or not the new instruction address information of this time is the same as the instruction address information of the branch instruction executed in the past, by referring to the branch instruction address information and the instruction address read from the storage device 12. The detection is performed by comparing the higher-order address information input from the control unit 11. As a result, if they are not the same, that is, if the new instruction address information this time indicates the instruction address of an instruction that has not been executed in the past, the control circuit 19 outputs an output from the comparator 15 indicating that. Based on the signal, the storage devices 12 and 13 are put into the write state through the signal line 60 on condition that the signal indicating the branch instruction is input from the branch determination circuit 7.

Then, as described with reference to FIG. 4, the storage circuit 12 stores, in the storage address corresponding to the lower address information of the instruction address information of this time, the upper address information as the address information of the branch instruction executed in the past. In addition, the memory circuit 13 calculates in the address calculator 8 and registers 9
The branch destination address information of the current branch instruction stored in
The branch destination address information of the branch instruction executed in the past is written in the corresponding storage address.

Further, the instruction fetch unit 2 is instructed to fetch the branch destination instruction of the address calculated by the address calculator 8 and held in the register 9 and indicated by the branch destination address information of the current branch instruction. .. As a result, the branch destination instruction of the branch destination address calculated by the address calculator 8 is fetched into the instruction buffer 3 of the instruction fetch unit 2. This fetched branch destination instruction is
The data is input to the branch destination instruction storage device 14 as storage information, and as shown in FIG. 4, stored as the branch destination address information of the previously executed branch instruction. In this case, the branch destination instruction is fetched at the timing shown in FIG. Therefore, the matching condition of the comparator 18 is not satisfied.

However, when the coincidence detection signal is output from the comparator 15 and the new instruction address information this time indicates the instruction address of the branch instruction that has been executed in the past, the control circuit 19 causes the branch destination address. The instruction fetch unit 2 is instructed to fetch the instruction at the address indicated by the predicted branch destination address information read from the storage device 13 and held in the register 16, that is, the branch destination instruction as the prediction. As a result, the branch destination instruction of the branch destination address indicated by the predicted branch destination address information read from the branch destination address storage device 13 is fetched into the instruction buffer 3 of the instruction fetch unit 2. That is, as shown in FIG. 2A, the branch destination instruction is fetched into the branch instruction at the same timing as the address calculation cycle A next to the decoding cycle D. If the fetched branch destination instruction is not canceled by the control circuit 19 based on the outputs of the comparators 10 and 18, the branch destination instruction read from the branch destination instruction storage device 14 is transferred via the register 5 to the instruction decoder. 6, the branch instruction and the branch destination instruction can be decoded in a state equivalent to the case where the branch instruction and the branch destination instruction are read out to the storage device 1 without an overhead, and the processing can be advanced.

However, the predicted branch destination information read from the branch destination address storage device 13 is used as the branch instruction decoding cycle D.
When the effective address calculated by the address calculator 8 and the comparator 10 in the next address calculation cycle A are not matched, the branch destination instruction fetched according to the predicted branch destination address information is canceled. A signal indicating that the comparator 10
Is input to the control circuit 19. Then, a signal for canceling the fetched branch destination instruction is input from the control circuit 19 to the instruction fetch unit 2. As a result,
As shown in (c), the branch destination instruction fetched according to the predicted branch destination address information is canceled. And
The instruction fetch unit 2 is instructed to fetch the instruction at the address indicated by the branch destination address calculated by the address calculator 8 in the address calculation cycle A, and as shown in FIG. The branch destination instruction is fetched with a delay of 3 cycles.

However, although the predicted branch destination address information and the calculated branch destination address information match, the branch destination instruction previously output from the branch destination instruction storage device 14 and the branch fetched according to the predicted branch destination address information. As a result of comparison by the comparator 18 with the preceding instruction, if they do not match, a signal for instructing to cancel (invalidate) the fetched branch destination instruction according to the predicted branch destination address information is sent through the signal line 59. Control circuit 1 from comparator 18
9 is input. Then, a signal for canceling the fetched branch destination instruction is input from the control circuit 19 to the instruction fetch unit 2. As a result, as shown in FIG. 2B, the branch destination instruction fetched according to the predicted branch destination address information is canceled. After that, the instruction fetch unit 2 is instructed to fetch the instruction of the address indicated by the predicted branch destination address information with a delay of 1 cycle, and the instruction is fetched with a delay of 1 cycle from the branch instruction decoding cycle D as shown in FIG. The previous instruction is fetched.

Therefore, a branch instruction in which the branch destination instruction stored in the branch destination storage device 14 in a pair with the predicted branch destination address information matches the branch destination instruction read from the storage device 1 by the predicted branch destination address information. If you run
Since there is no overhead to the storage device 1, the pipeline processing can be further speeded up.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

[0037]

As described above, according to the present invention, the address information of the branch instruction executed in the past and the address information of the branch destination are stored as a pair, and the new instruction address information is stored as the branch instruction. When the address information of the branch destination is matched, the information processing apparatus for reading the instruction of the branch destination using the stored address information of the branch destination is provided with a storage means for storing the instruction of the branch destination paired with the address information of the branch destination. When the new instruction address information coincides with the address information of the stored branch instruction, the instruction of the branch destination stored in the storage means is decoded and the processing is advanced. When performing, it is possible to reduce the overhead to the storage device that stores various instructions,
The pipeline processing can be further speeded up.

[Brief description of drawings]

FIG. 1 is an overall block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment.

FIG. 3 is an explanatory diagram showing a structure of a branch instruction.

FIG. 4 is an explanatory diagram of a storage structure of a storage device that stores information of a branch instruction executed in the past, a branch destination address, and branch destination instruction information.

FIG. 5 is a time chart for explaining the problem of the conventional device.
It is

[Explanation of symbols]

1 ... Memory device, 2 ... Instruction fetch unit, 6 ... Instruction decoder, 7 ... Branch decision circuit, 8 ... Address calculator, 1
0, 15, 18 ... Comparator, 11 ... Instruction address control unit,
12 ... Branch instruction address storage device, 13 ... Branch destination address storage device, 14 ... Branch destination instruction storage device, 19 ... Control circuit.

Claims (2)

[Claims] 1. The address information of a branch instruction executed in the past and the address information of the branch destination are stored as a pair, and when the new instruction address information matches the address information of the stored branch instruction, the memory is stored. In the information processing device that reads out the instruction of the branch destination using the address information of the branch destination,
A storage unit for storing the instruction of the branch destination is provided in pair with the address information of the branch destination, and when the new instruction address information matches the address information of the stored branch instruction, the branch destination stored in the storage unit is stored. An information processing device characterized by decoding instructions and proceeding with processing. 2. A means for invalidating a branch destination instruction stored in the storage means when the instruction of the branch destination read by the address information of the corresponding branch destination does not match is provided. 1. The information processing device according to 1.