JPH0667881A - Branch forecasting address processing system - Google Patents

Abstract

PURPOSE:To quickly detect the execution of incorrect branch by quick address calculation. CONSTITUTION:Simultaneously with the reading of a normal instruction word from an instruction buffer 1 to an instruction register 4, a branch forecasting flag 3 indicating the end of an instruction in an instruction word is checked. When the flag 3 is set up, the flag 3 is read out to a register 5. When the flag 3 corresponding to the instruction is set up, a forecasting branched address is read out from a buffer 2 and set up in a register 6. The contents of a register 8 are read out in accordance with the contents of the register 5 and added to the address field of the register 5 by a branched address adder 10 and the added address is set up in an address register 13. Simultaneously the contents of the register 6 are transferred to a buffer 21. A comparator 16 compares the contents of the register 13 with that of a register buffer 21, and at the time of detecting discrepancy, the error of the precedently forecasted address is judged and the register 13 is selected by a selector 18 and sent to a memory control part 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch prediction address processing method, and more particularly to a method for recalculating an incorrect branch destination address in branch instruction processing.

[0002]

2. Description of the Related Art Conventionally, in this type of branch instruction processing, it has been determined whether or not the predicted branch destination address is correct at the timing of normal instruction processing. In the branch instruction processing, as shown in the time chart of the instruction processing shown in FIG.
The branch destination address is calculated in A cycle. Therefore, the determination as to whether the predicted address is correct is made after the A cycle.

[0003]

The conventional predictive address determination process described above cannot be executed until the calculation of the branch target address is completed in the normal branch instruction process. Therefore, when the predicted address is different, the instruction with the correct branch target address is executed. Has the drawback of slowing down the branch prediction and impairing the effect of branch prediction.

[0004]

According to the branch prediction address processing method of the present invention, an instruction buffer for storing a prefetched instruction word and an instruction word prefetched corresponding to the instruction buffer are branch destinations by a branch prediction buffer. A branch prediction flag indicating a predicted branch instruction, a predicted branch destination address for storing a predicted branch destination address corresponding to the instruction huffer, and an instruction word from the instruction buffer in response to the branch prediction flag. For comparing the output of the address adder with the output of the predicted branch destination address buffer, and an address adder connected to the instruction buffer for calculating a branch destination address according to the read instruction word. And means.

Further, the branch prediction address processing system of the present invention corresponds to the instruction buffer for storing the prefetched instruction word, the first instruction register for holding the instruction word read from the instruction buffer, and the instruction buffer. Branch prediction flag indicating that the prefetched instruction word is a branch instruction whose branch target is predicted by the branch prediction buffer, and a predicted branch target address buffer that stores the predicted branch target address corresponding to the instruction buffer. Means for reading an instruction word from the instruction buffer in response to the branch prediction flag, a second instruction register for holding the read instruction word,
An address adder that calculates an address by selecting the output of either the first instruction register or the second instruction register is compared with the output of the address adder and the output of the predicted branch destination address buffer. And means.

Still further, according to the present invention, an instruction buffer for storing a prefetched instruction word, a first instruction register for holding an instruction word read from the instruction buffer, and a prefetched corresponding to the instruction buffer. A branch prediction flag indicating that the instruction word is a branch instruction whose branch destination is predicted by the branch prediction buffer, a prediction branch destination address buffer that stores a predicted branch destination address corresponding to the instruction buffer, and the branch prediction Means for reading an instruction word from the instruction buffer in response to a flag, an instruction register for holding the read instruction word, and an output of any one of the instruction register and the instruction register is selected to calculate an address. An address adder and means for comparing the output of the instruction address adder with the output of the predicted branch destination address buffer. .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. 1 is an instruction buffer (IB), 2 is a prediction address buffer (PAB), 3 is a branch prediction flag, and 4 is an instruction register (DIR). , 5 is a branch instruction register (TIR), 6 is a prediction address register (PAR), 7 is an instruction counter (IC), 8 is a general register (GR), 9 is an operand address adder (OAA), and 10 is a branch destination address. Adder (TAA) and 11 are instruction address adders (IA)
A) and 12 are operand address registers (OAR),
13 is a branch destination address register (TAR), 14 is an instruction address register (IAR), 15 is a branch prediction buffer (TAB), 16 and 17 are comparators, 18 is a selector, 1
9 is a prediction branch destination address register (PTAR), 20 is a control circuit, and 21 is a prediction address register buffer (PA).
RB) and 30 are memory control units.

Operand address calculation in normal instruction processing will be described. The instruction word read from the instruction buffer 1 is set in the instruction register 4, and instruction processing is started. The general purpose register 8 is accessed for address modification, and the contents of the read general purpose register 8 and the address field of the instruction word are added by the operand address adder 9. The calculated operand address is set in the operand address register 12 and sent to the memory control unit 30 in the next cycle.

Next, the instruction fetch will be described. Instruction fetch is performed according to the contents of the instruction counter 7. The output of the instruction counter 7 is added to a predetermined value (for example, +8 bytes) by the instruction address adder 11. The instruction address calculated by the instruction address adder 11 is set in the instruction address register 14 and the instruction counter 7 is updated. The output of the instruction address register 14 is selected by the selector 18 and sent to the memory controller, and the branch prediction buffer 15 is accessed. The branch prediction buffer 15 is a set associative buffer that holds an instruction address and a branch destination address as a pair, and the comparator 17 indicates that the instruction address of the instruction address register 14 is registered in the branch prediction buffer 15. When detected, the predicted branch destination address is set in the predicted branch destination address register 19. The output of the prediction branch destination address register 19 can be sent to the memory control unit 30 by selecting with the selector 18. On the other hand, the instruction word fetched by the memory control unit 30 using the output of the instruction address register 14 is set in the instruction buffer 1. At this time, if it is an instruction word whose branch target is predicted by the branch prediction buffer 15, the contents of the predicted branch target address register 19 will be the contents of the predicted address buffer 2.
Is set in the entry corresponding to the instruction buffer 1 and the corresponding branch prediction flag is set at the same time.

Next, the check of the predicted address will be described. At the same time as the instruction word is read from the instruction buffer 1 to the instruction register 4 for normal instruction processing, the instruction register 4
The branch prediction flag 3 of the instruction word of one instruction of the instruction word read in is checked. If the branch prediction flag 3 is set, the instruction word is read to the branch instruction register 5. (Here, it is assumed that one instruction is completed, but it may be completed by several instructions.) If the branch prediction flag 3 corresponding to the instruction read to the branch instruction register 5 is set, the predicted branch destination address Is read from the predicted address buffer 2 and set in the predicted address register 6. General-purpose register 8 according to the contents of branch instruction register 5
Is read and added to the address field of the instruction word of the branch instruction register 5 by the branch destination address adder 10.
The calculated branch destination address is set in the branch destination address register 13. At the same time, the contents of the predicted address register 6 are transferred to the predicted address register buffer 21. Branch destination address register 13 by comparator 16
And the predicted address register buffer 21 are compared. If a mismatch is detected here, the previously predicted branch target address is incorrect, and the branch target address register 13 is selected by the selector 18 to fetch the correct branch target and sent to the memory control unit. . FIG. 4 is a diagram for explaining the operation of the predicted address check. The branch destination address register 13 and the predicted address register buffer 21 are shown in FIG.
Will be performed in the D cycle of normal branch instruction processing, which is one cycle earlier than in the conventional case (FIG. 5).

FIG. 2 is a diagram showing a second embodiment of the present invention. The same parts as those in the first embodiment shown in FIG. Reference numeral 22 is a selector.

Operand address calculation in normal instruction processing will be described. The instruction word read from the instruction buffer 1 is set in the instruction register 4, and instruction processing is started. The general-purpose register 8 is accessed for address modification, and the contents of the read general-purpose register 8 and the selector 22 are read.
The address field of the instruction word selected by is added by the operand address adder 9. The calculated operand address is set in the operand address register 12 and sent to the memory control unit 30 in the next cycle.

Next, the instruction fetch will be described. Instruction fetch is performed according to the contents of the instruction counter 7. The output of the instruction counter 7 is added to a predetermined value (for example, +8 bytes) by the instruction address adder 11. The instruction address calculated by the instruction address adder 11 is set in the instruction address register 14 and the instruction counter 7 is updated. The output of the instruction address register 14 is selected by the selector 18 and sent to the memory controller, and the branch prediction buffer 15 is accessed. The branch prediction buffer 15 is a set associative buffer that holds an instruction address and a branch destination address as a pair, and the comparator 17 indicates that the instruction address of the instruction address register 14 is registered in the branch prediction buffer 15. When detected, the predicted branch destination address is set in the predicted branch destination address register 19. The output of the prediction branch destination address register 19 can be sent to the memory control unit 30 by selecting with the selector 18. On the other hand, the instruction word fetched by the memory control unit 30 using the output of the instruction address register 14 is set in the instruction buffer 1. At this time, if it is an instruction word whose branch target is predicted by the branch prediction buffer 15, the contents of the predicted branch target address register 19 will be the contents of the predicted address buffer 2.
Is set in the entry corresponding to the instruction buffer 1 and the corresponding branch prediction flag is set at the same time.

Next, the check of the predicted address will be described. At the same time as the instruction word is read from the instruction buffer 1 to the instruction register 4 for normal instruction processing, the instruction register 4
The branch prediction flag 3 of the instruction word of one instruction of the instruction word read in is checked. If the branch prediction flag 3 is set, the instruction word is read to the branch instruction register 5. (Here, it is assumed that one instruction is completed, but it may be completed by several instructions.) At the same time, the predicted branch destination address is read from the predicted address buffer 2 and set in the predicted address register 6. The general-purpose register 8 is read according to the contents of the branch instruction register 5, and the address field of the branch instruction register 5 is selected by the selector 22 and added by the operand address adder 9. The calculated branch destination address is set in the branch destination address register 13. At the same time, the contents of the predicted address register 6 are transferred to the predicted address register buffer 21. Comparator 1
6, the branch destination address register 13 and the predicted address register buffer 21 are compared. If a mismatch is detected here, it means that the previously predicted branch destination address is incorrect, and the selector 18 is used to fetch the correct branch destination.
The branch destination address register 13 is selected by and is sent to the memory control unit. FIG. 4 is a diagram explaining the operation of the predicted address check.
The comparison between the predicted address register buffer 21 and the predicted address register buffer 21 is performed in the D cycle of normal branch instruction processing, which is one cycle earlier than the conventional case (FIG. 5).

Next, FIG. 3 is a diagram showing a third embodiment of the present invention, in which the reference numeral 23 designates the same reference numerals as those in the first and second embodiments.

Operand address calculation in normal instruction processing will be described. The instruction word read from the instruction buffer 1 is set in the instruction register 4, and instruction processing is started. The general purpose register 8 is accessed for address modification, and the contents of the read general purpose register 8 and the address field of the instruction word are added by the operand address adder 9. The calculated operand address is set in the operand address register 12 and sent to the memory control unit 30 in the next cycle.

Next, the instruction fetch will be described. Instruction fetch is performed according to the contents of the instruction counter 7. The output of the instruction counter 7 is added to a predetermined value (for example, +8 bytes) by the instruction address adder 11. The instruction address calculated by the instruction address adder 11 is set in the instruction address register 14 and the instruction counter 7 is updated. The output of the instruction address register 14 is selected by the selector 18 and sent to the memory controller, and the branch prediction buffer 15 is accessed. The branch prediction buffer 15 is a set associative buffer that holds an instruction address and a branch destination address as a pair, and the comparator 17 indicates that the instruction address of the instruction address register 14 is registered in the branch prediction buffer 15. When detected, the predicted branch destination address is set in the predicted branch destination address register 19. The output of the prediction branch destination address register 19 can be sent to the memory control unit 30 by selecting with the selector 18. On the other hand, the instruction word fetched by the memory control unit 30 using the output of the instruction address register 14 is set in the instruction buffer 1. At this time, if it is an instruction word whose branch target is predicted by the branch prediction buffer 15, the contents of the predicted branch destination address register 19 will be the predicted address buffer 2.
Is set in the entry corresponding to the instruction buffer 1 and the corresponding branch prediction flag is set at the same time.

Next, the check of the predicted address will be described. At the same time as the instruction word is read from the instruction buffer 1 to the instruction register 4 for normal instruction processing, the instruction register 4
The branch prediction flag 3 of the instruction word of one instruction of the instruction word read in is checked. If the branch prediction flag 3 is set, the instruction word is read to the branch instruction register 5. (Here, it is assumed that one instruction is finished, but it may be several instructions.).

At the same time, the predicted branch destination address is read from the predicted address buffer 2 and set in the predicted address register 6. The general-purpose register 8 is read according to the contents of the branch destination instruction register 5, and the address field of the branch instruction register 5 is selected by the selector 22 and added by the instruction address adder 11. The calculated branch destination address is set in the branch destination address register 13. At the same time, the contents of the predicted address register 6 are transferred to the predicted address register buffer 21. The comparator 16 compares the branch destination address register 13 with the predicted address register buffer 21. If a mismatch is detected here, the previously predicted branch target address is incorrect, and the branch target address register 13 is selected by the selector 18 to fetch the correct branch target and sent to the memory control unit. . FIG. 4 is a diagram for explaining the operation of the predicted address check. The branch destination address register 13 and the predicted address register buffer 21 are compared in the D cycle of the normal branch instruction processing, which is different from the conventional case (FIG. 5). 1 cycle earlier.

[0021]

As described above, the present invention has an effect that it is possible to early detect that an erroneous branch prediction is performed by performing address calculation faster than normal instruction processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation in this embodiment.

FIG. 5 is a diagram illustrating an operation according to a conventional technique.

[Explanation of symbols]

 1 instruction buffer (IB) 2 prediction address buffer (PAB) 3 branch prediction flag 4 instruction register (DIR) 5 branch instruction register (TIR) 6 prediction address register (PAR) 7 instruction counter (IC) 8 general purpose register (GR) 9 Operand address adder (OAA) 10 Branch destination address adder (TAA) 11 Instruction address adder (IAA) 12 Operand address register (OAR) 13 Branch destination address register (TAR) 14 Instruction address register (IAR) 15 Branch prediction buffer (TAB) 16, 17 Comparator 18 Selector 19 Prediction branch destination address register (PTAR) 20 Control circuit 21 Prediction address register buffer (PARB) 22, 23 Selector 30 Memory control unit

Claims (3)

[Claims] 1. An instruction buffer for storing a prefetched instruction word in an information processing device for prefetching an instruction, comprising: a branch prediction buffer for holding a post-instruction address and a branch destination address in a pair. A branch prediction flag indicating that the prefetched instruction word is a branch instruction whose branch target is predicted by the branch prediction buffer, and a prediction branch storing a predicted branch target address corresponding to the instruction buffer. A destination address buffer, means for reading an instruction word from the instruction buffer in response to the branch prediction flag, an address adder connected to the instruction buffer for calculating a branch destination address according to the instruction word read out, And comparing the output of the address adder with the output of the predictive branch destination address buffer. A branch prediction address processing method, wherein when a mismatch is detected by the means, the instruction is fetched again by the output of the address adder. 2. An information buffer for prefetching an instruction, comprising: a branch prediction buffer for holding a post-instruction address and a branch destination address in a pair; an instruction buffer for storing a prefetched instruction word; and the instruction buffer. A first instruction register for holding the instruction word read from the branch instruction prediction unit, and a branch prediction indicating that the instruction word prefetched corresponding to the instruction buffer is a branch instruction whose branch target is predicted by the branch prediction buffer. A flag, a predicted branch destination address buffer for storing a predicted branch destination address corresponding to the instruction buffer, a unit for reading an instruction word from the instruction buffer in response to the branch prediction flag, and the read instruction word A second instruction register for holding the address, and an output from any one of the first instruction register and the second name register to calculate an address. Address adder, and means for comparing the output of the address adder with the output of the predicted branch destination address buffer, and when a mismatch is detected by the comparing means, the output of the address adder Branch prediction address processing method characterized by fetching instructions again. 3. An information processing apparatus for prefetching an instruction, comprising: a branch prediction buffer that holds a post-instruction address and a branch destination address as a pair; an independent operand address adder and an instruction address adder; An instruction buffer for storing the prefetched instruction word, a branch prediction flag indicating that the prefetched instruction word corresponding to the instruction buffer is a branch instruction whose branch target is predicted by the branch prediction buffer, and the instruction A prediction branch destination address buffer that stores the prediction branch destination address corresponding to the buffer,
Means for reading an instruction word from the instruction buffer in response to the branch prediction flag; an instruction register for holding the read instruction word; an output from one of the instruction counter and the instruction register; When an address is calculated by the instruction address adder and a means for comparing the output of the instruction address adder and the output of the predicted branch destination address buffer, if a mismatch is detected by the comparing means, A branch prediction address processing method, wherein an instruction is fetched again by the output of the instruction address adder.