JPH04239324A - Branch destination estimating system - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by storing the line address and the compartment number of an instruction cache storing a branch destination instruction into a branch destination estimating memory together with an intra- word address. CONSTITUTION:If the failure of branch is decided for the precedent result by reference to the branch destination estimating memories 1-5 and 1-6, the next instruction is taken out according to the contents of the next index address register 1-7. If the branch succeeds, the contents of the line addresses and the intra-word addresses stored in both memories 1-5 and 1-6 are set to the index address registers 1-7 and 1-8 via a selector 1-17. Then an instruction cache is retrieved and at the same time a compartment number is sent to a compartment selection signal generating circuit 1-11. Thus the next instruction is taken out. In such a constitution, the hardware quantity is decreased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch destination prediction method used for preemption control of instructions in an information processing apparatus.

0002

[Background Art] Conventionally, this type of branch destination prediction method stores only the branch direction when the branch instruction was executed last time, or stores the absolute address of the branch destination instruction when the branch is successful. Therefore, the next time the same branch instruction is prefetched, either the instruction cache is indexed after finding the branch destination address based on the memorized direction, or the next instruction cache is indexed using the absolute address of the memorized branch destination instruction. There is a method to pre-empt orders.

0003

[Problems to be Solved by the Invention] Among the conventional branch destination prediction methods described above, the method that stores only the branch direction is a method that stores only the branch direction after determining the branch destination address if the predicted direction is a successful branch. Because the instruction cache is indexed, even if the prediction is successful, there is a problem in that the processing performance of branch instructions will deteriorate because it takes several cycles after the branch instruction is prefetched until the next instruction is prefetched. .

Furthermore, although the method of storing the absolute address of the branch destination instruction does not cause the performance degradation described above, it has the problem that the amount of information to be stored is large, resulting in a significant increase in the amount of hardware.

[0005]

[Means for Solving the Problems] The method of the present invention predicts whether the next instruction will be a successful branch or an unsuccessful branch based on the previous result of the branch instruction when the prefetched instruction is a branch instruction. In a branch destination prediction method in information processing with a pipeline configuration that prefetches by If the instruction cache is not stored in the instruction cache, the line address and compartment number stored in the instruction cache are stored by block loading. A branch destination prediction memory is provided that stores the line address and compartment number of the instruction cache where the branch instruction was stored, along with the intra-word address, in correspondence with the line address and compartment number of the instruction cache where the branch instruction was stored, so that when the same branch instruction is prefetched next time, The next instruction is retrieved by reading the instruction cache from the line address, compartment, and word address where the next instruction is stored.

[0006]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an instruction fetch control section according to an embodiment of the branch destination prediction method of the present invention, and is a block diagram when the number of compartments of the instruction cache is two.

In the figure, 1-1 and 1-2 are instruction cache address arrays, 1-3 and 1-4 are data arrays, and 1-5 and 1-6 are branch destination prediction memories. -1, data array 1-3 and branch destination prediction memory 1-5 correspond to compartment number 0, and address array 1-2, data array 1-4 and branch destination prediction memory 1-6 correspond to compartment number 1. .

Reference numerals 1-7 and 1-8 are index address registers of the instruction cache, and index address registers 1-7 serve as lower addresses for address array, data array,
It is used as an index address of the branch target prediction memory, that is, a line address and an intra-word address. Further, the index address register 1-8 is used as an upper address for comparison with the contents of the address arrays 1-1, 1-2 read by the index address register 1-7. During normal instruction fetching, the instruction fetching address is signal 1-
17, the index address registers 1-7 and 1-8 are set.

1-9, 1-10 are comparators for comparing the contents of the address arrays 1-1, 1-2 read by the index address register with the contents of the index address register 1-8. The result is sent to the compartment select signal generation circuit 1-11, and data arrays 1-3, 1-4 and branch destination prediction memories 1-5, 1-
Selector 1-12, 1- for selecting the content read out from 6
Thirteen select signals 1-19 are generated.

Compartment select signal generation circuit 1
-11, if either of the comparators 1-9, 1-10 detects a match (that is, the instruction cache is hit), the data arrays 1-3, 1- 4 and branch destination prediction memory 1
A select signal 1-19 is generated to select -5, 1-6.

Furthermore, if neither of the comparators 1-9 and 1-10 detects a match (that is, if the instruction cache misses), the data ( At this time, a select signal 1-19 is generated to indicate the compartment to be registered.

1-15 holds the line address and compartment number indicating the location of the branch destination instruction in the instruction cache after the branch instruction is fetched until it is executed, that is, until the branch decision is made. buffer, 1-16
1-14 is the write data register of the branch destination prediction memory 1-5, 1-6, and 1-14 is the selector selected by the signal 1-17 or the output of the selector 1-13 as the input information of the index address register 1-7. is a branch determination result signal indicating that the branch was successful as a result of the branch determination.

FIG. 2 shows the format within the words stored in the branch target prediction memories 1-5, 1-6.

2-1 is the line address and intra-word address of the instruction cache where the branch destination instruction is stored;
2-2 is also the instruction cache compartment number, and 2-3 is "1" if the instruction stored in either data array 1-3 or 1-4 corresponding to this word was the previous branch instruction. A branch instruction indicator bit indicating that
2-4 is a previous branch direction indicator bit that indicates that the branch instruction was a successful branch last time when it is “1”; 2-5 is “1”
This is a valid display bit that indicates that the instruction is registered in the instruction cache.

FIG. 3 shows the format within the words buffered in buffers 1-15.

3-1 is the line address that indexed the instruction cache when fetching the instruction; 3-3 is the line address and word address similarly to 2-1, the line address that indexed the instruction cache in order to fetch the branch destination instruction. and an intra-word address, and 3-4 is the compartment number of the instruction cache, same as the compartment number 2-2.

Next, the branch destination prediction method of the present invention will be described in detail with reference to FIGS. 1 to 3.

First, consider a case where the instruction cache is hit and the information in the branch destination prediction memories 1-5, 1-6 is invalid, that is, the branch instruction display bits 2-3 are "0".

The instruction cache is indexed by the index address register 1-7, and when there is a hit, the contents of the data array and branch destination prediction memory corresponding to the compartment hit are selected by the selectors 1-12 and 1-13.

At this time, the buffer 1-15 contains the line address that indexed the instruction cache, that is, the contents of the index address register 1-7 and the compartment number 3-1,
3-2.

If the instruction read from the data array is a branch instruction, the contents of the branch destination prediction memory are referred to;
In this case, since the branch instruction display bits 2-3 are "0", fetching of the next instruction is inhibited and the CPU waits until the branch destination address is determined. Here, it is assumed that the branch destination address is determined before the branch instruction is executed in the lower stage of the pipeline.

When the branch destination address is determined, the signal 1-17
is set in the index address register 1-8, and the instruction cache is indexed by the branch destination address. When this hits, the lower address at this time, that is, the contents of the index address register 1-7, is buffered as the line address and word address 3-3, and the compartment number that hit, that is, the select signal 1-19, is buffered as the compartment number 3-4. 1-15, and is held until a branch decision is made.

As a result of the branch judgment, if the branch is successful, the branch judgment result signal 1-18 becomes "1", and the buffer 1-15
The branch instruction display bit 2-3 and previous branch direction display bit 2-4 are set to "1" in the branch destination prediction memory corresponding to the address and compartment stored in the line address 3-1 and compartment number 3-2. ”, the line address, word address, and compartment number of the buffer 1-15 are registered in the line address, word address 2-1, and compartment number 2-2.

As a result of the branch judgment, if the branch is unsuccessful, the branch judgment result signal 1-18 becomes "0", and the position indicated by the line address 3-1 and the compartment number 3-2 is reached as in the case of a successful branch. Branch instruction display bits 2-3
is registered as "1" and the previous branch direction display bits 2-4 are registered as "0". At this time, write data registers 1-16 are used as registers for writing.

Next, consider the case where the instruction cache misses.

If the instruction cache misses when fetching a branch instruction, as is well known, block load processing is performed to register the instruction cache, but the compartment number 3-1 stored in the buffer 1-15 is
2 is the compartment number registered in block load processing, and if the instruction cache misses when fetching a branch destination instruction, it is also registered as compartment number 3-4 in block load processing. It is the same as when the instruction cache is hit, except that the compartment number is taken.

Considering the case where the branch instruction display bits 2-3 are "1" as a result of referring to the contents of the branch destination prediction memory at the end, if the previous branch direction display bits 2-4 are "0", that is, If the previous result was an unsuccessful branch, the next instruction is retrieved as is based on the contents of the next index address register 1-7, and if the previous branch direction display bit is "1", that is, the previous result is a branch. If successful, the contents of the line address and word address 2-1 stored in the branch destination prediction memory are set to the index address register 1-7 via the selector 1-17, and the instruction cache is indexed and The contents of compartment number 2-2 are compartment select signal generation circuit 1-11.
As a result, the next instruction is retrieved by selecting the contents of the data array corresponding to the compartment indicated by compartment number 2-2, regardless of whether there is a hit in the instruction cache.

[0029]

As explained above, the present invention stores only the branch direction by storing the line address and compartment number of the instruction cache in which the branch destination instruction is stored in the branch destination prediction memory together with the in-word address. Compared to the case of prediction, it is possible to obtain higher performance, and the same performance can be obtained with a smaller amount of hardware than the case of storing all branch destination addresses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an instruction fetch control unit using a branch prediction method according to the present invention.

FIG. 2 is a diagram showing an intra-word format of a branch target prediction memory.

FIG. 3 shows the format within a word of a buffer.

[Explanation of symbols]

1-1, 1-2 Address array 1-3, 1-4
Data array 1-5, 1-6 Branch destination prediction memory 1-7, 1-
8 Index address register 1-9, 1-10
Comparator 1-11 Compartment select signal generation circuit 1-12, 1-13, 1-14
Selector 1-15 Buffer 1-16 Write data register 2-1
Line address and word address 2-2 Compartment number 2-3 Branch instruction display bit 2-4 Previous branch direction display bit 2-5
Validity display bit 3-1 Line address

Claims (1)

[Claims] 1. A pipeline configuration that performs prefetching by predicting whether the next instruction will be a successful branch or an unsuccessful branch based on the previous result of the branch instruction when the prefetched instruction is a branch instruction. In a branch destination prediction method in information processing, when a prefetched branch instruction is executed and the branch is successful, if the branch destination instruction is stored in the instruction cache, the line address and compartment of the stored instruction cache are number, and if it is not stored in the instruction cache, the line address and compartment number stored by block load,
In addition, if the branch instruction is not stored in the instruction cache, the branch destination prediction memory stores the line address and compartment number stored by block loading, along with the in-word address, in correspondence with the line address and compartment of the instruction cache where the branch instruction was stored. established,
A branch destination prediction method characterized in that the next time the same branch instruction is prefetched, the next instruction is retrieved by reading the instruction cache from the line address, compartment, and word address where the stored next instruction is stored.