JPH0516547Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) The present invention relates to a correction circuit for an analog clock that corrects the time by rotating a motor in the forward and reverse directions. The present invention relates to a correction circuit that can prevent the occurrence of such occurrence.

(Conventional technology) Traditionally, the time on analog watches has been adjusted by manually turning the pointer shaft, but in recent years it has become possible to adjust the time by fast forwarding the pointer using a switch, just like with digital watches. Something is being devised.

However, since analog clocks have lead and lag errors, it is necessary to rotate the hands forward and backward in order to quickly adjust the time according to these errors.

Therefore, it is necessary to drive the pointer using a polyphase motor capable of forward and reverse rotation, as disclosed in Japanese Utility Model Application Publication No. 56-141596.

(Problem to be solved by the invention) When the pointer is rotated in the forward and reverse directions as described above, when transitioning from reverse correction to the normal display state, the rotation of the motor does not appear as the movement of the pointer due to the backlash of the wheel train. However, there was a problem with delays.

An object of the present invention is to complete the correction by finally rotating the pointer in the forward direction when the pointer is corrected in the reverse direction, so that delays due to backlash of the wheel train do not occur.

(Means for Solving the Problems) The correction circuit for an analog timepiece of the present invention outputs a first detection signal when the operation time of the correction switch is within a set time in an analog timepiece that can be corrected in forward and reverse directions. a determination circuit that outputs a second detection signal when the set time is exceeded; an inversion signal output circuit that outputs an inversion signal that inverts the output generation transition direction of the shift register for a certain period of time in response to the first detection signal; a correction speed switching circuit that outputs a first correction start signal for a certain period of time in response to a second detection signal and then outputs a second correction start signal; and a correction speed switching circuit that outputs a second correction start signal after outputting a first correction start signal in response to a second detection signal; a switching gate circuit that outputs a fast-forward pulse signal for the drive, outputs a correction pulse signal in response to the first correction start signal, and outputs a normal drive pulse signal at times other than correction. There is.

(Function) In the correction circuit of the present invention, when the correction switch is turned on within a set time, the first detection signal is output from the discrimination circuit, and the inversion signal is output for a certain period of time from the inversion signal output circuit.

In response to this inversion signal, a correction fast-forward signal is output from the switching gate circuit, and in response to these signals, the shift register reverses the polyphase motor for a certain period of time and rotates the pointer in the reverse direction at high speed for a predetermined period.

Since the hands are rotated by a predetermined amount during the reverse rotation, the hands will stop after passing the time to be set.

Therefore, after this, it is necessary to rotate the hands in the forward direction to set the time.

To rapidly advance the pointer in the forward direction, turn on the correction switch for more than the set time, and the second
output the detection signal.

The correction speed switching circuit outputs a first correction start signal in response to this second detection signal, and further outputs a second correction start signal if the correction switch is turned on.

The switching gate circuit outputs a correction pulse signal in response to the first correction start signal, and outputs a correction fast-forward pulse signal in response to the second correction start signal.

As a result, the pointer is initially corrected in a fast forward direction, and then subsequently corrected in a fast forward direction at a high speed.

As described above, in the present invention, since the hands are rotated a predetermined amount when correcting the backward rotation, the hands are finally rotated in the forward direction to set the time.

Therefore, even if the pointer is rotated in the normal direction by the normal drive pulse signal after correction, the backlash that occurs when changing from reverse rotation to normal rotation does not occur.

(Example) An example of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the circuit configuration of a correction circuit for an analog timepiece according to an embodiment of the present invention.

2 is a reference signal generator, and 4 is a reference signal from this reference signal generator which is frequency-divided to produce a normal drive pulse signal φ ₀₀ and a correction pulse signal φ ₀₁ having a higher frequency than this signal φ ₀₀ . , and a frequency divider which outputs a correction fast-forward pulse signal φ ₀₂ having a frequency higher than that of the correction pulse signal φ ₀₁ and various clock signals φ ₁ to φ ₃ .

6 is a correction switch, and 8 is a switching circuit which inputs the signal from the correction switch 6 and outputs the operation signal.
It is composed of a chattering prevention circuit 10 that outputs Fs, a discrimination circuit 12, an inverted signal output circuit 14, a correction speed switching circuit 16, and a switching gate circuit 18.

This discrimination circuit 12 is a flip-flop (hereinafter referred to as "FF") which inputs an operation signal Fs to a data input D and inputs a clock signal _φ1 to a clock input C.
) 20, an FF 22 which inputs the operation signal Fs to the clock input C and a signal from the output to the data input D, and an FF 22 which inputs the inverted operation signal Fs and inputs the signal from the output of the FF 22. An AND gate 26 inputs the output Q of the FF 22 and the clock input _φ1 , and the output signal of the AND gate 26 inputs the output signal of the AND gate 24 to the clock input φ, and the output signal of the AND gate 24 is inputted to the reset input R. If it is within a predetermined time, a signal is output from output Qn, and if it is longer than the predetermined time, output Qn +
a shift counter 28 that outputs a signal from 1;
an AND gate 30 which inputs the inverted signal from the FF 20, inputs the signal from the output Qn of the shift counter 28, and outputs a first detection signal;
Output signal of FF20 and output of shift counter 28
It is composed of an AND gate 32 which inputs the signal from Qn+1 and outputs a second detection signal.

The inverted signal output circuit 14 includes an AND gate 34 that inverts a signal from a counter to be described later and inputs a clock signal _φ2 , and an AND gate 34 that inputs the output signal to a clock input φ and resets the first detection signal. A counter 36 that inputs to input R and applies a signal from output Qn to AND gate 34
, an inverter 38 that inverts the signal from the output Qn, an FF 40 that inputs the output signal to the set input S, inputs the signal from the output to the data input D, and outputs the inverted signal FR from the output Q; Q
It is composed of an AND gate 39 which inputs an output signal and an inverted signal of an output signal φc of a switching gate circuit 18, which will be described later, and outputs it to the clock input C of the FF 40.

The corrected speed switching circuit 16 includes an FF 42 which inputs a second detection signal to a set input S and a signal data input D from the output, and an FF 42 which inputs its Q output to an inverting terminal and outputs a switching gate circuit 18 to be described later. Input the inverted signal of signal φc to the other input terminal to turn the FF
AND gate 4 outputs to clock input C of 42
1, an AND gate 44 which inputs an inverted signal from a counter to be described later and further inputs a clock signal _φ3 , and inputs its output signal to a clock input φ and further inputs a signal FF from the output of FF 42 to a reset input R. A counter 46 which applies a signal from the output Qn to the AND gate 44, and its output
It is composed of an AND gate 48 which inverts and inputs the signal from Qn and the signal FF from FF 42, respectively.

The switching gate circuit 18 includes a NOR gate 50 which inputs signals from each output Q of the FFs 40 and 42, an AND gate 52 which inputs the output signal thereof and the normal drive pulse φ ₀₀ , and a first correction start signal from the AND gate 48. AND gate 54 that inputs the signal and the correction pulse signal φ ₀₁ , and the inverted signal FR from FF 40
and an AND gate 58 which inputs the output signal thereof and the correction fast-forward pulse signal φ ₀₂ ,
An OR gate 60 inputs signals from AND gates 52, 54, and 58, and an FF4 inverts its output signal φc and passes it through AND gates 39 and 41, respectively.
and an inverter 62 which applies the voltage to the clock input C of 0 and 42.

64 is a shift register, which includes AND gates 66 to 72 for inverting the inverted signal FR from the FF 40 and inputting the inverted signal to each one input terminal, AND gates 74 to 80 for inputting the inverted signal FR to each one input terminal; Set of AND gates 66 and 74, 68 and 76, 70 and 7
OR gates 82 to 88 input the output signals of 8, 72, and 80, respectively; FFs 90 to 96 each input the output signals to the data input D and the signal φc to the clock input C; and a set of FF96.
OR gates 98 to 1 input the output signals of and 90, 90 and 92, 92 and 94, and 94 and 96, respectively.
04, output signals of FF90-94 and FF92-9
NOR gate 10 which inputs each output signal of 6.
6,108.

110 is the OR gate 9 in the shift register 64
This is a polyphase motor driven by signals from 8 to 104.

Reference numeral 112 denotes a pointer mechanism consisting of a wheel train and a pointer driven by the polyphase motor 110.

Next, the operation of the analog timepiece correction circuit having the above configuration will be explained based on the time chart shown in FIG.

In a normal driving state, that is, when the correction switch 6 is not turned on, the signals FF and FR from the outputs Q of the FFs 40 and 42 are both maintained at L level.

Therefore, the output signal of the NOR gate 50 inputting these signals FF and FR is at H level, the AND gate 52 is in an open state, and the normal drive pulse signal φ ₀₀ is generated at its output. This normal drive pulse signal φ ₀₀ is generated as a signal φc via an OR gate 60.

Normal drive pulse signal φ ₀₀ generated in this signal φc
is applied to clock input C of FF90-96,
FF90 synchronizes with the pulse generated in this signal φc.
.about.96 sequentially set their output signals to H level.

That is, since the inverted signal FR is now at the L level,
AND gates 66-72 which invert this and input it.
is in the open state. At this time, if the output signal of FF90 is at H level, the AND gate 68
An H level signal is applied to the data input D of the FF92 via the OR gate 84, and when a pulse is generated in the signal φc, the FF9
The output signal of No. 2 becomes H level. At this time, since the output signal of the NOR gate 106 is at L level,
The output signal of the FF 90 which inputs this to the data input D via the AND gate 66 and the OR gate 82 becomes L level.

Furthermore, the H level signal from the FF92 is passed through the AND gate 70 and the OR gate 86 to the FF92.
is applied to the data input D of the signal φc, and when the next pulse is generated in the signal φc, the output signal is set to H level in synchronization with this. At this time, since the signal applied to the data input D of the FF 92 is already at the L level, the FF 92 switches its output signal to the L level.

Furthermore, in the same way, the H level signal from the FF94 in the previous stage is applied to the data input D of the FF96 via the AND gate 72 and the OR gate 88 which are open, and this FF96 is also synchronized with the pulse generated in the signal φc. to set the output signal to H level.

In this way, when the normal drive pulse signal φ ₀₀ is generated in the signal φc, pulses synchronized with the normal drive pulse signal φ ₀₀ are sequentially generated in the forward direction at the output of the shift register 64, and this pulse causes multiple The phase motor 110 is driven to rotate the pointer mechanism 112 in the forward direction.

Next, when the correction switch 6 is turned on for a certain period of time or more, the operation causes the chattering prevention circuit 1 to
The operation signal Fs from 0 becomes H level.

When this operation signal Fs becomes H level, the signals from the output Q of the FF 22 are switched to H and L levels, respectively.

Therefore, the AND gate 24 is closed,
AND gate 26 becomes open, and FF2
The output signal of 0 becomes H level.

Therefore, the shift counter 28 is reset and counts the clock signal _φ1 generated at the output of the AND gate 26.

This shift counter 28 advances the count, its output Qn becomes H level, and then the output Qn+1
becomes H level.

When the signal from this output Qn becomes H level,
Since correction switch 6 is still turned on,
The output signal of FF20 is kept at H level,
Therefore, AND gate 30 is in a closed state, and no signal from output Qn is generated at its output. Also, the output
When the signal from Qn+1 becomes H level, FF20
This occurs in the output signal of the AND gate 32, which is in an open state due to the signal from the AND gate 32.

When this second detection signal becomes H level, the FF 42 which inputs it to the set input S is set,
Its output Q, switches to H and L levels, respectively. Therefore, the output of the NOR gate 50 becomes L level, and the AND gate 52 becomes closed.

Further, the counter 46 is reset and counts the clock signal _φ3 from the AND gate 44.

At this time, since the signal from the output Qn of the counter 46 and the signal FF from the FF 42 are both at the L level, the AND gate 48 is in an open state, and the first correction start signal it outputs becomes an H level. Therefore, the AND gate 54 becomes open, and a correction pulse signal φ ₀₁ is generated at its output, and a signal φc output from the OR gate 60 is also generated.

At this time, the inverted signal FR is at L level, so
As described above, the shift register 64 is in a state where it outputs a signal in the direction of driving the multiphase motor 110 in the forward direction. Therefore, when the correction pulse signal φ ₀₁ is generated in the signal φc, the outputs of the FFs 90 to 96 are sequentially switched to the H level at the timing of the pulse generated in the signal φ ₀₁ , and the polyphase motor 110 is driven by the correction pulse signal φ. Fast-forwarded at timing ₀₁ .

Thereafter, when the output Qn of the counter 46 becomes H level, the AND gate 48 is closed, and accordingly, the AND gate 54 is also closed, and the output of the correction pulse signal φ ₀₁ is stopped.

At the same time, the signal from the output Qn of the counter 46 is applied to the AND gate 58 via the OR gate 56, which opens the AND gate 58 and generates the correction fast-forward pulse signal φ ₀₂ at its output. . This signal φ ₀₂ is output from the OR gate 60
The shift register 64 outputs a signal at the timing of the pulse generated in the correction fast-forward pulse signal _φ02 . Therefore, the polyphase motor 110 is fast forwarded in the forward direction at a faster speed.

When the correction switch 6 is turned off here, the operation signal Fs from the chattering prevention circuit 10 becomes L level.

At this time, the output Qn+1 of the shift counter 28
Since FF22 has already been reset by the signal from the output, the signal from the output and the inverted signal
The AND gate 24 that inputs Fs becomes open,
The output signal causes the counter 28 to be reset.

Therefore, the signal from the output Qn+1 of the counter 28 becomes L level, the AND gate 32 inputting this becomes closed, and the second detection signal output from it becomes L level. Therefore, the set holding state of the FF 42 is released, and its output Q is set to L and H, respectively, in synchronization with the pulse generated in the signal φc.
Switch to level.

Therefore, the counter 46 is reset again, and the forward correction is completed.

Here, when the correction switch 6 is turned on for a certain period of time, the shift counter 28 starts counting in the same manner as described above.

When the output Qn reaches the H level, the correction switch 6 is already in the OFF state.
When the operation signal Fs is at the L level, the output signal of the FF 20, which inputs the signal Fs to the data input D, is also at the L level, so that the AND gate 30 is opened. Therefore, the output first detection signal becomes H level, the counter 36 is reset, and when its output Qn becomes L level, it starts counting by the clock signal _φ2 from the AND gate 34 which becomes open.

When the output Qn of this counter 36 becomes L level, it is inverted and inputted to the set input S.
40 is set, and its output Q is switched to H and L levels, respectively. For this reason, FF40
The inverted signal FR from the output Q of is at HL level.

When this inverted signal FR becomes H level, this signal FR passes through the OR gate 56 to the AND gate 5.
8 to open it. For this reason,
A modified fast-forward pulse signal φ ₀₂ is generated at its output,
Furthermore, this signal φ ₀₂ is generated as a signal φc via an OR gate 60.

At this time, since the inverted signal FR is at H level, the AND gates 66 to 72 are closed, and the AND gates 74 to 80 are opened instead. Therefore, if the output signal of the FF96 is now at H level, this signal is passed through the AND gate 78 and the OR gate 86 to the data input D.
The FF94 input to the FF94 sets its output signal to H level in synchronization with the pulse generated in the signal φc, and at this time, the NOR gate 1 is input to the data input D of the FF96.
08, since an L level signal is applied via the AND gate 80 and the OR gate 88, the output signal is set to the L level. Similarly, FF9
The output signal of 4 is further applied to the data input D of FF92 via the AND gate 76 and the OR gate 84, and the FF92 makes the output signal H level in synchronization with the pulse of the signal φc. 82 to the data input D of the FF 90, and the FF 90 sets its output signal to H level in synchronization with the pulse of the signal φc.

Therefore, pulses are sequentially generated in the outputs of the OR gates 98 to 104 in the direction of rotating the multiphase motor 110 in the opposite direction, and the timing of generation of the pulses is synchronized with the correction fast-forward pulse signal φ ₀₂ .

As a result, the pointer is rotated in the opposite direction at high speed.

After that, the counter 36 counts for a certain period of time,
When the output Qn is set to H level, the AND gate 34
becomes a closed state, and the FF 40 is released from the set holding state and makes the inverted signal FR from its output Q go to L level in synchronization with the pulse generated in the signal φc.

When this inverted signal FR becomes L level, the AND gate 58 to which this signal is inputted via the OR gate 56 is closed, and the correction fast-forward pulse signal φ ₀₂ is no longer generated in the signal φc.

As a result, the drive pulse for high-speed reverse rotation that was being output from the shift register 64 is stopped.
Reverse rotation of the pointer will stop.

At this time, the pointer is rotated in the reverse direction at high speed until the counter 36 counts a certain period of time, so that it passes through the time that the user wants to set and makes a predetermined rotation (eg, one rotation). Therefore, it is necessary to further rotate the pointer in the forward direction.

As described above, the pointer is rotated in the forward direction by turning on the correction switch 6 for a certain period of time or more.

When all these correction operations are completed,
By keeping the correction switch 6 in the OFF state, the pulses generated in the signal φc adjust the FFs 40 and 4.
The output state of No. 2 returns to the initial state, and as a result, the AND gate 52 becomes open again, and the normal drive pulse signal φ ₀₀ is applied to the shift register 64.

(Effects of the invention) According to the invention, when the pointer is rotated in the reverse direction, it is always rotated by a predetermined amount, so that it is necessary to further correct it in the forward direction. For this reason, during forward rotation after reverse rotation, where wheel train backlash is a problem, it is always corrected in the forward direction, so that after the final correction in the forward direction, normal drive occurs, and when normal drive starts due to wheel train backlash, This eliminates time delay and eliminates time setting errors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of an analog clock correction circuit according to an embodiment of the present invention, and FIG. 2 is a time chart. 2... Reference signal generator, 4... Frequency divider, 6...
Correction switch, 8...Switching circuit, 12...Discrimination circuit, 14...Inverted signal output circuit, 16...Correction speed switching circuit, 18...Switching gate circuit, 64...
Shift register, 110... Polyphase motor, 112
...Guideline mechanism.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal; a frequency divider that divides the frequency of the reference signal from the reference signal generator and outputs a normal drive pulse signal and a correction pulse signal; a correction switch; a switching circuit that outputs a correction pulse signal in place of the normal drive pulse signal only when the correction switch is operated; an analog clock comprising: a shift register capable of shifting the generation of an output signal in a direction and reversing the direction of the shift; and a polyphase motor rotationally driven by an output signal from the shift register, wherein the frequency divider The switching circuit is configured to output a correction fast-forward pulse signal faster than the correction pulse signal, and further outputs a first detection signal when the operation time of the correction switch is within a preset time. a discriminator circuit that outputs a second detection signal when the predetermined time is exceeded; and an inverter that inverts the transition direction of the output signal of the shift register for a certain period of time in response to the generation of the first detection signal from the discriminator circuit. an inverted signal output circuit that outputs a signal; and a correction speed that outputs a second correction start signal after outputting the first correction start signal for a certain period of time in response to generation of the second detection signal from the discrimination circuit. a switching circuit; when outputting a second correction start signal from the correction speed switching circuit and an inversion signal from the inversion signal output circuit, outputting a correction fast-forward pulse signal from the frequency divider to the shift register; a switching gate circuit that outputs the correction pulse signal to the shift register when the correction start signal No. 1 is output, and further supplies a normal drive pulse signal to the shift register at other times. Analog clock correction circuit.