JPH0441352Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to an analog display timepiece using a polyphase motor, and particularly to a correction circuit that corrects the time by rotating the motor in forward and reverse directions.

(b) Prior art Traditionally, the time of analog display watches has been adjusted by manually rotating the pointer shaft.
In recent years, a system has been devised that allows corrections to be made with a single switch operation, similar to digital watches.

For example, there has been proposed a timepiece such as the one disclosed in Japanese Patent Application Laid-Open No. 56-675, in which a fast-forward pulse is supplied to a motor by a switch operation, and the hands are rapidly forwarded and corrected.

However, although this method is very convenient for correcting delay errors, it has the drawback that it takes a long time to correct lead errors.

Therefore, in order to quickly correct such advance errors, it was proposed to reverse the hands, that is, to correct the time by rotating the motor in the opposite direction. 56−
It was necessary to use a polyphase motor such as that used in the device disclosed in Publication No. 141596.

(c) Problems that the invention aims to solve This polyphase motor generally has larger torque and better damping characteristics than a two-pole step motor for watches, so it is suitable for high-speed rotation. By using , you can perform stable and fast corrections.

However, on the other hand, this polyphase motor has the drawback of large current consumption.

The reason why the current consumption increases is because the two-phase coils are excited at the same time to increase their torque and damping effect in order to obtain more stable rotational operation.

Therefore, current consumption can be reduced by adopting a one-phase excitation method that excites the coils one phase at a time for each drive pulse, instead of two-phase excitation that excites two-phase coils.

However, with this one-phase excitation, the torque is small,
Furthermore, due to the poor damping characteristics, although it could withstand normal step movement, it was not possible to perform high-speed rotation when making corrections.

(d) Means for solving the problem The purpose of the present invention is to reduce the current consumption of a polyphase motor that can rotate at high speed for time adjustment.

In order to solve the above problems and achieve the purpose, the analog clock correction circuit of the present invention drives a polyphase motor with one-phase excitation during normal time display conditions, and uses two-phase excitation during high-speed rotation such as correction. For this purpose, it includes a correction mode circuit that outputs a correction mode signal in the correction mode, and a drive switching circuit that switches the drive pulse from one-phase excitation to two-phase excitation according to the correction mode signal. , and a preset circuit that presets the frequency divider circuit with data that halves the period of the normal drive pulse signal when the correction mode signal disappears, and a A gate control circuit for removing generated extra pulses is provided.

(e) Examples Examples of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing a correction circuit for an analog timepiece according to an embodiment of the present invention.

A reference signal generator 2 includes an oscillator 4 and a frequency divider 6 that divides the high frequency signal output from the oscillator 4 into a reference signal having a predetermined frequency and outputs the same.

8 is a first frequency dividing circuit, and reference signal generator 2
The frequency of the reference signal is divided and a fast-forward pulse signal for correction is output.

The fast forward pulse signal in this example is 256Hz.
is set to .

10 is a second frequency dividing circuit that further divides the frequency of a predetermined signal from the first frequency dividing circuit, and includes a three-stage D type flip-flop (hereinafter abbreviated as FF) 1.
2, 14, 16 and 64Hz from the first frequency divider circuit 8
an AND gate 18 which inputs the signal and an inverted version of a correction mode signal to be described later and applies an output signal to the set input S of the FF 16, and an OR gate 20 which inputs a signal _φ3 from the output of the FF 16 and a correction mode signal. It consists of

Each FF 12, 14, 16 inputs output signals φ ₁ , φ ₂ , φ ₃ from each output to each input D,
Further, the FF12 inputs the clock signal φ ₀ from the first frequency dividing circuit 8 to its clock input C, and the FF14
inputs the signal _φ1 from FF12 to its clock input C, and FF16 inputs the signal φ1 from FF14 to its clock input C.
The signal _φ2 from

The signal φ ₃ outputted from the output of the FF 16 is a normal drive pulse signal for driving the normal motor, and is set to 1/4 Hz in this embodiment.

In addition, the first frequency divider 8 and FF12 input a signal PRESET, which will be described later, which is output at the end of the correction, to each reset input R, and the FF14 inputs a signal PRESET to each reset input R.
PRESET is input to set input S.

22 is a forward correction switch, and 24 is a reverse correction switch.

Reference numeral 26 denotes a pulse signal switching circuit, which switches and outputs an input fast-forward pulse signal and a normal drive pulse signal φ ₃ in response to a correction mode signal.

This pulse signal switching circuit 26 has an AND gate 28 which inputs the normal drive pulse signal φ ₃ to one input terminal and inputs an inverted correction mode signal to the other input terminal.
and an AND gate 3 which inputs a fast forward pulse signal to one input terminal and inputs a correction mode signal to the other input terminal.
0, and an OR gate 32 which inputs the output signals of these AND gates 28 and 30. A correction mode circuit 34 outputs a correction mode signal from when the correction switches 22 and 24 are operated to when the first pulse from the pulse signal switching circuit 26 is generated after the operation is completed.
This modification mode circuit 34 includes modification switches 22,
OR gate 37 that inputs the operation signal from 24
FF39 inputs the output signal to the set input S, inputs the signal from the output to the input D, and outputs the correction mode signal from the output Q, and the correction mode signal and the signal from the pulse signal switching circuit 26. and an AND gate 41 which inputs the signal and applies a signal to the clock input C of the FF 39.

36 is a shift register which sequentially outputs signals in a fixed direction from a plurality of output terminals in synchronization with a signal φ ₄ from a gate control circuit to be described later, and in response to a signal from a transition direction inversion circuit to be described later. This is to reverse the order in which signals are output.

This shift register 36 includes AND gates 38 to 4 which each input a signal from an output Q of an FF 136 in a transition direction inversion circuit 134 to be described later.
4, AND gates 46 to 52 which each input the signal from the output of FF 136 to one input terminal, and the output signals of each set of AND gates 38 and 46, 40 and 48, 42 and 50, 44 and 52, respectively. A gate control circuit 1 which inputs input OR gates 54 to 60 and inputs their output signals to input D, and which will be described later.
FFs 62 to 68 which input the signal φ ₄ from FF 38 to each clock input C, a NOR gate 67 which inputs the output signals Q ₀ to Q ₂ of these FFs 62 to 66, and FF 64
-68 output signals _Q1 to _Q3 are input to the NOR gate 69.

The other input terminals of the AND gates 38 to 44 are connected to the output signal of the NOR gate 67 and the signals Q ₀ to Q ₂ , respectively.
is applied, and AND gates 46 to 52
Signals Q ₁ to _{Q 3} and the output signal of the NOR gate 69 are applied to the other input terminals of the transistors.

Reference numeral 70 denotes a drive circuit that inputs a signal output from the shift register 36 via a drive switching circuit, which will be described later, and amplifies this input signal.

This drive circuit 70 is an AND circuit that inputs the output signals of the OR gates 20 in the second frequency dividing circuit 10 to one input terminal, and inputs signals successively output from a drive switching circuit, which will be described later, to other input terminals. The gates 72 to 78 and their output signals are connected to a resistor 80, respectively.
~86 to the base, each emitter of which is grounded, and the collector of which is connected to the diode 9.
The transistors 88 to 94 are connected to a power supply via transistors 6 to 102.

Motor coils 104 to 110 are connected between the collectors of these transistors 88 to 94 and the power supply, respectively.

112 is a drive switching circuit, and AND gates 114 to 120 each input a correction mode signal to one input terminal and input the output signals Q ₃ , Q ₀ , Q ₁ , and Q ₂ of the shift register 36 to the other input terminals, respectively. and each of its output signals is input to one input terminal, and the signal Q ₀ ~
It is composed of OR gates 122 to 128 which respectively input _Q3 to other input terminals.

The AND gates 114 to 120 are in an open state when the correction mode is entered, and if a pulse is generated in any of the output signals Q ₀ to _{Q 3} of the shift register 36 at this time, this pulse is transmitted to two adjacent predetermined OR gates. occurs at the output of , resulting in a two-phase excitation state.

Note that normally, each pulse from the OR gates 122 to 128 is sent to the AND gate 7 in the drive circuit 70.
2 to 78. (1 phase excitation state).

130 is a preset circuit, which is a D type.
It is composed of FF132.

This FF 132 inputs an inverted correction mode signal to its clock input C, and outputs a signal PRESET from its output.

Further, this FF 132 inputs this signal PRESET to an input D, and further inputs a predetermined frequency signal from the frequency divider 6 in the reference signal generator 2 to a set input S.

The signal output from the output of this FF132
PRESET is a preset signal, which is applied to the first frequency divider circuit 8, FFs 12 and 14, and presets the second frequency divider circuit 10 with frequency division ratio data of 1/2.

Reference numeral 134 denotes a transition direction inversion circuit for inverting the direction in which pulses are sequentially generated in the output of the shift register 36, and is composed of an FF 136.

This FF 136 inputs the operation signal from the reverse correction switch 24 to its reset input R, and also inputs the preset signal PRESET to its set input S.
is being entered.

A signal from the output Q of this FF 136 is applied to one input terminal of AND gates 38 to 44 in the shift register 36, and a signal from the output is applied to one input terminal of AND gates 46 to 52.

Therefore, depending on the state of the output signal of this FF 136, AND gates 38 to 44 or AND gate 4
One of the AND gate groups 6 to 52 is opened.

138 is a gate control circuit, which includes an inverter 140 which inputs and inverts the operation signals of the correction switches 22 and 24 via the OR gate 37 in the correction mode circuit 34, and an AND gate 142 which inputs the output signal and the correction mode signal. FF144 inputs its output signal to the reset input R and inputs the normal drive pulse signal φ ₃ to the set input S, and inputs the signal from its output Q and the signal from the pulse signal switching circuit 26 to generate the signal φ. It consists of an AND gate 146 that outputs ₄ .

Next, the operation of the correction circuit shown in FIG. 1 will be explained based on the time chart shown in FIG.

In normal driving conditions, the correction mode circuit 3
Since the correction mode signal outputted by FF 4 is at L level, the AND gate 18 in the second frequency dividing circuit 10 is in an open state, and therefore the normal drive pulse signal φ ₃ outputted by FF 16 has a 1/ Pulses are generated at a frequency of 4Hz.

The pulse generated in this normal drive pulse signal _φ3 is generated at the output of the OR gate 20, and is generated in the drive circuit 7.
0 to AND gates 72-78.

Also, since the correction mode signal is at L level,
The AND gate 28 in the pulse signal switching circuit 26 is in the open state, and the signal φ ₃ is also generated at its output, and the OR gate in the gate control circuit 138, which is normally in the open state, is further output via the OR gate 32. 146.

As a result, a pulse of signal φ ₃ is generated in output signal φ ₄ of AND gate 146 .

The pulse generated in this signal _φ4 is applied to each clock input C of FF62 to FF68 in the shift register 36.
is applied to FF6 in synchronization with the generation of this pulse.
Output signals Q ₀ to Q ₃ of 2 to 68 sequentially become H level.

That is, when the motor rotates forward, the output Q of the FF 136 in the transition direction inversion circuit 134 is at H level, and the AND gate 3 in the shift register 36
8 to 44 are in the open state.

At this time, if only the output signal Q ₃ of the FF 68 is at H level, the output signal of the NOR gate 67 which inputs the signals Q ₀ to _{Q 2} is at the H level, and the output signal of the FF 68 is passed through the AND gate 38 and the OR gate 54.
An H level signal is applied to input D of No. 2.

Here, when a pulse is generated in the signal φ ₄ , the output signal Q ₀ of the FF62 becomes H level in synchronization with this,
Also, the FF that inputs an L level signal to input D
The output signal _Q3 of 68 becomes L level.

This H level signal Q ₀ is applied to the input D of the FF 64 via the AND gate 40 and the OR gate 56 which are open, and when the next pulse is generated in the signal φ ₄ , the FF 64 is activated in synchronization with this pulse. The output signal _Q1 is set to H level.

At this time, since the signal applied to the input D of FF62 is already at L level, FF62
2 returns the output signal Q ₀ to the L level.

Furthermore, in the same manner, the signals Q ₁ and Q _{2 of the preceding stage FFs 64 and 66, which have reached the H level, are applied to each input D of the FFs 66 and 68 one after another via the AND gates 42 and 44} which are in an open state. This results in a signal Q ₀
~ _Q3 , H level pulses are generated sequentially.

Pulses generated in the signals Q ₀ to _{Q 3} are constantly applied to the drive switching circuit 112 .

Now, since the correction mode signal is at L level, the AND gates 114 to 12 in the drive switching circuit 112
0 is in the closed state, the signals Q ₀ to Q ₃ applied to this drive switching circuit 112 are in the OR gate 1.
It is applied to the drive circuit 70 via 22-128. The AND gates 72 to 78 that input the output signals of the OR gates 122 to 128 are opened at the timing of the signal φ ₃ generated at the output of the OR gate 20 in the second frequency dividing circuit 10. The signal generated at the output of ~128
Pulses are generated in the output signals M0 to _{M3 in the order in which Q0 to Q3 become H} level and at the timing of _the signal _φ3 .

When a pulse is generated in this signal M ₀ , the transistor 88 becomes conductive while the pulse is generated, current flows through the transistor 88 to the coil 104 of the motor, and the coil 104 is energized.

Thereafter, when pulses are sequentially generated in the signals _M1 to _M3 , the transistors 90 to 94 are also sequentially turned on, and the coils 106 to 110 are sequentially excited one phase at a time.

As described above, when the forward direction correction switch 22 is turned on in the normal motor driving state, the operation signal outputted therefrom becomes H level, which is generated at the output of the OR gate 37 in the correction mode circuit 34. When the output signal of this OR gate 37 becomes H level, this signal is input to the set input S.
FF39 is set and the correction mode signal outputted from its output Q is set to H level.

When this correction mode signal becomes H level, the second
The AND gate 18 in the frequency dividing circuit 10 is closed, so that the output signal φ ₃ of the FF 16 is kept at H level, and the correction mode signal and this signal φ ₃ are kept at H level.
The output signal of the OR gate 20 which inputs the signal is also maintained at H level.

Further, when the correction mode signal becomes H level, the AND gate 28 in the pulse signal switching circuit 26 is closed, and the AND gate 30 is opened instead.

Therefore, a fast-forward pulse signal from the first frequency dividing circuit 8 is generated at its output, which is further applied to the AND gate 146 in the gate control circuit 138 via the OR gate 32, and is generated at its output signal φ ₄ . It is applied to the clock input C of FFs 62 to 68 in the shift register 36.

As described above, since the forward direction correction switch 22 is now pressed, the output state of the transition direction reversal circuit 134 is the same as in the normal case described above.

Therefore, the AND gates 38 to 44 in the shift register 36 are in an open state, and when a pulse is generated in the signal _φ4 , the FF6 is activated in the same manner as described above.
Output signals Q ₀ to Q ₃ of 2 to 68 sequentially become H level.

Now, since a fast forward pulse signal (256Hz) is generated in signal φ ₄ , signals Q ₀ to Q ₃ are generated at a faster cycle than when the normal drive pulse signal φ ₃ described above is generated.
Pulses will be generated sequentially.

On the other hand, the AND gate 1 in the drive switching circuit 112
14 to 120 are in the open state because the correction mode signal is at H level.

Therefore, for example, when a pulse occurs in the output signal _Q3 of the shift register 36, this pulse is generated at the output of the OR gate 128, and at the same time, it is also generated at the output of the AND gate 114.
Occurs at the output of 2.

The pulses generated simultaneously at the outputs of the OR gates 122 and 128 are applied to the drive circuit 70, which has already been opened by the signal from the OR gate 20.
Output signals M ₀ , M ₃ of AND gates 72 and 78 in
occurs in When a pulse is generated in the signals M ₀ and M ₃ , transistors 88 and 94 simultaneously become conductive, and coils 104 and 110 are energized.

Following this, the output signal of the shift register 36
When a pulse occurs on Q ₀ , this pulse is generated at the output of OR gate 122 , which is also generated at the output of AND gate 116 , and is generated at the output of OR gate 124 .

Therefore, the next pulse will be applied to the AND gate 72 following the previous pulse, and a new pulse will be applied to the AND gate 74, and the output signals M ₀ and M ₁ will have a pulse. Occur.

Therefore, transistor 88 remains conductive and transistor 90 also becomes conductive.
Coils 104 and 108 will be energized simultaneously.

Similarly, when a pulse occurs on signal Q ₁ ,
Pulses are generated in signals M ₁ and M ₂ at the same time, and coil 1
When the coils 06 and 108 are excited and a pulse is generated in the signal Q ₂ , a pulse is generated in the signals M ₂ and M ₃ at the same time, and the coils 108 and 110 are excited.

When the forward direction correction switch 22 is turned on in this way, the motor is driven in the forward direction in fast forward motion by two-phase excitation.

When the forward correction switch 22 is turned off and turned off, the output signal of the OR gate 37 in the correction mode circuit 34 becomes L level.

Therefore, the output signal of the inverter 140 in the gate control circuit 138 becomes H level, and the AND gate 142 which receives this signal and the correction mode signal from the FF 39 outputs an H level signal.

Therefore, the FF 144 inputting the output signal of the AND gate 142 to the reset input R is reset, the signal from its output Q is set to L level, and the AND gate 146 inputting this signal is closed.

When the AND gate 146 is closed, its output signal φ ₄ becomes L level, and the FFs 62 to 68 in the shift register 36 which input this signal φ ₄ to the clock input C maintain the output state at this time. On the other hand, OR gate 3 in correction mode circuit 34
Immediately after the output signal of the AND gate 146 becomes L level, the pulse generated in the output of the pulse signal switching circuit 26 does not occur in the output signal of the AND gate 146, which is in the closed state, and the pulse is generated in the output signal of the AND gate 146, which is in the open state. The signal is generated at the output of the AND gate 41 in the FF 34, and is applied to the clock input C of the FF 39, which has already been released from the set state.

Therefore, the FF 39 sets its output Q to L level in synchronization with this pulse.

When the correction mode signal goes to L level in this way, the AND gate 114 in the drive switching circuit 112
~120 is in the closed state.

Further, the FF 132 in the preset circuit 130, which inverts and inputs this correction mode signal, sets its output to H level in synchronization with the falling edge of this correction mode signal, and immediately receives the high frequency signal from the frequency divider circuit 6. is set.

Therefore, a trigger pulse is generated in the signal PRESET output from the output of this FF 132, and this pulse is transmitted to the first frequency divider circuit 8 and the second frequency divider circuit 1.
It is applied to the FFs 12 and 14 within 0, and presets the frequency division ratio of the second frequency divider circuit 10 to 1/2 of the normal frequency.

At this time, the AND gate 18 in the second frequency dividing circuit 10 and the AND gate 28 in the pulse signal switching circuit 26 are in an open state, and the FF 144 in the gate control circuit 138 generates a pulse at the output of the FF 16. Then, it is set and the AND gate 146 is opened, so when a pulse is generated in the signal φ ₃ from the output of the FF 16 at 1/2 the normal period after the fast forward correction is completed, this pulse is the same as a normal drive pulse. is generated at the signal φ ₄ and the output of the OR gate 20.

As a result, the motor is driven by one-phase excitation in which current flows through one of the coils of the motor, as in the normal driving state described above.

In this embodiment, since the motor is driven by two-phase excitation during fast-forward correction, when the forward direction switch 22 is turned off, for example, the coil 106,
The rotor will come to a stop during 108.

Therefore, it is 1/2 the position where the rotor normally stops.
Since it stops at a position advanced by a step, instead of generating a pulse on signal _φ3 at the normal frequency (1/4Hz), only the first pulse after correction is generated at 1/2 the normal cycle (1/8Hz). By generating a pulse at , the difference between the position of the hand and the actual time can be further reduced, and this pulse causes the rotor to stop at the positive position.

After that, the normal driving state is resumed.

Now, when the reverse direction correction switch 24 is turned on, the correction mode signal from the correction mode circuit 34 becomes H level in the same way as in the operation described above, and the output signal of the pulse signal switching circuit 26 again has a fast forward pulse. A signal is generated and the drive switching circuit 1
AND gates 114 to 120 within 12 are also opened.

All of these operations are the same as when operating the forward direction correction switch 22, but since the operation signal of the reverse direction correction switch 24 is applied to the reset input R of the FF 136 in the transition direction inversion circuit 134, the operation is performed in the reverse direction. By turning on the direction correction switch 24, the FF 136 is reset, and the signal from its output Q becomes H level.

When the signal from the output of the FF 136 becomes H level, the AND gates 46 to 52 in the shift register 36 open instead of the AND gates 38 to 44.

When the AND gates 46 to 52 are opened, for example, if the output signal Q ₃ of the FF 68 is currently at H level, this signal Q ₃ is output to the AND gate 5.
0 output and passes through the OR gate 58 to FF
66 input D.

Therefore, when a fast forward pulse signal is generated in the signal φ ₄ , the output signal Q ₂ of the FF 66 becomes H level in synchronization with this pulse.

In addition, the H level signal Q ₂ is applied to the AND gate 4
8 output and passes through the OR gate 56 to FF
64 input D.

The FF 64 then sets its output signal Q ₁ to H level in synchronization with the next pulse generated in the signal φ ₄ .

Further, this H level signal Q ₁ is applied to the input D of the FF 62 via the AND gate 46 and the OR gate 54, and this FF 62 outputs its output signal Q ₀ in synchronization with the next pulse generated in the signal φ ₄ .
to H level.

When this signal Q ₀ is at H level, signals Q ₁ to _{Q 3}
Since all are at L level, the output signal of NOR gate 69 is at H level, and FF 68, which inputs this signal to input D via AND gate 52 and OR gate 60, synchronizes with the pulse generated in signal _φ4. Then, the output signal _Q3 is set to H level again.

In this way, when the AND gates 46 to 52 are open, the output signal Q ₀ of the shift register 36
~ _Q3 , pulses are generated in the order of signals _Q3 to _Q0 , respectively.

The drive switching circuit 112 and the drive circuit 70 drive the motor by two-phase excitation, as described above, when the correction mode signal is at H level.

Therefore, when the output signal _Q2 of the shift register 36 becomes H level as described above, the coils 108,
110 is simultaneously excited, and then when the signal _Q1 becomes H level, the coils 106 and 108 are excited.

Therefore, the motor is fast forwarded in the opposite direction, and the time can be adjusted by reversing the hands.

After making the correction in this way, when the reverse direction correction switch 24 is turned off, its operation signal goes to the L level, and as described above, in response, the gate control circuit 138 closes the AND gate 146. state to prevent extra pulses from being generated in the signal _φ4 , and the correction mode circuit 34 uses its FF38
The output state of the correction mode signal is changed to L level.

When this correction mode signal goes to L level, the drive switching circuit 112 returns to the normal state, and a pulse is generated in the output signal PRESET of the preset circuit 130 as described above.

The pulse generated in this signal PRESET presets the second frequency dividing circuit 10 to a frequency division ratio of 1/2 of the normal drive pulse.

At the same time, the FF 136 in the transition direction inversion circuit 134 is set by the pulse generated in the signal PRESET, and its output Q is set to H level.

As a result, the AND gates 38 to 44 in the shift register 36 are opened again, and the pulses generated in the output signal of the shift register 36 shift in the direction of normal rotation of the motor.

After performing the reverse correction as a result, when the reverse direction correction switch 24 is turned off, for example, the coil 10
The rotor stops between 6 and 108, and thereafter the coil 108 is excited by a pulse generated in the signal φ ₃ at half the normal period and rotates in the normal direction.

(f) Effects of the invention According to the invention, the motor is energized in one phase during normal time display, and energized in two phases during forward/reverse fast-forward correction, which enables stable fast-forward correction and at the same time reduces current consumption. can be kept to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a correction circuit for an analog clock according to an embodiment of the present invention, and FIG. 2 is a time chart. 2... Reference signal generator, 8... First frequency dividing circuit, 10... Second frequency dividing circuit, 22... Forward correction switch, 24... Reverse direction correction switch, 26
...Pulse signal switching circuit, 34... Correction mode circuit, 36... Shift register, 70... Drive circuit, 104-110... Coil, 112... Drive switching circuit, 130... Preset circuit, 134...
... Transition direction reversal circuit, 138... Gate control circuit.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal; a first frequency dividing circuit that divides the frequency of the reference signal from the reference signal generator and outputs a correction fast-forward pulse signal; a second frequency divider circuit that further divides the frequency of the signal from the first frequency divider circuit and outputs a normal drive pulse signal; a forward direction correction switch; a reverse direction correction switch; and the first and second frequency divider circuits. a pulse signal switching circuit that inputs a correction fast-forward pulse signal and a normal drive pulse signal from the peripheral circuit and switches and outputs one of the two signals; and one of the forward correction switch and the reverse correction switch. a correction mode circuit that outputs a correction mode signal from the time of operation until the time when the first pulse is generated from the pulse signal switching circuit after the end of the operation; and a plurality of output terminals in response to generation of the pulse signal from the pulse signal switching circuit. a shift register that can shift the generation of an output signal in a more constant direction and reverse the direction of the shift; a drive circuit that amplifies the output signal from the shift register; a polyphase motor connected to the drive circuit; an analog clock circuit comprising: a first gate group that receives signals from each output terminal of the shift register and outputs a signal from the shift register when a correction mode signal is generated from the correction mode circuit; The drive circuit receives signals from the first gate group and receives signals from an output end adjacent to the output end of the shift register to which the first gate group is input. a drive switching circuit comprising a second group of gates that applies a signal to the second frequency dividing circuit; and a drive switching circuit that presets frequency division ratio data of 1/2 in the second frequency dividing circuit in response to the correction mode signal stop of the correction mode circuit. a preset circuit; and a transition for reversing the transition direction of the output of the shift register in response to operation of the reverse direction correction switch and returning the transition direction of the shift register to a normal state in response to a preset signal from the preset circuit. a direction inversion circuit; and a pulse signal from the pulse signal switching circuit is supplied to the shift register only when the forward and reverse correction switches are not operated and when the correction mode signal is generated from the correction mode circuit. A correction circuit for an analog clock, characterized in that it is provided with a gate control circuit that prevents .