JPH05160262A - Method of verifying integrated circuit mask pattern - Google Patents

Abstract

PURPOSE:To provide integrated circuit mask pattern verifying method which reduces the burden of network retrieval and that allows accurate comparison. CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with connecting information S5 extracted from the circuit chart for verification. Based on text information, the identification S6 of the bonding wire parts of S4 and S5 is performed and connecting information comparison S13 is performed permitting the identification S6 as a retrieval starting point. Based on signal path tables S7 and S8, the extraction of S9 and S10 of a floating signal path independent from the bonding wire part is performed and the identification 11 of a corresponding gate is carried out. The identified same gates are used as the additional retrieval starting points.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying an integrated circuit mask pattern, and more particularly to a method for verifying whether a created integrated circuit mask pattern matches the original circuit diagram.

[0002]

2. Description of the Related Art When designing an integrated circuit, first, an integrated circuit mask pattern is designed from a circuit diagram. However, as the degree of integration of integrated circuits improves, the integrated circuit mask pattern becomes very complicated, and it is very difficult to manually verify whether or not the pattern is equivalent to the original circuit diagram. Is. Conventionally, a method using a computer has been used for such verification. In other words, the designed mask pattern is digitized and fetched as mask pattern data (or vector data), and a graphic operation is performed on this to extract connection information between elements. On the other hand, based on the circuit diagram, the connection information between the elements is fetched, the two are compared and collated, and the presence or absence of inconsistency is confirmed.

[0003]

When the first connection information extracted from the circuit diagram and the second connection information extracted from the mask pattern are compared and collated, first, the same location is identified between them. There is a need. That is, on the assumption that the node P1 in the first connection information and the node P1 ′ in the second connection information are the same point, which is the same point as a reference, the comparison and collation work between them is performed. Is done. If it is possible to recognize that the nodes P1 and P1 'are the same location, both of these points are used as search start points to search the circuit network connected to them.

In the conventional method, a node to which a text is added in advance (specifically, the position of the bonding pad) is used as the reference same position.
Text indicating some terminal name as an external connection terminal is attached to each bonding pad. So the first
Between the connection information and the second connection information, the nodes to which the text of the same terminal name is added are identified as the same node.

However, when the comparison and collation is performed using only a portion identified based on such text information as a search starting point, there is a problem that it takes a lot of time to search the circuit network. In addition, if an error occurs in the input of text information, correct identification cannot be performed, and there is a possibility that an unsearchable portion may occur. Furthermore, when the verification is performed by excluding a part of the mask pattern, the circuit network to be verified is divided in the middle, so that a part which is not connected to any bonding pad occurs. Such a part cannot be searched because it is not connected to any search start point.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for verifying an integrated circuit mask pattern which can reduce the burden of circuit network search processing and can perform reliable comparison and verification.

[0007]

(1) A first invention of the present application is an integrated circuit mask pattern for verifying whether an integrated circuit mask pattern designed based on a circuit diagram is equivalent to the original circuit diagram. In the verification method of step 1, extracting connection information of each element from the circuit diagram as first connection information, extracting connection information of each element from the integrated circuit mask pattern as second connection information, and Between the connection information and the second connection information, a step of identifying the same place based on the added text information, and based on the first connection information,
For each signal path, a step of creating a first signal path table showing input / output attributes for gates connected to the signal path, and for each signal path based on the second connection information, Creating a second signal path table showing input / output attributes for gates connected to the signal path;
In the first signal path table, a step of extracting a signal path showing only one of the attributes of input or output as a first floating signal path, and in the second signal path table, either input or output. Extracting a signal path showing only one of the attributes as a second floating signal path, a gate connected to the first floating signal path, and a gate connected to the second floating signal path And a step of identifying the same gate between the first connection information and the second connection information using the identified same location and the same gate as a search start point.
The step of comparing and collating with the connection information of (1) is performed.

(2) The second invention of the present application is the verification method according to the first invention, wherein the remaining gates other than the gates connected to the first floating signal path and the second floating signal path are connected. The step of identifying the same gate between the remaining gates other than the connected gates is further added.

(3) The third aspect of the present invention is the verification method according to the first or second aspect of the invention, in which n gates (n is 2 or more) are identified when the gates cannot be identified on a one-to-one basis. N of groups between groups of
The identification of each group is performed in advance, and the number n of the gates forming the group is sequentially decreased based on the information of the same gate that was newly identified in the comparison and collation stage.

(4) In the fourth aspect of the present invention, in the verification method according to any one of the first to third aspects, the identification of the gates is made by referring to the type of the gate and the connection relation to each signal path. This is done by

[0011]

[Operation] According to the integrated circuit mask pattern verification method of the present invention, the number of search starting points, which are the starting points for searching the network, is increased more than in the conventional method. That is, in the conventional method, only a portion such as a bonding pad to which text information is added is identified, and this is used as a search starting point. In the method according to the present invention, for all gates connected to a signal path, a signal path that shows only one of the attributes of input and output is defined as a floating signal path,
The gates connected to this floating signal path are identified, and the gates recognized as the same are added as a new search start point. In this way, by performing the search using a larger number of search start points, the load of the circuit network search processing is reduced, and reliable comparison and collation can be performed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. First, the procedure of the conventional general verification method is
A description will be given based on the flowchart of FIG. First, in step S1, a circuit is designed and an original circuit diagram is created. A mask pattern is designed in step S2 based on this original circuit diagram. The verification method described here is intended to verify whether or not the circuit diagram created in step S1 and the mask pattern designed in step S2 are equivalent. Therefore, the mask pattern designed in step S2 is digitized in step S3. That is, the designed mask pattern is loaded into a computer as digital data. Then, in step S4, the connection information of the mask pattern is extracted based on this digital data. This is done by performing a graphic operation on the graphic information represented by digital data to recognize each element and the phase relationship of each node. In order to recognize each element, it is necessary to set conditions such as a resistance element in a region consisting of only a certain diffusion layer and a transistor in a region where a polysilicon layer overlaps with a certain diffusion layer. However, since this kind of graphic operation is known, detailed description thereof is omitted here. Similarly, in step S5, based on the circuit diagram created in step S1,
The connection information of the circuit diagram is extracted.

Next, in step S6, the same portion is identified based on the text information. For example, the connection information of the circuit diagram extracted in step S5 is as shown in FIG. 2 (a), and the connection information of the mask pattern extracted in step S4 is as shown in FIG. 2 (b). Suppose The connection information includes signal paths S1, S2, S3 or S1 ', S2', S3 'and gates G1, G2, G.
3 or G1 ', G2', G3 ', but the correspondence between each signal path and each gate cannot be determined from such information. Here, the terminal name "AP" is attached to the bonding pad located at the end point P1 of the signal path S1.
The text information "PLE" is added to the signal path S
It is assumed that the bonding pad located at the end point P1 'of 1'has the text information of the same terminal name "APPLE". In this case, from the added text information, the end point P1 on the connection information of the circuit diagram (FIG. 2 (a)) and the end point P1 'on the connection information of the mask pattern (FIG. 2 (b)) are the same point. I can recognize it. If the same location is identified in this way, the network location can be searched using the identified location as the search start point, and the comparison and collation processing of both connection information can be performed. This is the process shown in the last step S13 in the flowchart of FIG. 1 (step numbers are skipped to match FIG. 4 described later).
Specifically, first, the signal path S connected to the end point P1
It can be recognized that 1 and the signal path S1 ′ connected to the end point P1 ′ are the same signal path. In this way, by searching the network from the search starting points P1 and P1 ′, the signal paths S1 and S1 ′ are identified, the gates G1 and G1 ′ are identified,
The signal paths S2 and S2 'are identified, the gates G2 and G2' are identified, the signal paths S3 and S3 'are identified, and the gates G3 and G3' are identified.

However, as already described as a problem of the prior art, if only the same portion identified based on the text information is used as the search start point, the calculation load of the search processing becomes considerably heavy. In addition, there are cases where unsearchable parts occur. For example, as shown in FIG. 3, consider a case where a RAM is configured in a predetermined area in the circuit and the connection information in this RAM is not verified. In such a case, since the connection information is not extracted for the RAM area hatched in the figure, the circuit network is divided at the boundary line of this area. here,
The node Q1 on the boundary of the RAM area can be searched by the search route R1 from the search start point P1, and the node Q2 can be searched by the search route R2 from the search start point P2. Since Q3 and Q4 are connected only to the route R3 connecting them, it is not possible to search from the search start point P1 or P2. In such a case, even if the circuit diagram and the mask pattern actually match, the result of the comparison and collation does not match.

In FIG. 3, if the nodes Q1 to Q4 in the circuit network can be used as the search start points in addition to the end points P1 and P2 to which the text information is added as the bonding pads, the route R3 can be searched, Moreover, the calculation load of the search can be reduced. The present invention is based on such a basic idea. In the present specification, signal paths reaching nodes that are divided in the middle, like the nodes Q1 to Q4, are referred to as “floating signal paths”. According to the present invention, the gates connected to the floating signal path are identified with each other, and when the gates are recognized as the same gate, the same gate is newly added to the search start point.

The verification method according to the present invention will be described below with reference to the flow chart shown in FIG. Steps S1 to S6 in the flowchart of FIG. 4 are the same as steps S1 to S6 in the flowchart of FIG. That is, in step S1, a circuit is designed and an original circuit diagram is created. Here, for example, the following description will be continued assuming that an original circuit diagram including a circuit shown in FIG. In step S2, a mask pattern is designed based on this original circuit diagram, and this mask pattern is digitized in step S3 and taken in as computer graphic data. Then, step S4
Then, in step S5, the connection information is extracted. When the circuit diagram shown in FIG. 5 is used, step S5
For example, the connection information of the circuit diagram extracted in step S4 is as shown in FIG. 6, and the connection information of the mask pattern extracted in step S4 is as shown in FIG. Each connection information includes signal paths S1 to S
23 or S1 'to S23' and gates G1 to G15
Alternatively, it is composed of G1 'to G15'. Each of the signal paths has information regarding the signal transmission direction, and can recognize whether it is an input signal or an output signal for a specific gate. Also, each gate belongs to one of four gate types in this embodiment. The connection information shown in FIG. 6 and the connection information shown in FIG. 7 are actually equivalent, but it is not known at this point whether or not they are equivalent. For example, it cannot be specified yet which signal path in FIG. 7 the signal path S1 in FIG. 6 is identical to.

Next, in step S6, the same portion is identified based on the text information. As described above, this is a process of recognizing that the connection information of the circuit diagram and the connection information of the mask pattern are the same at a specific node such as a bonding pad. Since the circuit shown in FIG. 5 is an isolated portion that is not connected to any bonding pad, the connection information shown in FIG. 6 and the connection information shown in FIG. It is not.

The procedure following step S7 is a process which is a feature of the present invention. First, in step S7, a first signal path table (FIG. 8) and a first gate table (FIG. 9) are created based on the connection information (FIG. 6) of the circuit diagram. The first signal path table is a table in which the number of connection gates, each connection gate name, gate type, and input / output attribute are summarized for each signal path. For example, for signal path S1, only one gate G1 is connected, this gate G1 is of gate type 1, and signal path S1 has an input / output attribute of input I to this gate G1. Similarly, for signal path S2, two gates G
1, G2 are connected, one gate G1 is of gate type 1, the signal path S2 has an input / output attribute of output O with respect to this gate G1, and the other gate G2 is of gate type 1. The signal path S2 has the input / output attribute of the input I with respect to this gate G2. It will be understood from FIG. 6 and FIG. 8 that the table of FIG. 8 can be easily created based on the connection information of FIG. On the other hand, the first gate table shown in FIG. 9 is a table in which the gate type, the number of connection signal paths, the signal path name, and the input / output attribute are summarized for each gate. For example, for the gate G1, the gate type is 1, the number of connection signal paths is 2, one signal path S2 has an input / output attribute of the output O with respect to this gate G1, and the other signal path S1 has this It has an input / output attribute of input I with respect to the gate G1. It will be understood from reference to FIGS. 6 and 9 that the table of FIG. 9 can be easily created based on the connection information of FIG. In the same manner, in step S8, the second signal path table (FIG. 10) and the second gate table (FIG. 11) are created based on the mask pattern connection information (FIG. 7).

Then, in step S9, the first floating signal path is extracted. As mentioned above, "floating signal path"
Is a signal path leading to a node that is divided on the way. Such a first floating signal path can be extracted from the first signal path table shown in FIG. 8 as follows. That is, if a signal path whose input / output attribute shows only one of the input I and the output O is extracted from among the signal paths shown in this table, it is extracted as the first floating signal path. Is. For example, in the table of FIG. 8, since the input / output attribute of the signal path S1 is only the input I, the signal path S1 is extracted as the floating signal path. However, since the input / output attribute of the signal path S2 has both output O and input I, the signal path S2
2 does not serve as a floating signal path. Further, the signal path S14 is
Despite being connected to the three gates, all three of its input / output attributes are inputs I, so that they are extracted as floating signal paths. Thus, if only the floating signal path is extracted from the first signal path table shown in FIG.
The first floating signal path table shown in can be created. In addition,
The table shown in FIG. 12 is classified according to the number of connection gates for the convenience of identification work described later. In step S10, the second floating signal path is extracted in exactly the same manner. That is, the second signal path table shown in FIG. 13 is extracted by extracting from the second signal path table shown in FIG. 10, the signal path whose input / output attribute shows only one of the input I and output O attributes. The floating signal path table of is obtained.

Next, in step S11, the same gate is identified based on the floating signal path. That is, the gate connected to the first floating signal path (the gate listed in the gate name column of the table of FIG. 12) and the gate connected to the second floating signal path (of the table of FIG. 13). Gates listed in the gate name column) and an identification process for recognizing the same. This identification can be performed by referring to the gate type and input / output attribute of each gate. For example, in FIG. 12, the gate G1 is of gate type 1, and the input / output attribute is I. Therefore, this is abbreviated as “1I”.
The gate that can be abbreviated as “1I” is the gate G
These are 1, G5, G7, and G10. On the other hand, in FIG. 13, the gate which can be abbreviated as “1I” is a gate G1 ′,
They are G5 ', G7', and G10 '. Therefore,
A group of four gates G1, G5, G7 and G10 and gates G1 ', G5', G7 'and G10'.
The group consisting of four gates is a group in which any one of the gates can be associated with each other in a one-to-one relationship, and it means that information indicating identification in group units is obtained. However, with such information, it is not possible to identify which gate corresponds to which gate on a gate-by-gate basis. On the other hand, let's focus on the gate G9 in FIG. This gate G9 is of gate type 2, and the input / output attribute is O. That is, in short, "2
"O". This gate G9 is the only gate that can be abbreviated as "20" in the table of FIG. On the other hand, also in the table of FIG. 13, the gate that can be abbreviated as "2O" is only the gate G9 '. Therefore, the gate G9
It can be recognized that the gate and the gate G9 'are the same gate. Hereinafter, combinations that can be recognized as the same gate will be expressed as G9 = G9 ′ using an equal sign.

Similarly, in the table of FIG.
Only two gates G6 and G11 can be abbreviated as “2I”, and in the table of FIG. 13, only two gates G6 ′ and G11 ′ can be abbreviated as “2I”. Therefore, also for these, information indicating identification in group units can be obtained.

If the table of FIG. 12 and the table of FIG. 13 are compared and the number of connected gates is referred to, the number of identifiable gates increases. For example, in FIG. 12, the signal path S14 has three connection gates, and the gates G10, G11, and G12 are connected.
Therefore, when the data is arranged and abbreviated in the order of the number of connected gates, the gate type, and the input / output attribute, the gate G10 is "31".
I ", the gate G11 is" 32I ", and the gate G12 is" 3 ".
3I ”, respectively. On the other hand, in FIG. 13, the gate G10 'can be abbreviated as "31I", the gate G11' as "32I", and the gate G12 'as "33I". Moreover, no other gate can be abbreviated in the same way. Therefore, these gates are 1: 1
Corresponding to G10 = G10 ′, G11 = G11 ′, G1
2 = G12 'can be identified.

Thus, for the time being, G9 = G9 ', G
10 = G10 ', G11 = G11', G12 = G12
', 4 sets of gates are identified. Where G11 =
Since the identification G11 'is performed, the gate G6
Based on the identification of the group unit obtained between the group consisting of G11 and the group consisting of the gates G6 'and G11', the identification of the gate unit G6 = G6 'becomes possible. Since these gates are recognized as the same gate, they can be used as a search start point in the subsequent comparison and collation processing. After all, by performing step S11, it becomes possible to set five new search start points.

As described above, the gates G1, G5,
The group consisting of four gates G7 and G10 and the group consisting of four gates G1 ′, G5 ′, G7 ′, and G10 ′ have been identified in group units. Although such identification of a group unit does not contribute to setting a new search start point by itself, if a gate unit identification is performed later on a gate that is a member of the group, a new gate unit identification is performed. Can contribute to the identification of For example, as described above, since the identification G10 = G10 ′ has already been performed, the gates G10 and G10 ′ are excluded from the members of the group, and the size of the group is three of the gates G1, G5, and G7. It is reduced to a group of gates and a group of three gates G1 ', G5' and G7 '. Here, if the identification of the gate unit G1 = G1 ′ and G5 = G5 ′ is performed in the future, the identification of the gate unit G7 = G7 ′ can be performed using the identification of the group unit. In this way, the identification information in group units can be used as information indicating candidates for identifying gate units.

The basic principle of the present invention resides in that the same gate is identified based on the floating signal path, as performed in step S11. The process of the subsequent step S12 is
This basic principle is used in reverse to identify gates not related to the floating signal path. This identification method will be described below. In the gate name column of the first floating signal path table shown in FIG. 12, gates connected to the floating signal path are listed. On the other hand, all the gates are listed in the first gate table shown in FIG. So, for the gates listed in the table in Figure 9,
Gates not listed in the table of FIG. 12 are extracted as remaining gates. Specifically, the gates G2, G3, G
Three of 13 are extracted as remaining gates. This is shown in the table of FIG. 14 (a), which is shown separately for each gate type. Similarly, the gates connected to the floating signal path are listed in the gate name column of the second floating signal path table shown in FIG. 13, and all the gates connected to the floating signal path are listed in the second gate table shown in FIG. The gate is posted. Therefore, the gates listed in the table of FIG.
Gates not listed in the table of No. 3 are extracted as remaining gates. Specifically, the gates G2 ', G3', G
Three of 13 'are extracted as remaining gates. This is shown in the table of FIG. 14 (b), which is divided into gate types. The identification in step S12 is a process of recognizing the same gate among these remaining gates. When (a) and (b) of FIG. 14 are compared, among the remaining gates, the gate type 4 has only one set of the gates G13 and G13 '. That is, the identification of G13 = G13 'is possible. The remaining gates G2, G3 and G2
It is possible to identify the groups 'and G3' in units of groups.

In this way, when step S12 is completed, the identification of the gate unit is completed for the six sets of gates shown in FIG. Therefore, each of these 6 sets of gates can be used as a search starting point. In step S13, the connection information is compared and collated based on these search start points. The identification of each group has been completed for the two groups shown in FIG. 16, and this information is used for identification of each gate.

The present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this embodiment and can be implemented in various modes other than this.

[0028]

As described above, in the verification method according to the present invention, since the search starting point identified based on the text information is added to the search starting point identified in the gate unit, more search starting points are used. It is possible to search the existing network, reduce the processing load of the comparison and collation processing of connection information, and shorten the verification time. Further, it becomes possible to verify the circuit portion including the floating signal path, which could not be verified by the conventional method.

[Brief description of drawings]

FIG. 1 is a flowchart showing a procedure of a conventional general mask pattern verification method.

FIG. 2 is a diagram showing an example of connection information extracted from a circuit diagram and a mask pattern.

FIG. 3 is a verification exclusion area (RAM area) in a part of connection information.
It is a figure which shows the example in which was defined.

FIG. 4 is a flowchart showing a procedure of a mask pattern verification method according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a specific circuit diagram to be verified according to the present invention.

6 is a diagram showing connection information extracted from the circuit diagram shown in FIG.

7 is a diagram showing connection information extracted from a mask pattern created based on the circuit diagram shown in FIG.

8 is a diagram showing a signal path table created based on the connection information of the circuit diagram shown in FIG.

9 is a diagram showing a gate table created based on the connection information of the circuit diagram shown in FIG. 6;

10 is a diagram showing a signal path table created based on the connection information of the mask pattern shown in FIG.

11 is a diagram showing a gate table created based on the connection information of the mask pattern shown in FIG.

12 is a diagram showing a floating signal path table created from the signal path table shown in FIG. 8;

13 is a diagram showing a floating signal path table created from the signal path table shown in FIG.

FIG. 14 is a diagram showing remaining gates extracted based on the gate tables shown in FIGS. 9 and 11 and the floating signal path tables shown in FIGS. 12 and 13.

FIG. 15 shows the finally identified gate pairs.

FIG. 16 is a diagram showing finally identified gate group pairs.

[Explanation of symbols]

 G1 to G15 ... Gate of circuit diagram G1 'to G15' ... Gate of mask pattern P1, P1 ', P2 ... End point (bonding pad) Q1 to Q4 ... Nodes R1 to R3 ... Search route S1 to S23 ... Signal path of circuit diagram S1 'to S23' ... Mask pattern signal path

Claims (4)

[Claims] 1. An integrated circuit mask pattern verification method for verifying whether an integrated circuit mask pattern designed on the basis of a circuit diagram is equivalent to the circuit diagram. Between the first connection information and the second connection information; extracting the connection information of each element from the integrated circuit mask pattern as the second connection information; A step of identifying the same location based on the added text information, and showing, for each signal path, an input / output attribute for a gate connected to the signal path, based on the first connection information, And a second signal path table showing, for each signal path, an input / output attribute with respect to a gate connected to the signal path, based on the second connection information. Creating, a step of extracting, in the first signal path table, a signal path showing only one of the attributes of input or output as a first floating signal path, and the second signal path table In the step of extracting, as a second floating signal path, a signal path showing only one of the attributes of input and output, a gate connected to the first floating signal path, and a second floating signal path. Identifying the same gate between the gate connected to the floating signal path and the first connection information and the second connection using the identified same location and the same gate as a search start point. A method for verifying an integrated circuit mask pattern, comprising: comparing and collating connection information. 2. The verification method according to claim 1, wherein a remaining gate other than the gate connected to the first floating signal path and a remaining gate other than the gate connected to the second floating signal path. The method for verifying an integrated circuit mask pattern is characterized in that a step of identifying the same gate is further added between the two. 3. The verification method according to claim 1, wherein if the gate cannot be identified on a one-to-one basis, n
The number of gates that make up the group is based on the information of the same gate that was newly identified at the stage of comparison and verification, by identifying n to n group units between groups (n is a natural number of 2 or more). A method for verifying an integrated circuit mask pattern, wherein n is sequentially decreased. 4. The integrated circuit mask according to claim 1, wherein the gates are identified by referring to the gate type and the connection relationship with each signal path. How to verify the pattern.