JP2776267B2 - Circuit output method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for outputting a circuit diagram, and more particularly to a method for displaying a circuit diagram for creating a mask pattern and a circuit diagram for performing a circuit simulation and extracting respective circuit information.

[0002]

2. Description of the Related Art The main purposes of creating a circuit diagram in a circuit diagram output system are to hold the circuit diagram as a drawing and to output circuit connection information. Of these, circuit connection information is required as input information of a CAD system used in each step of design, and typically, circuit connection information is required in the following three steps.

[0003] 1. Circuit simulation process When performing a circuit simulation to verify that the circuit operates as designed, the circuit simulator assembles a circuit equation from the element names, characteristics, and connection relations of the circuit connection information to obtain a solution. (Step 1).

[0004] 2. Step of Creating Layout with Automatic Layout System When creating a mask pattern with the automatic layout system, the automatic layout determines layout and wiring based on the names and connection relationships of elements or blocks in circuit connection information (step 2).

[0005] 3. Layout verification process After the mask pattern is created, when verifying whether the layout has been created with the circuit configuration according to the circuit design, the circuit connection information of each element or block extracted from the circuit diagram and the connection information extracted from the mask pattern Are compared with each other (Step 3).

In steps 2 and 3, the same circuit information is used, but in step 1, the circuit information is different. That is, in the steps 2 and 3, the elements and wirings constituting the circuit diagram must correspond one-to-one with the elements and wirings on the mask pattern.

However, a circuit simulation is performed by adding a parasitic element which is not intentionally arranged by the designer and which exists parasitically to the circuit. In the wiring part, process 2,
3 is represented as a wiring in a circuit diagram. However, when performing a circuit simulation, a capacitance element is added to the wiring, and a resistance element is added to the wiring because the capacitance and resistance of the wiring that affect the circuit operation must be considered. Is the circuit connection information inserted between.

In other words, circuit connection information for circuit simulation (also referred to as “circuit information”) is obtained by adding circuit information for a parasitic element portion to circuit information for a mask pattern. Therefore, the portion of the circuit connection information excluding the parasitic element portion is exactly the same.

If the parasitic element portion of the circuit information is removed, a circuit diagram for the mask pattern is obtained, and if the parasitic element portion of the circuit information is added, the circuit information for the mask pattern and the parasitic circuit portion become a circuit diagram for circuit simulation. It is necessary to divide the circuit information of the element part.

FIG. 12 is a block diagram showing a functional configuration of a conventional circuit diagram output system (referred to as "conventional example 1").

In FIG. 12, reference numeral 49 denotes an arithmetic processing unit;
Reference numeral denotes an input unit for inputting an instruction for determining the designation, arrangement position, and wiring location of the element. An output unit 51 displays the arrangement of elements and the wiring state. 50 is a storage unit for storing necessary information. The arithmetic processing unit 49 includes a circuit diagram creation process 52 and a circuit connection information extraction process 53.

The storage unit 50 includes element information 54, element arrangement wiring information 55, and circuit connection information 56. The element information 54 registers characteristics such as names, shapes, element values, and the like of elements used in a circuit diagram such as a transistor, a resistor, and a capacitor. The element arrangement wiring information 55 stores a name for specifying an element of the circuit, element position information, and wiring position information.
The circuit connection information 56 stores a name for specifying an element of the circuit and information on the connection relation of the element.

Referring to FIG. 12, an element arrangement and wiring means (not shown) of the arithmetic processing unit specifies an element and determines an arrangement position in accordance with element information 54 and a command input from input unit 48. Further, wiring is performed according to an instruction from the input unit 48. The information on the arrangement and wiring is stored in the element arrangement and wiring information 55.

The circuit connection information extraction processing 53 converts the data into a format determined based on the element arrangement wiring information 55 and stores the converted data in the circuit connection information 56.

FIG. 13 is a diagram showing an example of a display of this conventional circuit diagram output system.
1, an output example of a circuit diagram including a configuration of Q2 and a resistor R0 commonly connected to the emitter of the differential pair transistor.

Another object of the present invention is to provide a method of verifying a mask pattern of an integrated circuit, which can cope with a case where a mismatch has occurred between a mask pattern and a circuit diagram with respect to wiring parasitic resistance or parasitic capacitance. For example, Japanese Unexamined Patent Publication No. 3-67372 discloses a method for verifying whether or not an integrated circuit mask pattern is equivalent to a circuit diagram. Extracting as connection information, extracting connection information of each element from the integrated circuit mask pattern as second connection information, deleting a resistance element and a capacitance element from the first connection information, and disconnecting as a result Correcting the first connection information by reconnecting the connected portions, and deleting a resistance element and a capacitance element from the second connection information Correcting the second connection information by reconnecting the resulting disconnected portion, and comparing the corrected first connection information with the corrected second connection information. A method for verifying an integrated circuit mask pattern has been proposed.

That is, a method of verifying a mask pattern disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-67372 (hereinafter referred to as "conventional example 2").
In order to solve the problem that the connection information of each element extracted from the mask pattern does not match with the connection information of each element extracted from the circuit diagram when performing layout verification, the circuit information is extracted from the circuit diagram and the mask pattern. By extracting the resistive element and the capacitive element at the time of extracting, the coincidence between the circuit diagram and the circuit information of the mask pattern is realized.

Japanese Patent Application Laid-Open No. 4-42374 discloses an example of displaying the value of a parasitic element in the circuit information of a mask pattern in a circuit diagram.
Based on information on elements and wiring extracted from the layout data, a portion where a parasitic element is generated and a wiring portion on a logic / circuit diagram are associated with each other, and the electrical parameters of the parasitic element are displayed on the logic / circuit diagram. A parasitic element display method has been proposed (referred to as “conventional example 3”).

FIG. 14 shows a display example of the third conventional example. When two elements and the symbol 14-1 of the gate are connected to the node 14-2 of the logic / circuit diagram, the logic / circuit diagram is displayed, and at the same time, the electrical parameter of the parasitic resistance is provided near the node 14-2. Parasitic resistance element R
(= 10.0 KΩ) and the parasitic capacitance element C (= 100 p
F) is displayed.

[0020]

In the method of the prior art 1 described above, in order to obtain a circuit for circuit simulation and a circuit for mask pattern, the following three methods have to be performed.

First, a circuit diagram for a mask pattern is created by removing parasitic elements from a circuit diagram input for circuit simulation.

Second, a circuit diagram for circuit simulation is created by adding a parasitic element to the circuit diagram for the mask pattern.

Third, when both are necessary (in most cases, both circuit diagrams are necessary), two circuit diagrams for a mask pattern and a circuit diagram for a circuit simulation are created. It is.

As a design process, circuit simulation and mask pattern design are not completely independent. In other words, it often happens that a mask pattern design is started before all circuit simulations are completed.

In this case, a change in the circuit may occur even during the mask pattern design. In the methods 1 and 2 described above, there is a problem that the circuit diagram must be corrected for the circuit simulation or corrected for the mask pattern each time.

According to the third method, when a circuit diagram is input, a circuit diagram for a mask pattern and a circuit diagram for a circuit simulation are created and registered as separate circuit diagrams. The following problems are mentioned.

When registering a circuit diagram for a mask pattern and a circuit diagram for a circuit simulation as separate circuit diagrams,
For example, a technique is conceivable in which a circuit diagram for a mask pattern is created, and this is duplicated in a circuit diagram for circuit simulation, and a parasitic element is added to the duplicated circuit diagram.

However, circuit design is often forced to change circuits. Each time, the circuit diagram for the mask pattern must be corrected, and the circuit diagram for the circuit simulation must be corrected. In this case, if the circuit diagram for the mask pattern is copied to the circuit diagram for circuit simulation every time the circuit is changed, there is a problem that after the copy, the parasitic element must be input again from scratch.

Alternatively, if the circuit diagram for the circuit simulation is directly changed instead of duplicating the circuit diagram for the mask pattern into the circuit diagram for the circuit simulation, it is said that the circuit configuration for the circuit for the mask pattern matches the circuit configuration. There is a problem that warranty is lost.

Further, the distinction that the created circuit information is a circuit diagram for a mask pattern and a circuit diagram for circuit simulation of the same circuit cannot be managed on a system basis.
Since it depends on the creator, there is a problem that it is not guaranteed that the circuits are the same.

As described above, the circuit for the mask pattern and the circuit for the circuit simulation are not completely different circuits. The circuit diagram for the circuit simulation is obtained by adding information to the circuit diagram for the mask pattern, and the portion of the connection information excluding the parasitic element portion is exactly the same.

Therefore, when a circuit diagram for a mask pattern has two pieces of information of a circuit diagram for a circuit simulation, redundant information must be held, which causes an increase in data amount.

Next, in the method of the second conventional example, in order to match the connection information between the mask pattern and the circuit diagram, all the resistance elements and capacitance elements in the circuit are deleted regardless of the presence or absence of the parasitic element. This method has no effect on the operation of a digital circuit that performs a logical operation.However, in an analog circuit designed using a resistive element and a capacitive element as elements, the resistive element and the capacitive element should be deleted. No circuit operation is performed at all.

That is, in the case of an analog circuit, the verification of the element values of the resistance element and the capacitance element is also an important verification, and cannot be deleted. Therefore, the method of the conventional example 2 is applied to the analog circuit. Can not.

Further, the third conventional example discloses a method of storing circuit information and parasitic element information in separate files, and the parasitic element information is obtained by extracting a parasitic element from a mask pattern. For this reason, in the method of Conventional Example 3, circuit information for circuit simulation cannot be obtained until after the mask pattern is created, and when performing circuit simulation before the mask pattern is created, the method of Conventional Example 3 is used. Not applicable.

However, a circuit designer usually performs a circuit simulation before a mask pattern is created. The influence of parasitic elements such as wiring can be expected to some extent from the experience of designers. The designer performs a simulation based on the prediction in consideration of a parasitic resistance and a parasitic capacitance in a portion that may affect the circuit characteristics. Therefore, the designer needs to specify an arbitrary part of the displayed circuit diagram, add parasitic element information, and obtain circuit connection information including the parasitic element.

In the method of the third conventional example, the information of the parasitic element must be stored in a file in advance. Although the information of the parasitic element stored in the file can be displayed, the designer recognizes the parasitic element information in which an arbitrary element value is added to an arbitrary position as a circuit element as the parasitic element information, and then displays the parasitic element information. Cannot be stored in a file. Therefore, this method cannot be applied to the case where a circuit simulation is performed before the mask pattern is created.

Japanese Unexamined Patent Application Publication No. 63-291169 (hereinafter referred to as "conventional example 4") extracts circuit information and parasitic element information from a mask pattern and adds the element value of the parasitic element to a circuit diagram for display. How to do is shown. However, in this method, since the circuit information and the parasitic element information are stored in the same file, the circuit information including the parasitic element can be output, but the information including only the circuit information cannot be output. Therefore, it is impossible to output two pieces of circuit information, that is, circuit information for circuit simulation and circuit information for verifying a mask pattern, which are the objects of the present invention.

This method can display the circuit information and the parasitic element information stored in the file as in the method of the conventional example 3 (Japanese Patent Application Laid-Open No. 4-42374). Parasitic elements and element values cannot be specified at any position in the displayed circuit diagram. Therefore, circuit information for circuit simulation cannot be output before the mask pattern is created.

Therefore, the present invention solves the above-mentioned problems, and when creating a circuit diagram for mask pattern design and verification and a circuit diagram in which a parasitic element is added for circuit simulation, any one of the circuit diagrams can be used. It is an object of the present invention to provide a circuit diagram output method capable of displaying information and arbitrarily outputting any connection information.

[0041]

According to an aspect of the present invention, there is provided a method for outputting a circuit diagram, comprising: at least a circuit diagram input layer and a parasitic element input layer; A circuit for creating a mask pattern is input to the circuit, a circuit diagram for the mask pattern is output, and a parasitic element portion of the circuit for the mask pattern is input to the parasitic element input layer, and the parasitic element portion is A circuit diagram output method is provided, which is superimposed on the circuit diagram for the mask pattern and displayed and output as a circuit diagram for circuit simulation.

According to the circuit diagram output method of the present invention, circuit information of a circuit diagram for a mask pattern is extracted from the circuit diagram input layer, and the circuit information of the parasitic element input layer is added to the circuit information of the circuit diagram input layer. In addition to the information, circuit information for circuit simulation is extracted from a circuit diagram including the parasitic element portion.

In the circuit diagram output method according to the present invention, in the circuit diagram for the mask pattern, a new wiring line segment name corresponding to a newly provided wiring line segment is provided for the wiring line for introducing the parasitic element. Then, a correspondence table including a connection destination of the end point of the new wiring line segment is created, and the connection information for the circuit simulation is output based on the correspondence table.

Further, in the circuit diagram output method of the present invention, as a preferred mode of the method for outputting circuit information for circuit simulation, (a) circuit information for a mask pattern input to the circuit diagram input layer; A predetermined intermediate file is created from the circuit information input to the parasitic element input layer, and (b) a connection correspondence table representing at least position coordinates of the terminals of the parasitic element and a connection state with reference to the intermediate file is created. (C) Referring to the intermediate file and the connection correspondence table, a new wiring corresponding to a newly provided wiring line segment with respect to the wiring connecting the parasitic element in the circuit diagram for the mask pattern. A wiring correspondence table including a line segment name and a connection destination of an end point of the new wiring line segment is created, and (d) the circuit correspondence information based on the circuit information for the mask pattern in the intermediate file and the information of the wiring correspondence table. Extracting the connection information for the simulation, and wherein the.

[0045]

According to the present invention, a parasitic element for circuit simulation can be displayed by displaying a circuit diagram for a mask pattern and superimposed on the circuit diagram. And connection information for circuit simulation including the parasitic element can be extracted. For this reason, in the conventional method, it was not possible to create a circuit diagram by making a distinction between a parasitic element and a circuit element used as a mask pattern. This makes it possible to create a circuit diagram by distinguishing the elements from the elements. According to the present invention, a normal circuit diagram and a circuit diagram after back annotation can be managed in a unified manner.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing embodiments thereof.

FIG. 4 is a flowchart showing a circuit diagram output system using one embodiment of the present invention and a circuit design process related thereto.

Referring to FIG. 4, a circuit diagram output system (3
In 8), a circuit diagram for a mask pattern is created (39).
This is input to the circuit input layer of the circuit diagram output system.

Next, a parasitic element predicted by the designer is added (40). This is input to the parasitic element input layer of the circuit diagram output system.

From these circuit diagrams, circuit connection information (11) for circuit simulation is output and passed to the circuit simulation (41).

When the normal operation of the circuit is verified by the circuit simulation (41) (42), the circuit connection information (10) for the mask pattern is obtained from the circuit diagram for the mask pattern.
Is extracted and an automatic layout system for mask design (4
Hand over to 3). The automatic layout system (43)
The circuit connection information (44) extracted from the mask pattern is output.

Next, in order to verify the designed mask pattern, the circuit connection information (1) is obtained from the circuit diagram for the mask pattern.
0) is extracted and compared with the circuit connection information (44) extracted from the mask pattern.

When the verification of the mask pattern is completed (4)
7), parasitic element information extracted from the mask pattern (4)
6) is input to the parasitic element input layer of the circuit diagram output system (38) (40).

Back annotation (transistor size obtained by parameter extraction from mask pattern,
In order to perform a procedure for adding a capacitance value, a resistance value, and the like to the original circuit information, circuit connection information (11) for circuit simulation is output again and circuit simulation (41) is performed. If there is no defect in the circuit operation (42), the present design process is completed.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, input section (1) receives an instruction to input a circuit diagram and an output instruction to output circuit connection information.

The arithmetic processing unit (2) comprises a circuit diagram creation process (5) and a circuit connection information extraction process (6).

The circuit diagram creation process (5) is composed of a mask pattern circuit diagram creation process (12) and a circuit simulation circuit diagram creation process (13), and is performed according to the instruction of the instruction input from the input unit (1). , Arrangement and wiring of elements.

The circuit connection information extraction processing (6) comprises a mask pattern circuit connection information extraction processing (14) and a circuit simulation circuit connection information extraction processing (15), and includes a command input from the input unit (1). Follow the instructions in
The connection information for circuit simulation (11) or the connection information for mask pattern (10) is output.

The storage section (3) stores element information (7), circuit information for a circuit diagram input layer (8), circuit information for a parasitic element input layer (9), connection information for a mask pattern (10), The connection information (11) is stored.

The element information (7) registers the names, shapes, characteristics such as element values, etc. of the elements used in the circuit diagram.
In the circuit diagram creation processing (5) of the arithmetic processing unit (2), the element information (7) is referred to and the elements are arranged.

The circuit diagram input layer circuit information (8) is processed by a circuit diagram creation process (5) in accordance with an instruction from the input unit (1).
The circuit diagram information created by the mask pattern circuit diagram creation process (12) is stored.

The circuit information (9) for the parasitic element input layer is supplied to the circuit diagram creating process (1) in the circuit diagram creating process (5) in accordance with an instruction from the input unit (1).
The circuit diagram information created in 3) is stored.

The circuit information (8) for the input layer and the circuit information (9) for the parasitic element input layer preferably correspond to the elements and wirings of the circuits input to the respective layers. 2 is stored. Table 2 below
, The wiring information has each piece of information in line segment units.

[0065]

[Table 1]

[0066]

[Table 2]

The mask pattern connection information (10) is information used for mask pattern design (see 43 in FIG. 4) and mask pattern verification (see layout 45 in FIG. 4). Based on the information (8), information necessary for mask pattern design and verification of the mask pattern is output by the mask pattern circuit connection information extraction processing (14) of the circuit connection information extraction processing (6).

Connection information for circuit simulation (11)
Is information used for circuit simulation,
Based on the circuit information for the circuit input layer (8) and the circuit information for the parasitic element input layer (9), information necessary for circuit simulation is extracted from the circuit connection information extraction processing for circuit simulation (6). 15).

The output section (4) has a function of displaying the created circuit diagram.

Next, the operation of the circuit diagram output system using the circuit diagram output method of this embodiment will be described. FIG.
Circuit diagram creation processing (5) of operation processing unit (2) shown in FIG.
5 is a flowchart showing the operation of FIG.

The processing flow of the mask pattern circuit diagram creation processing will be described with reference to the flowchart of FIG.

The circuit diagram input layer mode flag is turned on (step 16).

The mode flag is a flag indicating whether the circuit input layer is currently being processed or the parasitic element input layer is being processed. Used to identify.

The following processing steps 17 to 19 are repeated until a termination instruction is given.

Processing for displaying the circuit diagram input to the circuit diagram input layer is performed (step 17), and the circuit diagram on the circuit diagram input layer is displayed on the display unit (step 18).

With reference to the elements registered in the element information file (7), the layout wiring is edited (step 1).
9).

Next, if there is an instruction to store the circuit information in a file (step 21), a placement and wiring information storing process is performed (step 22), and the circuit information is stored in the circuit information for circuit diagram input layer (8).

The mode flag is turned off (step 2
3), end.

The processing flow of the circuit diagram creation process for circuit simulation will be described with reference to the flowchart of FIG.

The parasitic element input layer mode flag is turned on (step 24).

A circuit diagram input layer display process is performed (step 1).
7) Display the circuit diagram on the circuit diagram input layer on the output unit (step 18).

The following processing steps 25, 26 and 19 are repeated until a termination instruction is given.

A parasitic element input layer display process is performed (step 25), and a circuit diagram on the parasitic element input layer is displayed on the display section displayed in step 18 (step 2).
6).

A layout and wiring editing process is performed (step 1).
9).

If there is an instruction to store the input parasitic element circuit information in a file (step 21), a placement and wiring information storage process is performed (step 22), and the information is stored in the parasitic element input layer circuit information (9).

The mode flag is turned off (step 2
7), end.

Next, the circuit connection information extracting process (6) of the arithmetic processing unit (2) shown in FIG. 1 will be described. Here, the following items 1 to 3 regarding the circuit input to the parasitic element input layer are assumed.

1. The parasitic element is connected to the wiring of the circuit input layer.

2. Parasitic elements, such as parasitic resistances, placed on the wiring of the circuit diagram input layer are elements only, and have no wiring elements.

3. When the connection information for the circuit simulation is output, if a parasitic element is placed on the wiring of the circuit input layer, the connection information is output with priority given to the state where the parasitic element is placed.

FIG. 3 is a flowchart showing the operation of the circuit connection information extraction processing (6).

A processing flow for extracting circuit connection information for a mask pattern will be described with reference to the flowchart of FIG.

When extracting the circuit connection information for the mask pattern, the format conversion process (28) for the mask pattern shown in the following table is performed from the circuit information file (8) for the circuit diagram input layer and the element information file (7). 3 is output to the mask pattern connection information file (10).

[0094]

[Table 3]

Next, a processing flow for extracting circuit connection information for circuit simulation will be described with reference to the flowchart of FIG.

The circuit connection information for circuit simulation is obtained by adding the circuit information input to the parasitic element input layer to the circuit information input to the circuit input layer.

In order not to change the contents of the circuit information file for circuit diagram input layer (8) and the circuit information file for parasitic element input layer (9), the contents of the circuit information file for circuit diagram input layer (8) and the parasitic element The contents of the input layer circuit information file (9) are stored in the intermediate file (30) (step 29).

The subsequent steps are performed by referring to or modifying the intermediate file (30).

The coordinate position of the unconnected terminal of the element in the parasitic element layer or the coordinate position of the end point of the unconnected wiring (see FIG. 7)
Then, the wiring in the circuit input layer is specified, and a connection correspondence table (see FIG. 9) of the names of the elements, the names of the unconnected terminals, and the names of the wiring line segments to which they are connected is created (step 31).

Next, the elements in the connection correspondence table having the same wiring line segment at the connection destination are extracted (step 32), and steps 33 to 35 are repeated. That is, the processes of steps 32 to 35 are repeated for each wiring segment to which the parasitic element is connected.

When the parasitic element is connected to the wiring line segment, the wiring line segment is divided, and a new line segment is created. A wiring correspondence table (see FIG. 10) having the information of Table 4 below for each wiring line segment is created for each wiring line segment (step 33).

[0102]

[Table 4]

In the elements of the wiring correspondence table in Table 4 above, the connection destination of the end point of the wiring line is further connected to a wiring not in the wiring correspondence table, and the equipotential name of the wiring is If it is the new equipotential name, an equipotential table (see FIG. 11) having the contents of Table 5 below is created (step 34).

[0104]

[Table 5]

A wiring correspondence table, an equipotential table,
The following information corresponding to the intermediate file (30) is added or replaced (step 35).

The names of the unconnected connection elements of the elements of the parasitic element input layer circuit information and the names of the new wiring line segments in the connection correspondence table.

A new wiring line segment name in the wiring correspondence table;
End point name of new wiring line, coordinate value of each end point, new equipotential, connection element name and wiring line segment name of circuit diagram input layer circuit information, equipotential name, end point name, end point position coordinate, connection element name .

The equipotential names of the wiring lines in the equipotential table and the equipotential names of the wiring lines in the circuit diagram input layer circuit information.

A format conversion process for circuit simulation is performed (step 37).

When extracting circuit connection information for circuit simulation, the information shown in Table 6 below is converted from the intermediate file (30) and the element information file (7) by the circuit conversion format conversion process (37). Output to the connection information file for simulation (11).

[0111]

[Table 6]

FIG. 5 is a diagram showing a circuit diagram display example for a mask pattern and a circuit simulation and an output example of connection information according to the present embodiment.

More specifically, FIG. 5A is a diagram showing a display example of a circuit diagram input to the circuit diagram input layer.
5B is a diagram showing an example of mask pattern connection information output from the circuit connection information extraction processing (6) of the circuit of FIG. 5A. In FIG. 5B, the circuit connection information includes an element name, a connection point name (equipotential name), an element model name (modelname), or an element value (value).
e) and the like.

FIG. 5C shows the circuit connection information extraction process for circuit simulation according to this embodiment.
FIG. 10 is a diagram showing a display example of a circuit diagram when a resistor R1 and a capacitor C1 are introduced into a parasitic element input layer on the circuit of FIG. FIG. 5 (D)
FIG. 6 is a diagram illustrating an example of connection information for circuit simulation of the circuit of FIG. Referring to FIG. 5D, by introducing parasitic resistance R1 and parasitic capacitance C1 to the wiring (indicated by equipotential name t1 in FIG. 5A), transistor Q1
Is connected to the new equipotential name t1_2, the parasitic resistance R1 is connected between the new equipotential names t1_1 and t1_2, and the parasitic capacitance C1 is connected between the equipotential name t1_1 and the ground. The circuit simulation performs various characteristic analyzes such as DC analysis, AC analysis, and transient analysis based on the circuit connection information shown in FIG.

FIG. 6 shows an example of the circuit information for the circuit input layer in this embodiment. FIG.
(A) (one end of the wiring w1 is connected to the base terminal of the transistor Q1, and the other end of the wiring w1 is connected to the wirings w2 and w
6 (see also Table 1), the element name (Q1) and the terminal names (collector terminal c, base terminal) as shown in FIG. 6B (see Table 1). b, the emitter terminal e), the position coordinates of the terminal of the element, and the name of the element to which the terminal is connected (the wiring w1 is connected to the base terminal b) are input.

Also, as shown in FIG.
As the wiring information (see Table 2) of the circuit of (A), the name of the line segment unit, the name of the equipotential unit, the name of the end point of the line segment, the position coordinates of the end point of the line segment, the line segment Consists of the names of the elements connected to the endpoints of. Referring to FIG. 6C, for example, the wiring line segment name w1 is t1 as an equipotential name, n1 and n2 as line segment end point names, and position coordinates (x3, y2) and (x2, y2) As the connection destination element name, the end point n1 is connected to the wirings w2 and w3, and the end point n
2 indicates that it is connected to the transistor Q1.

FIG. 7 shows an example of the circuit information for the parasitic element input layer in this embodiment. The circuit information (9) for the parasitic element input layer includes element names, terminal names, position coordinates of element terminals, names of elements to which the terminals are connected, and the like as element information for the circuit input to the layer. Store. The parasitic capacitance C1 and the parasitic resistance R shown in FIG.
7 (B), both ends (p1, p2) of the parasitic resistance R1 are not connected, one end (p1) of the parasitic capacitance C1 is not connected, and the other end (p2). ) Is grounded.

FIG. 8 shows a circuit example for explaining the circuit connection extraction processing in this embodiment. FIG. 8A shows a circuit example (corresponding to FIG. 6A) input to the circuit input layer. FIG. 8B is a diagram showing a circuit when the circuits input to the parasitic element input layers in FIG. 8A and FIG. 8C are overlapped according to the present embodiment.

FIG. 9 shows an example of a connection correspondence table showing the names of the elements, the names of the unconnected terminals, and the names of the wiring segments to which they are connected. The parasitic resistance R1 shown in FIG. The connection terminals p1 and p2 are connected to the wiring line w1 in FIG. 8A, and the unconnected terminal p1 of the parasitic capacitance C1 in FIG. 8C is connected to the wiring line w1 in FIG. 8A. Is shown.

Referring to FIG. 8B, when the parasitic resistance R1 and the parasitic capacitance C1 are connected to the wiring line w1 in FIG. 8A, the wiring line w1 is divided, and a new line segment is formed. w1_
1, w1_2 and w1_3 are created, and as described above,
In step 31 of FIG. 3, a wiring correspondence table of the number of the wiring lines is created.

Referring to FIG. 10, the wiring correspondence table is as follows.
Has a wiring w1 as a connection destination wiring line name of the circuit input layer,
New wiring line names w1_1, w1_2, and w1_3 are provided by adding the parasitic capacitance C1 and the parasitic resistance R1. The equipotential state of the new wiring line segment w1_1 (see FIG. 8B) is changed by the connection of the parasitic element,
The new equipotential name is t1_1, one end point is connected to the wiring w2 and the wiring w3, and the other end point is connected to the new wiring line segment w1_2 and the parasitic capacitance C1.

Similarly, a new wiring line segment w1_2 (FIG. 8B)
), The new equipotential name is t1_1, one end point is connected to the new wiring line segment w1_1 and the parasitic capacitance C1, and the other end point is connected to the parasitic resistance R1. New wiring line segment w1_3
Has a new equipotential name of t1_2, one end point is connected to the parasitic resistance R1, and the other end point is connected to the transistor Q1.

As described above, in the element of the wiring correspondence table, the connection destination element is further connected to a wiring not included in the table, and the equipotential name of the wiring becomes a new equipotential name. If so, an equipotential table is created. 10, the wirings w2 and w3 correspond to this wiring, and referring to FIG. 11, the equipotential table indicates that the equipotential names of the wirings w2 and w3 are equal to the new equipotential name t1_1.

According to the present embodiment, a parasitic element for circuit simulation can be displayed by displaying a circuit diagram for a mask pattern and overlaid on the circuit diagram, and the mask pattern not including the parasitic element can be formed. Connection information for circuit simulation including parasitic elements and parasitic elements can be extracted. For this reason, it is possible to create a circuit diagram with a distinction between a parasitic element and a circuit element used as a mask pattern.
The present invention can also be applied to an analog circuit designed using a resistor and a capacitor as circuit elements.

As described above, the method of the circuit diagram creation processing and the circuit connection information extraction processing according to the present invention has been described with reference to the above-described embodiment. However, the present invention is not limited to the above-described embodiment. Includes various aspects according to the principles of the invention. For example,
The circuit connection extraction method shown in FIG. 3 is shown as an example, and various other methods can be implemented.

[0126]

As described above, according to the present invention, a parasitic element for circuit simulation can be displayed on a circuit diagram for a mask pattern, and can be created over the circuit diagram. It is possible to extract connection information for a mask pattern including no element and connection information for a circuit simulation including a parasitic element.

For this reason, in the conventional method, the parasitic element and
Although it has not been possible to create a circuit diagram with a distinction from a circuit element used as a mask pattern, this is made possible by the present invention. Therefore, the present invention can be applied not only to a digital circuit but also to an analog circuit designed using a resistor and a capacitor as circuit elements.

In a preferred embodiment of the circuit connection information extraction processing for circuit simulation according to the present invention, a file in which the contents of the circuit diagram input layer circuit information and the parasitic element input layer circuit information are added is referred to, and the circuit simulation The circuit diagram is displayed and the connection information is extracted, and the circuit diagram for the mask pattern and the circuit diagram after the back annotation can be centrally managed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a hardware configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of a circuit diagram creation process in one embodiment of the present invention. 9A is a flowchart showing a mask pattern circuit diagram creation processing flow. (B) is a flowchart showing a circuit diagram creation processing flow for circuit simulation.

FIG. 3 is a flowchart showing an operation of a circuit connection information extracting process according to one embodiment of the present invention. (A) is a flowchart showing a mask pattern circuit connection information extraction processing flow.
(B) is a flowchart showing a circuit connection information extraction process for circuit simulation.

FIG. 4 is a flowchart of a circuit design process relating to a circuit diagram output system using the circuit diagram output method according to the present invention.

FIG. 5 is a diagram showing an output example of one embodiment of the present invention.
(A) is a figure which shows the example of a display of the circuit diagram input into the circuit diagram input layer. FIG. 6B is a diagram illustrating an example of mask pattern connection information output from the circuit of FIG. (C) is a diagram showing a display example when a resistance R1 and a capacitance C1 are input to the parasitic element input layer on the circuit of (A). (D) is a diagram showing an example of connection information for circuit simulation of the circuit of (C).

FIG. 6 is a diagram illustrating an example of circuit information for a circuit input layer.
(A) is a figure which shows the example of a circuit input into the circuit input layer.
(B) is a diagram showing element information of the circuit of (A).
(C) is a diagram showing wiring information of the circuit of (A).

FIG. 7A is an explanatory diagram illustrating an example of circuit information for a parasitic element input layer. (B) is a diagram showing element information of the circuit of (A).

FIG. 8 is a diagram illustrating an example of a circuit for explaining circuit connection extraction processing; (A) is a figure which shows the example of a circuit input into the circuit input layer. (B) is a figure which shows the example of a state when (A) and (C) are overlapped. (C) is a diagram showing a circuit example input to the parasitic element input layer.

FIG. 9 is a diagram illustrating an example of a connection correspondence table for a circuit input to a parasitic element input layer.

FIG. 10 is a diagram showing an example of a wiring correspondence table of wiring lines changed by connecting the parasitic elements of FIG. 8B;

FIG. 11 is a diagram illustrating an example of an equipotential table in which the equipotential names changed by connecting the parasitic elements of FIG. 8B are defined.

FIG. 12 is a diagram illustrating a configuration example of a circuit diagram output system according to Conventional Example 1.

FIG. 13 is a diagram showing a display example of Conventional Example 1.

FIG. 14 is a diagram showing a configuration example of a conventional example 3 (Japanese Patent Laid-Open No. 4-42374).

[Explanation of symbols]

 Q1 to Q2 Transistors R0 to R1 Resistance C1 Capacitance t1 to t7 Equipotential names W1 to W6 Wiring line names

Claims (4)

(57) [Claims] 1. A method for outputting a circuit diagram, at least, includes a schematic capture layer, and the parasitic element input layer, a to the circuit diagram input layer, enter the circuit for creating a mask pattern Mask A circuit diagram for a pattern is output. Further, a parasitic element portion of the circuit for the mask pattern is input to the parasitic element input layer, and the parasitic element portion is superimposed on the circuit diagram for the mask pattern. A circuit diagram output method for displaying and outputting a circuit diagram for simulation. 2. Extracting circuit information of a circuit diagram for a mask pattern from the circuit diagram input layer, adding circuit information of the parasitic element input layer to circuit information of the circuit diagram input layer, and including the parasitic element portion. 2. The circuit diagram output method according to claim 1, wherein circuit information for circuit simulation is extracted from the circuit diagram. 3. In the circuit diagram for the mask pattern,
For the wiring for introducing the parasitic element, a correspondence table including a new wiring line segment name corresponding to a newly provided wiring line segment and a connection destination of an end point of the new wiring line segment is created. 3. The circuit diagram output method according to claim 2, wherein the circuit simulation connection information is output based on a table. 4. A predetermined intermediate file is created from circuit information for a mask pattern input to the circuit diagram input layer and circuit information input to the parasitic element input layer, and At least the position coordinates of the terminal of the parasitic element with reference to the file, a connection correspondence table representing a connection state is created, (c) with reference to the intermediate file and the connection correspondence table, in the circuit diagram for the mask pattern, For the wiring connecting the parasitic elements, a new wiring line segment name corresponding to the newly provided wiring line segment and a wiring correspondence table including a connection destination of an end point of the new wiring line segment are created, 3. The circuit diagram output method according to claim 1, wherein d) connection information for the circuit simulation is extracted based on circuit information for a mask pattern in the intermediate file and information in the wiring correspondence table.