JPH0567680A - Parasitic device information extraction device - Google Patents

Abstract

PURPOSE:To enable a parasitic device to be easily retrieved by a method wherein the content of the parasitic device information extracted from layout pattern data is so displayed to be found in circuit chart data at a glance. CONSTITUTION:Parasitic device information 6 such as the parasitic capacitance and the parasitic resistance of a device and wirings extracted through a layout verification module 4 are controlled by a circuit chart feedback process module 8, data displayed and arranged on the circuit chart data 2 are generated using data in which layout pattern data 1 and the circuit chart data 2 are compared with each other and verified and the verification result 5 is coincident, and the content of the parasitic device data 6 is displayed and arranged through a display arrangement module 9 in accordance with the above data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parasitic device information extracting device for extracting parasitic device information (back annotation) such as parasitic capacitance and parasitic resistance of devices and wirings from layout pattern data of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional parasitic device information extraction device. In the figure, 1 is layout pattern data of the integrated circuit, and 2 is circuit diagram data of the integrated circuit. Reference numeral 3 is a comparative verification between the layout pattern data 1 and the circuit diagram data 2 for verification information such as device information of the layout pattern data 1 and the circuit diagram data 2, circuit connection information, and the like; It is a verification rule for extracting parasitic device information such as parasitic capacitance and parasitic resistance of wiring. 4 is layout pattern data 1 and circuit diagram data 2
From the above, according to the verification rule 3, the device information, the circuit connection information, etc. are extracted and the comparison verification is performed, the verification result is generated and stored, and the parasitic pattern information such as the parasitic capacitance and the parasitic resistance of the device and the wiring from the layout pattern data 1. Is a layout verification module for extracting Reference numeral 5 is a verification result generated and stored by the layout verification module 4, 6 is parasitic device information extracted by the layout verification module 4, and 7 is a display module for displaying the parasitic device information 6.

Next, the operation will be described with reference to the flowchart of FIG. The device information and the circuit connection information of the layout pattern data 1 and the circuit diagram data 2 are extracted and compared with each other, that is, the layout pattern data 1 and the circuit diagram data 2 are compared with each other, and the device and the wiring from the layout pattern data 1 are compared. Using the verification rule 3 for extracting the parasitic device information 6 such as the parasitic capacitance and the parasitic resistance of the above, the layout verification module 4 performs the above-mentioned comparative verification (steps 11 to 14), and generates and stores the verification result 5 ( Step 15). Further, the parasitic device information 6 is extracted from the layout pattern data 1 (step 16). When the extracted parasitic device information 6 is searched on the circuit diagram data 2, the display module is created by using the matching information of the layout pattern data 1 of the verification result 5 generated and stored in step 15 and the circuit diagram data 2. In step 7, the corresponding device and wiring on the circuit diagram data 2 are selected and the position is displayed (steps 17 and 18).

FIG. 6 shows an example in which the position (wiring) on the circuit diagram data of the parasitic device information is selectively displayed. In the figure, the bold line indicates the position of the parasitic device.

[0005]

Since the conventional parasitic device information extraction apparatus is configured as described above, the corresponding portion (device, wiring) on the circuit diagram data is selected and displayed by referring to the parasitic device information. Therefore, the position of the parasitic device must be determined, and it is difficult to find the position of the parasitic device at a glance, and there is a problem that it takes time to search.

The present invention has been made to solve the above problems, and the contents of the parasitic device information extracted from the layout pattern data are displayed on the circuit diagram data so that they can be seen at a glance to display the parasitic device information. It is an object of the present invention to provide a parasitic device information extraction device that can easily search for.

[0007]

A parasitic device information extraction apparatus according to the present invention performs a comparative verification of layout pattern data 1 and circuit diagram data 2, and at the same time, based on layout pattern data 1, parasitic capacitances and parasitic resistances of devices and wirings. The extracted parasitic device information 6 on the circuit diagram data 2 by using the layout verification module 4 for extracting the parasitic device information 6 such as The circuit diagram feedback processing module 8 that performs a process for generating data to be displayed and arranged on the circuit diagram, and the output data of the circuit diagram feedback processing module 8 displays and arranges the contents of the parasitic device information 6 on the circuit diagram data 2. And a display arrangement module 9 for

[0008]

The parasitic device information 6 is extracted from the layout pattern data 1, and the data for displaying and arranging the parasitic device information 6 on the circuit diagram data 2 is the result of comparison and verification between the layout pattern data 1 and the circuit diagram data 2. Of the parasitic device information 6 is generated and displayed on the circuit diagram data 2 by the data.

[0009]

1 is a block diagram showing the configuration of a parasitic device information extracting apparatus according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 3 are designated by the same reference numerals, and their description will be omitted. In FIG. 1, reference numeral 8 generates data for displaying and arranging the parasitic device information 6 on the circuit diagram data 2 by using the information in which the layout pattern data 1 and the circuit diagram data 2 in the verification result 5 obtained by the comparison and verification match. It is a circuit diagram feedback processing module for performing the processing. 9 is the circuit diagram data 2 according to the output data of the circuit diagram feedback processing module 8.
A display arrangement module for displaying and arranging the contents of the parasitic device information 6 on the top.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. Comparison of verification information such as device information and circuit connection information between the layout pattern data 1 and the circuit diagram data 2, that is, comparison between the layout pattern data 1 and the circuit diagram data 2, and the parasitics of devices and wirings from the layout pattern data 1. Using the verification rule 3 for extracting the parasitic device information 6 such as capacitance and parasitic resistance, the layout verification module 4 uses the verification information such as device information of the layout pattern data 1 and the circuit diagram data 2 and circuit connection information. Are compared and verified (steps 21 to 24), and the verification result 5 is generated and stored (step 25). Further, the parasitic device information 6 such as the parasitic capacitance and the parasitic resistance of the device and wiring is extracted from the layout pattern data 1 (step 26). When the extracted parasitic device information 6 is searched on the circuit diagram data 2, the parasitic device information 6 is controlled by the circuit diagram feedback processing module 8 and the layout verification of the data to be displayed and arranged on the circuit diagram data 2 is performed. It is generated using the matching information of the layout pattern data 1 of the verification result 5 generated and stored in the module 4 and the circuit diagram data 2. According to the generated data, the display arrangement module 9 displays and arranges the contents of the parasitic device information 6 on the circuit diagram data 2 (steps 27, 28,
29).

FIG. 3 shows an example in which the parasitic device information 6 is displayed on the circuit diagram data 2. In the figure, dotted lines indicate parasitic devices.

[0012]

As described above, according to the present invention, the parasitic device information extracted from the layout pattern data is displayed and arranged on the circuit diagram data. It is possible to make the above judgment at a glance, and it is possible to obtain an effect that the search for the parasitic device becomes easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a parasitic device information extraction device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of this embodiment.

FIG. 3 is a diagram showing a display example of parasitic device information according to this embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional parasitic device information extraction device.

FIG. 5 is a flowchart showing the operation of this conventional example.

FIG. 6 is a diagram showing a display example of parasitic device information according to this conventional example.

[Explanation of symbols]

 1 Layout pattern data 2 Circuit diagram data 4 Layout verification module 6 Parasitic device information 8 Circuit diagram feedback processing module 9 Display arrangement module

Claims (1)

[Claims] 1. A parasitic device information extracting device for extracting parasitic device information such as parasitic capacitances and parasitic resistances of devices and wirings from layout pattern data of an integrated circuit, and comparing and verifying the layout pattern data and the circuit diagram data. The layout verification module that extracts parasitic device information such as parasitic capacitance and parasitic resistance of devices and wirings from the layout pattern data, and the extracted parasitic using the information that the layout pattern data and the circuit diagram data match by the above-mentioned comparison verification. The circuit diagram feedback processing module that performs a process of generating data for displaying and arranging device information on the circuit diagram data, and the contents of the parasitic device information on the circuit diagram data by the output data of this circuit diagram feedback processing module. Display And a display arrangement module for arranging the information, and a parasitic device information extracting apparatus.