JPH06348781A - Layout vertification device - Google Patents

Abstract

PURPOSE:To easily form a layout pattern with high reliability without generating a parasitic element by employing such constitution to verify the potential of the forming layer of a P-diffused resistor which comprises a semiconductor integrated circuit. CONSTITUTION:A net list extraction part 16 generates layout pattern drawing net list data 17 and an island free net information file 18 based on a layout pattern drawing net list inputted from a circuit diagram and layout pattern drawing input/output part 1. A circuit simulator 19 performs circuit simulation based on the data 17, and an island potential verification part 21 verifies the potential of an island based on a circuit simulation result 20, the file 18, and the data 17. In such a manner, the potential at both terminals of the P-diffused resistor are compared with that of the forming layer of the P-diffused resistor, thereby, the potential of the forming layer of the P-diffused resistor can be verified. In this way, it is possible to verify the potential of the forming layer of the P-diffused resistor which comprises the semiconductor integrated circuit with high accuracy by the circuit simulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification device for a semiconductor integrated circuit including a P diffusion resistance formed by P diffusion in an epitaxial layer formed separately on a substrate or an N diffusion layer in a substrate. is there.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional semiconductor integrated circuit layout verification apparatus. In the figure, reference numeral 1 is a circuit diagram for inputting and displaying a semiconductor integrated circuit diagram and its layout pattern diagram, and layout pattern diagram input / output. And 3 are the circuit diagram and the layout pattern diagram. From the circuit diagram data 2 for displaying the circuit diagram input from the input / output unit 1, from the instance number of the element that constitutes the circuit and the net number of the wiring that connects the element. A netlist extraction unit for creating the circuit diagram netlist data 4 and a layout pattern diagram netlist 6 for displaying the layout pattern diagram input from the circuit diagram / layout pattern diagram input / output unit 1 Netlist extraction unit for creating data 7, 8 netlist comparison unit, 9 netlist comparison Over data, 10 is a net list comparison results list.

Next, the operation will be described. Circuit diagram, layout pattern diagram The circuit diagram drawn and displayed by the input / output unit 1 and the circuit diagram data 2 of the layout pattern diagram are input to the netlist extracting unit 3, and in the netlist extracting unit 3, the circuit diagram netlist is displayed. Data 4 is created and input to the netlist comparison unit 8. On the other hand, the layout pattern diagram data 5 of the layout pattern diagram is input to the netlist extraction unit 6, the layout pattern diagram netlist data 7 is created in the netlist extraction unit 6, and is input to the netlist comparison unit 8. Then, the layout pattern diagram netlist data 7 is compared with the circuit diagram netlist data 4 in the netlist comparison unit 8, and the netlist comparison result data 8 is stored in a storage unit (not shown) and printed. The list output 10 is performed and the connection state is verified.

[0004]

Since the conventional layout verifying apparatus is constructed as described above, the connection state of the P diffusion resistance forming the integrated circuit is verified, but the P diffusion resistance 11 is As shown in FIG. 7, since it is formed by P diffusion in the epitaxial layer (hereinafter referred to as an island) 13 that is separated and formed by the separation P diffusion portion 14 on the substrate 12, the potential of the island 13 is not verified, Island 13
If the potential of 2 is lower than the potentials of both ends of the P diffused resistor 11, there is a problem that a parasitic element 15 such as a transistor is generated as shown by a broken line in FIG.

The present invention has been made in order to solve the above problems, and it is possible to verify the connection state of the semiconductor integrated circuit and verify the potential of the P diffusion resistance forming layer constituting the semiconductor integrated circuit. It is an object of the present invention to provide a layout verification device that can also be used.

[0006]

A layout verification device according to the present invention performs circuit simulation based on a layout pattern diagram netlist of a semiconductor integrated circuit, and the potential across the P diffusion resistor and the P diffusion resistor forming the semiconductor integrated circuit. The potential of the diffusion diffusion layer is obtained, the potentials at both ends of the P diffusion resistor are compared with the potential of the diffusion layer formation layer, and the potential of the diffusion layer formation layer is verified. .

[0007]

In the layout verifying device according to the present invention, the potential of the layer in which the P diffusion resistance forming the semiconductor integrated circuit is formed is accurately verified by circuit simulation.

[0008]

【Example】

Example 1. The configuration diagram of the layout verification apparatus according to the embodiment of the present invention shown in FIG. 1 will be described below. In FIG. 1, the same reference numerals as those in FIG. Reference numeral 16 is a circuit diagram and a layout pattern diagram netlist data 17 shown in FIG. 2 and an island fishing net information file 18 shown in FIG. 3 are created based on the layout pattern diagram netlist input from the layout pattern diagram input / output unit 1. Netlist extraction unit, 19
Is a circuit simulator for performing circuit simulation based on the layout pattern diagram netlist data 17, 21
Is the circuit simulation result 20, the island fishing information file 18, and the layout pattern diagram netlist data 1
7 is a resistance island potential verification unit for verifying the potential of the island 13 on the basis of FIG.

Next, the operation will be described. Circuit diagram, layout pattern diagram The circuit diagram drawn and displayed by the input / output unit 1 and the circuit diagram data 2 of the layout pattern diagram are input to the netlist extracting unit 3, and in the netlist extracting unit 3, the circuit diagram netlist is displayed. 4 is created. On the other hand, the layout pattern diagram data 5 of the layout pattern diagram is input to the netlist extraction unit 6. Based on the layout pattern diagram data 15 input in the netlist extraction unit 16, the instance number of the P diffusion resistance formed by the P diffusion in the island 13 shown in FIG. 7 and the wiring connected to both ends of the P diffusion resistance. Net number and net number of wiring connected to the terminal 13a of the island 13 (hereinafter referred to as island fishing net number)
2 including the layout pattern diagram netlist data 17 shown in FIG. 2 and the island fishing net shown in FIG. 3 which is composed of the instance number of the P diffusion resistor 11 formed by P diffusion on the island 13 and the island fishing net number. The information file 18 is created. Then, as in the conventional case, the circuit list netlist data 4 and the layout pattern diagram netlist data 17 are used in the netlist comparison unit 8.
And are compared to verify the wiring state. On the other hand, the circuit simulator 19 executes circuit simulation based on the input layout pattern diagram netlist data 17. The circuit simulation result 20 is input to the resistance island potential verification unit 21, and the resistance island potential verification unit 21 calculates the island net potential (based on the simulation result file 20, the island fishing net information file 18 and the layout pattern diagram netlist data 17). Island potential)
The island potential is verified by determining whether it is the same potential as the net potential at both ends of the P diffusion resistance formed by diffusion or a high potential.

The judgment operation of the resistance island potential verification unit 21 is shown in FIG.
As shown in the flowchart of FIG. 5, the instance number of the P diffusion resistance and the island fishing net number of the P diffusion resistance formed on the island are read from the island fishing net information file 18, and the net number and the voltage value are read from the circuit simulation result file 20. (Step A), the net number n of the simulation result file 20 corresponding to the net number N of the island fishing net information file 18 is searched (N = n). Therefore, it is found that the island fishing net potential (island potential) of the P diffusion resistance is Vn (N = Vn) (step B). Next, the instance number RN of the P diffusion resistance corresponding to the island fishing net number N in the island fishing net information file 18 is read, and the net numbers 20 and 25 at both ends of the instance number RN are read from the layout pattern diagram net list 17. From the net numbers 20 and 25 of the circuit simulation result file 20, the voltage values V ₂₀ and V ₂₅ across the P diffusion resistance RN are obtained (step C). Next, the island potential Vn is compared with the voltage values V ₂₀ and V ₂₅ across the P diffusion resistance RN. If Vn is larger than V ₂₀ and V ₂₅ , or the same, the island net number is normal. If Vn is smaller than V ₂₀ and V ₂₅ , the islanding net number is judged to be erroneous, and only if it is judged to be erroneous, the verification result data 22 is added to the layout pattern diagram data 15. Are returned (step D).

Embodiment 2. Although the P-diffusion resistor forming the semiconductor integrated circuit is formed by P-diffusion in the epitaxial layer formed separately on the substrate in the first embodiment, the present invention is not limited to this, and as shown in FIG. The P diffused resistor may be formed in the N diffused layer in the substrate 12 by P diffusion, and can be verified in the same manner by the layout verifying device according to the first embodiment, and the same effect can be obtained.

[0012]

As described above, according to the present invention, since the potential of the formation layer of the P diffusion resistance forming the semiconductor integrated circuit is verified, a highly reliable layout pattern in which parasitic elements are not generated can be obtained. Easy to form.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a layout verification apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout pattern diagram net list.

FIG. 3 is a diagram showing an example of an island fishing net information file.

FIG. 4 is a flowchart showing an example of the operation of the resistance island potential verification unit 21 shown in FIG.

FIG. 5 is a cross-sectional view showing P diffusion resistance.

FIG. 6 is a configuration diagram showing a conventional layout verification device.

FIG. 7 is a cross-sectional view showing P diffusion resistance.

FIG. 8 is a diagram showing an example of generation of parasitic elements.

[Explanation of symbols]

 1 circuit diagram, layout pattern input / output device 2 circuit diagram data 3 netlist extraction unit 4 circuit diagram netlist 8 netlist comparison unit 9 netlist comparison result data 15 layout pattern diagram data 16 netlist extraction unit 17 layout pattern diagram Netlist 18 Island fishing net information file 19 Circuit simulator 20 Circuit simulation result 21 Resistor island potential verification unit

Claims (1)

[Claims] 1. A circuit diagram of a semiconductor integrated circuit including a P diffusion resistor formed by P diffusion in an epitaxial layer formed separately on a substrate, an N diffusion layer in a substrate, and the like, and its layout pattern diagram from an input / output section. A circuit diagram netlist is extracted based on the circuit diagram data, and a layout pattern diagram netlist is extracted based on the circuit diagram and the layout pattern diagram data from the layout pattern diagram input / output unit.
A circuit simulator for comparing the two netlists and performing a layout verification, in which a circuit simulation is performed based on the layout pattern diagram netlist to obtain the potentials at both ends of the P diffusion resistance and the potential of the formation layer of the P diffusion resistance. P diffusion resistance formation layer potential verification means for comparing the potentials of both ends of the P diffusion resistance obtained by the circuit simulator with the potentials of the formation layer of the P diffusion resistance to verify the formation layer potential of the P diffusion resistance. A layout verification device characterized by being provided.