JP4684911B2 - LSI for shielded wiring - Google Patents

Description

  The present invention is used for shield wiring of a large-scale integrated circuit device (hereinafter referred to as “LSI”). In particular, the present invention surrounds a net susceptible to noise and crosstalk noise from other nets. The present invention relates to an LSI for performing shield wiring when performing shield wiring that makes it difficult to receive.

  A conventional example will be described below. Conventionally, in a LSI, there has been known a shield wiring that surrounds a net that is particularly susceptible to crosstalk noise, such as a clock wiring, with a net connected to a power source (hereinafter referred to as “clipped”). This shield wiring prevents noise generated in other adjacent nets.

  In this case, the normal shield wiring is connected to the power supply net at a plurality of locations. The power supply wiring causes a voltage drop called IR drop (voltage drop due to current I and resistance R = I × R) due to the power consumption of the nearby element, and the power supply at a plurality of locations may have slightly different potentials. In that case, an excessive current may pass through the shield wiring.

  (a): In conventional shield wiring, power supply wiring is usually thick, but the shield wiring uses the same thickness as the signal line, so the current density may exceed the specified value. . As a result, the degradation of wiring called electromigration occurs, and the life and reliability of the LSI are degraded.

  (b): Switching noise is applied to the power supply due to the operation of the element. In recent years, it has been necessary to absorb noise as the integration density of LSIs has increased, but it has been difficult to completely eliminate such switching noise.

  (c): In order to test the registers on the LSI, they are usually connected in a daisy chain with wiring called a scan net. This scan net is used for tests to determine defective products after manufacture, but is unnecessary because it does not operate during the operation of the LSI, but conventionally this scan net has not been effectively used after the end of the test. . Also, if shield wiring is provided separately from the scan net, it may take up space and hinder the miniaturization of the LSI.

  (d): Conventionally, since the wiring density was not so high, the influence of crosstalk was small and shield wiring was not necessary. Further, since the power consumption was sufficiently small and there was no potential difference between the power supplies, the current flowing through the shield wiring was small, and no current density constraint violation was caused. However, when the LSI wiring density becomes high, the current density constraint violation may occur, but no countermeasure has been taken.

  The present invention solves such a conventional problem and aims at the following. In other words, if the shield wiring is connected to the power supply net at multiple locations, excessive current may flow through the shield wiring due to the potential difference between the power supply nets, or current density constraint violations may occur between the shield wirings or the power supply. However, even in an LSI having high-density wiring, it is possible to prevent such a current density constraint violation and to realize reliable shield wiring and to perform shield wiring processing in a short time. For the purpose.

  In order to achieve the above object, the present invention is configured as follows.

(1): a shield wiring in a connected state surrounds the target net of LSI, the LSI having the structure were connected to the power supply line or ground line a power supply voltage is applied, the shield wire, the power line or It has a clip point where the part that intersects the ground line, the power line or the part close to the ground line is clipped to the power line or the ground line by using a via , and the clip point and the clip point are separated from each other. The shield wiring has a configuration in which current does not flow between points, and the shield wiring has a configuration connected to a power supply line or a ground line only at one place .

(2) : In an LSI having a configuration in which a shield wiring that surrounds the LSI target net is connected to a power supply wiring to which a power supply voltage is applied , the shield wiring uses a via that connects the shield wirings between layers. without, configured as shed shield interconnect structure are not connected to each other, to said shed shielded wire, and characterized in that it does not connect to the power supply line only at one location from the shield wiring connected to one To do.

(Function)
The operation of the present invention based on the above configuration will be described.

(a) : In the LSI of (1) above, the shield wiring is disconnected near the middle of the clip point where the shield wiring is connected to the power source, and all shield wiring is connected to the power source only at one location. In addition, a shield wiring that prevents excessive current from flowing in the shield wiring is used.

  In an LSI having such a structure, the current density constraint violation due to the current flowing through the shield wiring does not occur. In addition, even if no power network analysis is performed, the current density constraint violation does not occur structurally, and the shield is farther away from the clip, but it is easier to get on the noise. It is possible to reduce the distance and enhance the shielding effect.

(b) : In the LSI of (2) above, by not using vias that connect the wiring layers, the shielded wiring that is divided is connected to the power supply wiring only at one location from the shielded wiring that is connected to one. Thus, the shield wiring can be made to prevent an excessive current from flowing in the shield wiring.

  In an LSI with such a structure, a shield with a higher wiring resistance away from the clip is more susceptible to noise, so the shielding effect is enhanced by not using vias that have higher wiring resistance and affect yield. Can do. In addition, the break point can be easily determined.

  The present invention has the following effects by the structure of the claims.

  (1) In the LSI according to claim 1, in the LSI having a configuration in which a shield wiring that surrounds the target net of the LSI and is connected to a power supply line or a ground line to which a power supply voltage is applied is connected. The wiring has a clip point where a portion intersecting the power supply line or the ground line or a portion close to the power supply line or the ground line is clipped to the power supply line or the ground line using a via, and the gap between the clip point and the clip point is between The shield wiring has a configuration in which current does not flow between the clip points, and the shield wiring has a configuration connected to a power supply line or a ground line only at one place, so that excessive current is passed through the shield wiring. Shield wiring that prevents flow is used.

  (2) In the LSI according to claim 2, in the LSI having a configuration in which the shield wiring surrounding the periphery of the target net of the LSI is connected to the power supply wiring to which the power supply voltage is applied, the shield wiring connects the shield wirings to each other. By not using vias connected between layers, it is configured as a divided shield wiring structure that is not connected to each other, and the divided shield wiring is connected to one power supply wiring from only one shield wiring. By not connecting to the shield wiring, it is possible to provide a shield wiring that prevents an excessive current from flowing in the shield wiring.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 7 show data on a computer for designing an LSI, and a circle indicates a via. Further, in the following description, “separation” refers to eliminating the contact by slightly shortening the end of the line segment. “Cut” means a state where the line segment is broken into two but still in contact.

(Description of each example)
(1): Description of Example 1 (LSI Shield Wiring Method: Example of Thickening or Thinning) An explanatory diagram of Examples 1 and 2 is shown in FIG. Example 1 is an example in which processing for performing shield wiring of an LSI is realized by a computer (for example, CAD) program.

  In this case, when connecting the power supply wiring to the shield wiring that surrounds the LSI target net by a computer program, when connecting to the power supply at multiple locations, the current supplied through the shield wiring is Using the calculation result and the calculation result, the shield wiring is made thicker or thinner so as to satisfy the current density design rule. Specifically, it is as follows.

  In the example of FIG. 1, the target net is a clock wiring wired in the first layer and the second layer, and shield wiring is provided on both sides of the clock wiring so as to surround the clock wiring. The power supply wiring is the second-layer main power-supply wiring and the first-layer sub-power-supply wirings 1 and 2, and the circles in the figure indicate vias for electrically connecting the first-layer wiring and the second-layer wiring. It is.

  In other words, in Example 1, the current generated in the portion of the thin power supply wiring obtained by clipping the shield wiring or the shield wiring is calculated, and the current density is increased by increasing the thickness of the shield wiring so that the current density is not more than a specified value. Lowering the shield wiring or conversely reducing the current density constraint in the thin power wiring connected to the shield wiring can be prevented.

  For example, by increasing the thickness of the shield wiring (second layer) in part A in FIG. 1, the density of the current flowing from the sub power supply wiring 1 (first layer) to the sub power supply wiring 2 (first layer) becomes a constraint value. Do not exceed. In addition, a current flows from the main power supply wiring (second layer) to the sub power supply wiring 1 (first layer) in the portion B (first layer and second layer shield wiring). If this potential difference is large, If this portion is made thick, the sub power supply wiring 1 may cause a current density constraint violation.

  In such a case, conversely, by narrowing the portion B to increase the wiring resistance, the current is reduced and the current density does not exceed the constraint value. Usually, since the standard line width is determined by each wiring layer, it may be moved to a layer having an appropriate wiring width together with the clock wiring instead of being thickened or thinned.

(2): Explanation of example 2 (example of thickening first in shield wiring process of example 1) Example 2 is an example in which the process of performing shield wiring of LSI is realized by a program of a computer (for example, CAD). .

  In this case, in Example 2, when the process of connecting the shield wiring (1st and 2nd layers) surrounding the periphery of the target net to the power supply wiring by the computer program in Example 1, simple calculation is performed during wiring. To increase the thickness of the shield wiring that is likely to violate the current density constraint, and after the wiring is completed, perform a time-consuming power network analysis to narrow the shield wiring at the required location. A step is performed so as not to cause a density constraint violation.

  That is, time-consuming current density calculation is not performed during wiring. A simple calculation that does not take a long time investigates the possibility of thickening the shield wiring later on the shield wiring, and performs shield wiring processing to thicken them.

  For example, in FIG. 1, the portions A and B are thickened. Then, from the result of the power supply network analysis at the end of all the wirings, a portion that does not need to be thickened is returned to the original thickness. When narrowing, the restriction on the distance from other general signal lines is not violated, so that it is not necessary to rewire. Therefore, the shield wiring of Example 1 can be realized in a short time. In addition to the shield wiring, a part of the power supply wiring may be thickened in some cases.

(3): Explanation of Example 3 (LSI separation structure) An explanatory diagram of Examples 3 and 4 is shown in FIG. In example 3, the shield wiring is disconnected near the clip point connected to the power supply and the middle of the clip point, and all shield wiring is connected to the power supply only at one location, This is an example of an LSI structure using shield wiring that prevents current from flowing.

  In FIG. 2, the portion that intersects the power supply or the portion that is close to the power supply is clipped using power supply wiring and vias (circles in the figure), and the point C between the clip points is disconnected. Prevents excessive current from flowing between the clip points. In this structure, since no current flows between the clips, it is not necessary to perform a time-consuming power network analysis.

(4): Explanation of Example 4 (Shield Wiring Disconnection Processing) Example 4 is an example in which processing for performing shield wiring of LSI is realized by a program of a computer (for example, CAD).

  In this case, in order to realize the LSI structure of Example 3, in Example 4, a shield wiring that is all connected first is generated by a computer program, and then a point that intersects or is very close to the power supply wiring The step of connecting to the wiring and the intermediate point of the connection point to the power source are obtained and disconnected, and the step of connecting all the shield wirings to the power source only at one place is executed.

  In FIG. 2, the portion that first intersects with the power supply or the portion that is close to the power supply is clipped to the power supply wiring using a via or the like, the point C between the clip points is disconnected, and an excessive current is generated between the clip points. To prevent the flow. In this case, if the procedure described later is performed, the middle of the clip point can be found and cut off.

(5): Explanation of Example 5 (Separation Processing Considering Capacity) An explanatory diagram of Example 5 is shown in FIG. Example 5 is an example in which the process of performing shield wiring of an LSI is realized by a computer (for example, CAD) program.

  In this case, in order to realize the LSI structure of Example 2, in Example 5, a shield wiring that is all connected first is generated by a computer program, and then a point that intersects or is very close to the power supply wiring The step of connecting to the wiring, the next step is to examine the branch-like wiring that is a dead end, and the step of remembering the area or capacity at the branch point of the base of the branch, and ignoring the branch-like wiring of the dead end Then, while adding the root value and the area of the part that is not ignored, the step of obtaining the capacitive intermediate point of the connection point to the power source and disconnecting it is executed.

  As shown in FIG. 3, when a dead-end shield wire is connected to the shield wire, the area or capacitance of the shield wire in that portion is calculated, and the value is indicated by the root (root) indicated by F in FIG. ). As in Example 3, when determining the intermediate point from the clip point, not the intermediate distance (position D in the figure), but the intermediate point of the area or capacitance.

  Instead of searching for a dead-end shield line, if it is added to the value of the root, an intermediate point of capacitance such as point E in FIG. 3 can be obtained. If the electrostatic capacity of each shield wiring (capacitance with GND) is balanced, the noise on the shield wiring can be quickly released to the power supply through the clip, and the effect of the shield wiring can be enhanced. it can.

(6): Explanation of Example 6 (Separation Processing Considering Capacity) An explanatory diagram of Example 6 is shown in FIG. Example 6 is an example in which processing for performing shield wiring of LSI is realized by a computer (for example, CAD) program.

  In this case, in order to realize the LSI structure of Example 3, in Example 6, the shield wiring connected first is generated by the computer program, and then the point crossing the power supply wiring or a point very close to the power supply wiring is shown. The next step is to check the part that is in the loop, break the loop at one point, eliminate all the loops, and then check the branch-like wiring that is dead end Alternatively, the capacity is memorized at the branch point at the base of the branch and the dead-end branch wiring is ignored, and the value of the base and the area of the non-ignored part are added, and the capacitive middle of the connection point to the power supply is added. A point is obtained and a step of cutting off the point is executed.

  As shown in FIG. 4, if a loop exists in the shield wiring, the shield wiring method of Example 4 cannot be realized unless some device is used. Therefore, as preprocessing, a loop is detected and the point (point G in FIG. 4) is disconnected. As a result, the shield including the loop that cannot be processed by the shield wiring method of Example 4 can be processed by preprocessing.

(7): Explanation of Example 7 (no connection at the time of generation) An explanatory diagram of Example 7 is shown in FIG. In Example 7, by using no vias that connect the wiring layers, the shielded wiring that is divided is connected to the power supply wiring only at one location from the shielded wiring that is connected to one, so that It is an example regarding the LSI structure using the shield wiring which prevents that the electric current flows.

  As shown in FIG. 5, the points H are not connected by vias. The shield wiring is not connected to each other by not using vias that connect between shields, and only one location is clipped from the island of each shield, so that the current density can be calculated without calculating the current density. The shield wiring is guaranteed not to violate constraints.

  In this way, the wiring layers are not normally connected, but in a region where connection to the power source is difficult, if only part of the wiring layers may be connected to other shield wirings using vias.

(8): Explanation of Example 8 (changing the left and right potentials) FIG. By the way, switching noise is put on the power supply due to the operation of the element. With recent improvements in LSI integration density, it has become necessary to absorb the noise. Therefore, in Example 8, the shield lines on both sides of the shielded wiring are connected to power supplies having different potentials so that the potentials of the adjacent shield wirings are always different, and the electrostatic capacitance when the shield wirings are adjacent to each other is used. This is an example of an LSI structure using shield wiring with improved noise resistance of the power supply.

  The shield wirings 2, 3, 4 and 5 shown in FIG. 6 are adjacent to each other. The potential of the shield wiring is determined from the relative position of the net to be shielded. In FIG. 6, the right and lower shield lines of the clock line are connected to a positive power supply (power supply voltage: VCC), and the left and upper shield lines are connected to GND (ground).

  As a result, as shown in FIG. 6, since the adjacent shield wirings have different potentials, they serve as a capacitor, absorb noise on the power supply, and prevent malfunction due to noise.

(9): Explanation of Example 9 (Shield Wiring Using Scanning) An explanatory diagram of Example 9 is shown in FIG. In order to test LSI registers, all the registers are normally connected in a daisy chain by wiring called a scan net. This net is used in a test for determining defective products after manufacture, but is unnecessary because it does not operate during the operation of the LSI. Also, the scan net does not generate noise.

  Therefore, Example 9 is an example of an LSI structure in which a part of the scan net is also used as a shield wiring to save a wiring area necessary for the shield wiring and the scan net.

  The scan net shown in FIG. 7 also partially serves as a shield wiring. Wiring resources can be saved by combining the scan net that does not generate noise at a constant potential and shield wiring during operation as much as possible. Each scan net connects two certain points. At that time, such a structure can be realized by utilizing as much as possible the shield wiring existing between the two points.

(Detailed explanation of processing)
(1): Detailed Processing of Example 3 FIG. 8 shows a processing flowchart (No. 1) of Example 3. Moreover, the process flowchart (the 2) of Example 3 is shown in FIG. Hereinafter, the processing of Example 3 will be described in detail with reference to FIGS. In addition, S1-S12 shows each process step.

  In the processing of Example 3, there are three elements: a wiring line segment, a via, and a clip. The clip indicates a connection point between the power source and the shield wiring, and has a different clip number. Each element has “check number”, “connection position”, “reach distance”, “shortest child element”, and “shortest child element distance”.

  First, all shield wirings are cut at clip positions, via positions, and intersections with other line segments, and one line segment is in contact with other line segments and vias only at both ends ( S1). In this case, contact is made even if the cutting is performed.

  Next, for all clips, “arrival distance” = 0, “check number” = clip number, “connection position” = clip position, “shortest child element” = all elements in contact with the clip , The shortest distance to the opposite side, “shortest child element distance” = distance to the opposite side of the shortest child element (= reach distance + shortest child element length), all clips are registered in the next search position set (S2).

  Then, it is determined whether or not the next search position set is empty (S3). If the next search position set is empty, the location registered as the break point is cut off and then slightly shortened to eliminate contact (S12). This process is terminated. However, if the next search position set is not empty in the process of S3, one element having the smallest “shortest child element distance” is taken out from the next search position set and set as the current element. The “shortest child element” of the current element is set as the next element (S4).

  Next, it is determined whether or not there is an element that does not have a “check number” other than the next element among all the elements that are in contact with the “connection position” of the current element (S5). As a result, if there is a “check number” other than the next element, the “shortest child element” of the current element = the shortest distance to the opposite side among them, “shortest child element distance” = The distance to the opposite side of the shortest child element is set, and the current element is returned to the next search position set (S6).

  Next, it is determined whether there is a “check number” of the next element (S7). Further, in the process of S5, if there is no element that does not have a “check number” other than the next element among all elements in contact with the “connection position” of the current element, the process of S6 is performed. If not, the process proceeds to S7. If there is no “check number” of the next element in the processing of S7, “check number” of the next element = “check number” of the current element, “connection position” = position opposite to the next element, “reach distance” "=" Shortest child element distance "of the current element (S8).

  If there is a “check number” of the next element in the process of S7, the process proceeds to S3. Next, it is determined whether or not there is a “check number” among all the elements in contact with the “connection position” of the next element (S9). An element having the same “connection position” as the “connection position” is defined as a reaching element. Then, from the connection position of the next element of the next element, register the distance part of (reaching distance of the reaching element + the length of the next element−the “reaching distance” of the current element) / 2 as a break point. (S10).

  In this case, the minimum distance from the clip to both ends of the next element is the “reaching distance” of the reaching element and the “reaching distance” of the current element, and the next element does not return to the next search position set. Thereafter, the process proceeds to S3.

  Also, if there is no check number in the process of S9, the next element “shortest child element” = the shortest distance to the opposite side among all elements in contact with the next element “connection position” “Shortestest child element distance” = distance to the opposite side of the shortest child element, the next element is registered in the next search position set (S11). Thereafter, the process proceeds to S3.

(2): Explanation of Processing in Example 3 FIG. 10 is a diagram for explaining processing in Example 3. The example of FIG. 10 is an example of the processing shown in FIGS. 8 and 9 and shows an example of a simple case. In FIG. 10, the elements are C1, C2, S1, S2, S3, two clips (C1, C2: clip), and three shield wires (S1, S2, S3: shield wire). The position is represented by P1, P2, P3, and P4.

  In this case, the line lengths of S1, S2, and S3 are 5, 6, and 7. The element name is expressed by a check number, connection position, reach distance, shortest child element, and shortest child element distance. In addition, a thick power supply may be connected by a plurality of vias. In that case, it is meaningless to disconnect the vias, and therefore it is better to consider them as one via.

(3): Detailed Processing of Example 5 FIG. 11 shows a processing flowchart of Example 5. Hereinafter, the processing of Example 5 will be described with reference to FIG. S21 to S24 indicate each processing step.

  First, cutting is performed at clip points, intersections, and via positions of all shield lines so that they are in contact with other elements only at both ends of the shield line (S21). Next, all the shield and via search target marks are initialized to 0 (S22). Then, a branch area calculation function (one clip, that point) is called (S23).

  Next, in the processing flowchart of Example 3 shown in FIGS. 8 and 9, the element with the mark not to be searched is completely ignored as the area of the element + the area recorded in the element instead of the length of the element. (S24), and this process is terminated.

(4) Processing of branch area calculation function FIG. 12 shows a processing flowchart (part 1) of the branch area calculation function. FIG. 13 shows a processing flowchart (part 2) of the branch area calculation function. Hereinafter, the processing of the branch area calculation function will be described with reference to FIGS. S31 to S43 indicate each processing step.

  First, as initialization processing, the number of branches = 0, the number of clips = 0, and the area = 0 are set (S31), and all elements connected to the start point are registered in the set (S32). Next, one element is extracted from the set, removed from the set (S33), and it is determined whether there is an element to be extracted from the set (S34).

As a result, if there is an element to be extracted from the set, it is determined whether or not the element to be extracted and the start element are the same (S35). If they are the same, the process proceeds to S33. However, if the element to be extracted and the start element are not the same, it is determined whether or not the element is a clip (S36).
As a result, if the element is a clip, the number of clips is incremented (number of clips = number of clips + 1) (S37), and the process proceeds to S32. However, if the element is not a clip in the process of S36, the number of branches is incremented (the number of branches = the number of branches + 1) (S38).

  Next, | area element, clip presence flag | = branch area calculation function (the element, a point on the opposite side of the element) is set (S39). Next, the number of clips = number of clips + clip existence flag is set (S40), and the process proceeds to S33.

  If there is no element to be extracted from the set in the process of S34, it is determined whether or not the number of clips> 0 (S41). If the number of clips> 0, the area is recorded at the position of the start element. Then, with {0, the number of clips} as an answer, the process returns to the function caller (S42), and this process is terminated.

  If the number of clips is not greater than 0 in the process of S41, a mark that is not a search target is added to the start element. Then, {area of the start element, 0} is set as an answer, the function caller is returned (S43), and this process is terminated.

(5): Detailed Processing of Example 9 FIG. 14 shows a processing flowchart of Example 9. Hereinafter, the process of Example 9 will be described with reference to FIG. S51 to S56 indicate each processing step.

  First, all shield line segments are cut at clip points, intersections, and via positions so that they are in contact with other elements only at both ends of the shield line segments (S51). Next, all shields and via marks are initialized to 0 (S52), and clips of all shields are put into a set (S53).

  Next, one clip is taken out from the set and deleted from the set (S54). Then, it is determined whether or not the clip to be taken out is in the set (S55). If the clip to be taken out is in the set, a loop break function (clip, position of the clip, clip number of the clip) is obtained ( S56) and the process proceeds to S54. If there is no clip to be taken out in the process of S55, this process ends.

(6): Processing of loop check function FIG. 15 shows a processing flowchart of the loop check function. Hereinafter, processing of a loop check function (a function used to detect and break a loop in Example 6) will be described with reference to FIG. S61 to S68 indicate each processing step.

  First, all the elements connected to the starting point are put into the set (S61). Next, one element is extracted from the set and removed from the set (S62). Then, it is determined whether there is an element to be extracted from the set (S63). If there is, it is determined whether the element is the same as the start element (S64). If there is no element to be taken out from the set, the process returns to the function caller (S68), and this process ends.

  If the element is the same as the start element in the process of S64, the process proceeds to S62. If not, it is determined whether the element and the mark are 0 (S65). As a result, if the element and the mark are 0, the mark of the element = mark number, the loop check function (the element, the point on the opposite side of the element, the mark number) is executed (S66), and the process proceeds to S62. To do.

  If the element and the mark are not 0 in the process of S65, the start point side of the start element is shortened to break the loop (S67), and the process proceeds to S62. In this way, the loop check function is processed.

(Specific device example and description of recording medium)
FIG. 16 shows a specific apparatus example. The “processing for performing shield wiring of LSI” described in Examples 1 to 9 of the embodiment can be realized by an arbitrary computer such as a workstation or a personal computer.

  This apparatus includes a computer main body 1, a display device 2 connected to the computer main body 1, an input device (keyboard / mouse, etc.) 3, a removable disk drive (referred to as “RDD”) 4, and a hard disk device (referred to as “HDD”). It is composed of 5 etc.

  The computer main body 1 has a CPU 6 for performing various internal controls and processes, a ROM 7 (nonvolatile memory) for storing programs and various data, a memory 8, and an interface control unit (“I / F”). 9) and a communication control unit 10 are provided. The RDD 4 includes a flexible disk drive and an optical disk drive.

  In the apparatus having the above-described configuration, for example, a program for realizing the processing is stored in a magnetic disk (recording medium) of the HDD 5, and the CPU 6 reads out and executes the program, thereby executing the “LSI” executed by the computer. The process for performing the shield wiring is executed.

  However, the present invention is not limited to such an example. For example, the program can be stored in the magnetic disk of the HDD 5 as follows, and the program can be executed by the CPU 6 executing the program. .

  (a): A program (program data created by another device) stored in a removable disk created by another device is read by the RDD 4 and stored in a recording medium of the HDD 5.

  (b): Data such as a program transmitted from another device via a communication line is received via the communication control unit 10, and the data is stored in a recording medium (magnetic disk) of the HDD 5.

(Appendix)
The following configuration of the present invention is added to the above description.

  (Supplementary note 1): When connecting a shield wiring that surrounds the LSI target net to the power supply wiring to the computer, when connecting to the power supply at a plurality of locations, the current supplied through the shield wiring is A computer-readable recording medium on which a program for realizing a step of calculating and a step of increasing or decreasing a thickness of a shield wiring so as to satisfy a current density design rule using the calculation result is recorded.

  (Supplementary note 2): The shield wiring is disconnected near the clip point connected to the power source and the middle of the clip point, and all shield wirings are connected to the power source only at one place. An LSI characterized by using shielded wiring that prevents excessive current from flowing.

  (Supplementary note 3): By not using vias that connect the wiring layers, the shielded wiring that is divided is connected to the power supply wiring at only one point from the shielded wiring that is connected to one, and the shield wiring An LSI characterized by using shield wiring that prevents current from flowing.

  (Appendix 4): Connect the shield wires on both sides of the shielded wiring to power sources with different potentials, make sure that the potential of the adjacent shield wires is different, and use the capacitance when the shield wires are adjacent to each other. LSI that uses shield wiring with improved noise resistance of the power supply.

  (Supplementary Note 5): LSI having a structure in which a part of a scan net is also used as a shield wiring, and a wiring area necessary for the shield wiring and the scan net is saved.

  (Appendix 6): In the recording medium of (Appendix 1), when performing the process of connecting the shield wiring that surrounds the LSI target net to the power supply wiring, the computer calculates the current by simple calculation during the wiring. Steps to thicken the shield wiring that is likely to violate the density constraint and perform the power network analysis that takes time after the wiring is completed, narrow the shield wiring at the necessary location, and violate the current density constraint A computer-readable recording medium having recorded thereon a program for realizing the step of preventing the occurrence of noise.

  (Appendix 7): In order to realize the LSI structure of (Appendix 2) above, a shield wiring that is all connected first is generated in a computer, and a point that intersects or very close to the power supply wiring is used as the power supply wiring. A computer recording a program for realizing the step of connecting and the step of finding the middle of the connection point to the power source, disconnecting it, and connecting all the shield wirings to the power source only at one place A readable recording medium.

  (Appendix 8): In order to realize the LSI structure of (Appendix 2) above, a shield wiring that is all connected first is generated in a computer, and a point that intersects or very close to the power supply wiring is used as the power supply wiring. The step of connecting, and then examining the branch-like wiring that is dead-end, making the area or capacity memorize at the branch point of the base of the branch, ignoring the branch-like wiring of the dead-end, A computer-readable recording medium on which a program for realizing a step of obtaining a capacitive intermediate point of a connection point to a power source and disconnecting it is added while adding the value of and a non-negligible area.

  (Appendix 9): In order to realize the LSI structure of (Appendix 2), a shield wiring connected first is generated in a computer, and then a point that intersects or very close to the power supply wiring is connected to the power supply wiring. The next step is to check the part that is a loop, break it at one place, eliminate all the loops, and then check the branch-like wiring that is dead-end, its area or capacity Ignoring the step at the base of the branch and the dead-end branch-like wiring, adding the base value and the area of the non-ignored part, the capacitive intermediate point of the connection point to the power supply A computer-readable recording medium having recorded thereon a program for realizing the step of obtaining and separating the information.

  (Supplementary Note 10): When connecting a shield wiring that surrounds the target net of an LSI to a power supply wiring to a computer, when connecting to a power supply at a plurality of locations, the current supplied through the shield wiring is A program for realizing a step of calculating and a step of making the shield wiring thicker or thinner so as to satisfy the current density design rule using the calculation result.

(Characteristics of the above supplementary notes)
(a): In (Appendix 6), the shield wiring of the LSI is performed by the computer reading and executing the program of the recording medium. In other words, when a computer program performs processing to connect the shield wiring that surrounds the target net to the power supply wiring, the shield wiring that is likely to violate the current density constraint is thickened by simple calculation during wiring. A wiring step and a time-consuming power supply network analysis after wiring is completed, and a shield wiring at a necessary portion is thinned so that a wiring constraint violation and a current density constraint violation do not occur.

  In such a process, when realizing the LSI structure, the time-consuming power supply network analysis does not have to be performed during wiring, and only needs to be performed once at the end, so that time for performing shield wiring can be saved.

  (b): In (Appendix 7), the computer reads and executes the program on the recording medium, thereby performing LSI shield wiring. That is, when performing shield wiring for realizing the LSI structure described in (Appendix 2), a shield wiring that is all connected first is generated by a computer program, and then intersects with or very close to the power supply wiring. Are connected to the power supply wiring, and an intermediate point between the connection points to the power supply is obtained, and the connection is disconnected, and all the shield wirings are connected to the power supply only at one place.

  If such a process is used, the current density constraint violation due to the current flowing through the shield wiring does not occur. In addition, even if no power network analysis is performed, the current density constraint violation does not occur structurally, and the shield is farther away from the clip, but it is easier to get on the noise. Thus, an LSI capable of reducing the distance and enhancing the shielding effect can be realized.

  (c): In (Appendix 8), the computer reads and executes the program on the recording medium, thereby performing LSI shield wiring. That is, when performing shield wiring for realizing the LSI structure described in (Appendix 2), a shield wiring that is all connected first is generated by a computer program, and then intersects with or very close to the power supply wiring. To the power supply wiring, and then to examine the branch-like wiring that is dead-end, to learn the area or capacity at the branch point of the base of the branch, and to connect the dead-end branch-like wiring While ignoring, adding the base value and the area of the non-ignored part, a capacitive intermediate point of the connection point to the power source is obtained, and a step of disconnecting it is executed.

  In this way, in shielded wiring, shields with a larger electrostatic capacity (capacitance) away from the clip are more susceptible to noise, so when determining the intermediate point of the clip point, by determining the intermediate point considering the capacitance, The shielding effect can be enhanced.

  (d): In (Appendix 9), the shield wiring of the LSI is performed by the computer reading and executing the program of the recording medium. That is, when performing shield wiring for realizing the LSI structure of (Appendix 2), the shield wire connected first is generated by a computer program, and then a point intersecting or very close to the power supply wiring is determined. Step to connect to the power supply wiring, then check the looped part, disconnect at one place, eliminate all the loops, then check the branch-like wiring that is dead end, Capacitance of the connection point to the power supply while adding the root value and the area of the non-ignored part, ignoring the branch-like wiring at the base of the branch, ignoring the area or capacity of the branch at the base of the branch The middle step is determined and the step of cutting off is executed.

  In such a shield wiring process, the process of (Appendix 8) cannot be applied to a shield pattern in which a loop exists. However, if this process is used, the shield wiring process of (Appendix 8) can be used. It becomes possible.

It is explanatory drawing of the examples 1 and 2 in embodiment of this invention. It is explanatory drawing of the examples 3 and 4 in embodiment of this invention. It is explanatory drawing of Example 5 in embodiment of this invention. It is explanatory drawing of Example 6 in embodiment of this invention. It is explanatory drawing of Example 7 in embodiment of this invention. It is explanatory drawing of Example 8 in embodiment of this invention. It is explanatory drawing of Example 9 in embodiment of this invention. It is a processing flowchart (the 1) of example 3 in an embodiment of the invention. It is a process flowchart (the 2) of Example 3 in embodiment of this invention. It is process explanatory drawing of Example 3 in embodiment of this invention. It is a process flowchart of Example 5 in an embodiment of the invention. It is a process flowchart (the 1) of the branch area calculation function in embodiment of this invention. It is a process flowchart (the 2) of the branch area calculation function in embodiment of this invention. It is a processing flowchart of Example 9 in the embodiment of the present invention. It is a processing flowchart of the loop check function in the embodiment of the present invention. It is a specific example of an apparatus in an embodiment of the invention.

Explanation of symbols

1 Computer Main Body 2 Display Device 3 Input Device 4 Removable Disk Drive (RDD)
5 Hard disk drive (HDD)
6 CPU (Central Processing Unit)
7 ROM (Read Only Memory)
8 Memory 9 Interface control unit (I / F control unit)
10 Communication control unit

Claims (2)

In an LSI having a configuration in which a shield wiring that is in a connected state surrounding an LSI target net is connected to a power supply line or a ground line to which a power supply voltage is applied, the shield wiring intersects the power supply line or the ground line. A clip point that is clipped to the power line or ground line using a via, and the clip point and the clip point are separated from each other. Has a configuration that does not flow,
The shield wiring LSI, characterized in that have a structure that is connected to the power supply line or the ground line only in one place. In an LSI having a configuration in which a shield wiring that surrounds an LSI target net is connected to a power supply wiring to which a power supply voltage is applied,
The shield wiring is configured as a divided shield wiring structure that is not connected to each other without using vias that connect the shield wirings between layers,
An LSI, wherein the divided shield wiring is connected to the power supply wiring at only one position from the shield wiring connected to one.

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