JP2008108783A - Simulation program and simulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the analysis time of a power supply noise analysis model. <P>SOLUTION: A computer 1 is allowed to function as an extraction means 2, a contact detection means 3, a model creation means 4, and a simulation execution means 5. The extraction means 2 extracts a contact pattern from layout data 6 in a semiconductor integrated circuit. A contact detection means 3 detects a contact nearest the circuit affected by noise from a pattern inside the semiconductor integrated circuit, or a group of contacts including the nearest contact. The model creation means 4 removes an element propagating noise via a substrate, to the contact detected by the contact detection means 3 from the generation source of noise for creating a model for data analysis. The simulation execution means 5 uses the created model for data analysis to conduct simulation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a simulation program and a simulation apparatus, and more particularly to a simulation program and a simulation apparatus for modeling and analyzing voltage fluctuations generated by a power supply.

  2. Description of the Related Art There is known a circuit simulation apparatus that models voltage fluctuations (power supply noise) generated in a power supply due to the operation of a semiconductor integrated circuit and calculates circuit characteristics using the generated power supply noise analysis model.

FIG. 14 is a diagram showing a model creation flow of the conventional circuit simulation apparatus.
When obtaining a power supply noise analysis model, first, patterns of metal wiring, via, contact, and well are extracted from layout data of a semiconductor integrated circuit to be analyzed (step S91). Next, based on each extracted pattern and given process parameters, wiring resistance, wiring capacity, and substrate resistance are calculated (step S92), and a power supply noise analysis model is created (step S93).

Conventionally, in order to create a power supply noise analysis model of a semiconductor integrated circuit installed on a substrate on which a MOSFET having a gate length of about 130 nm, which is used as an index of miniaturization of the integrated circuit, is mounted, wiring in the semiconductor integrated circuit is used. In addition, it is necessary to extract all the elements on the substrate, and there is a problem that the number of elements becomes enormous and analysis takes a long time.
Japanese Patent Laid-Open No. 10-50849

  In recent years, a high-resistance substrate on which a MOSFET having a gate length of about 65 nm or about 90 nm is mounted has been developed. In such a high-resistance substrate, the reduction in leakage current has been verified, and an easy power supply noise analysis model can be expected.

  The present invention has been made in view of these points, and an object of the present invention is to provide a simulation program and a simulation apparatus that can shorten the analysis time of a power supply noise analysis model.

  The present invention provides a simulation program for modeling and analyzing voltage fluctuations generated by a power supply, an extraction step of extracting a contact pattern from layout data of the semiconductor integrated circuit, and an influence of noise in the semiconductor integrated circuit from the pattern. A contact detection step of detecting only the contacts included in a predetermined region with respect to the circuit receiving the noise, and propagation of the noise through the substrate between the noise generation source and the contacts detected by the contact detection step The computer is caused to execute a model creation step of creating a data analysis model excluding the elements to be performed and a simulation execution step of performing a simulation using the created data analysis model.

  In the present invention, since only the contact closest to the circuit affected by noise is detected, the configuration of the data analysis model becomes simple, and the simulation time can be greatly shortened.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, an outline of the present invention will be described, and then an embodiment will be described.
FIG. 1 is a diagram showing an outline of the present invention.

The computer 1 can function as the extraction unit 2, the contact detection unit 3, the model creation unit 4, and the simulation execution unit 5.
The extraction unit 2 extracts a contact pattern from the layout data 6 of the semiconductor integrated circuit to be evaluated. In FIG. 1, the layout data 6 is stored in the computer 1, but the present invention is not limited to this and may be received from the outside.

  The contact detection means 3 detects a contact closest to a circuit affected by noise in the semiconductor integrated circuit or a contact group including the closest contact from the pattern. Here, the noise mainly refers to noise that propagates from the wiring or board to the circuit.

  The model creation means 4 creates a data analysis model by removing elements that propagate noise through the substrate from the noise source to the contact detected by the contact detection means 3.

The simulation execution means 5 performs a simulation using the created data analysis model.
According to such a configuration, a contact pattern is extracted from the layout data 6 by the extracting unit 2. The contact detection means 3 detects the contact closest to the circuit affected by noise or the contact group including the closest contact among the extracted patterns. The model creation means 4 creates a data analysis model excluding elements that propagate noise through the substrate from the noise source to the contact detected by the contact detection means 3. The simulation is performed by the simulation execution means 5 using the created data analysis model. The user verifies the circuit using the obtained simulation result.

Embodiments of the present invention will be described below.
FIG. 2 is a diagram illustrating a hardware configuration example of the simulation apparatus.
The entire simulation apparatus 11 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, and a communication interface 106 are connected to the CPU 101 via a bus 107.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 51 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 51 in accordance with a command from the CPU 101. A keyboard 52 and a mouse 53 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 52 or the mouse 53 to the CPU 101 via the bus 107.

  The communication interface 106 is connected to the network 54. The communication interface 106 transmits / receives data to / from other computers via the network 54.

  With the hardware configuration as described above, the processing functions of the present embodiment can be realized. In order to perform circuit simulation in a system having such a hardware configuration, the following functions are provided in the simulation apparatus 11.

FIG. 3 is a block diagram illustrating functions of the simulation apparatus.
The simulation apparatus 11 includes a layout data storage unit 12, a pattern extraction unit 13, a contact detection unit 14, a metal wiring storage unit 15, a via storage unit 16, a contact storage unit 17, a well storage unit 18, a wiring A calculation unit 19, a substrate resistance calculation unit 20, a process parameter storage unit 21, a wiring resistance element storage unit 22a, a junction capacitance element storage unit 22b, a substrate resistance element storage unit 23, a noise model synthesis unit 24, A power supply noise analysis model storage unit 25 and a simulation execution unit 26 are included.

  The layout data storage unit 12 stores layout data (eg, GDSII). This layout data includes, for example, all of the arrangement of transistors of the semiconductor integrated circuit to be analyzed, wiring patterns, contacts, and the like.

  The pattern extraction unit 13 determines the metal wiring, via, contact, and well patterns from the layout data, that is, the electrical characteristic values such as the size, resistance value, and capacitance value of each device element, and information on the connection between the device elements. To extract.

The contact detection unit 14 detects a contact to be detected from the contact patterns extracted by the pattern extraction unit 13 and stores the detected contact in the contact storage unit 17.
The metal wiring storage unit 15, the via storage unit 16, and the well storage unit 18 store the metal wiring, via, and well patterns extracted by the pattern extraction unit 13, respectively.

The wiring calculation unit 19 includes a wiring resistance calculation unit 19a and a junction capacitance calculation unit 19b.
The wiring resistance calculation unit 19a calculates a wiring resistance between interconnections of the metal wiring, the via, and the contact, and extracts a wiring resistance element (parasitic resistance element).

The junction capacitance calculation unit 19b calculates a junction capacitance between interconnections of the metal wiring, the via, and the contact, and extracts a junction capacitance element (parasitic capacitance element).
The substrate resistance calculation unit 20 calculates the substrate resistance between the contact and the well and extracts the substrate resistance element.

  The process parameter storage unit 21 includes process parameters (e.g., wiring sheet resistance, substrate resistivity, per unit area) required for each calculation of the wiring resistance calculation unit 19a, the junction capacitance calculation unit 19b, and the substrate resistance calculation unit 20. Well junction capacity, etc.). That is, each calculation unit performs calculation using the process parameter stored in the process parameter storage unit 21.

The wiring resistance element storage unit 22a stores the wiring resistance element calculated by the wiring resistance calculation unit 19a.
The junction capacitance element storage unit 22b stores the junction capacitance element calculated by the junction capacitance calculation unit 19b.

The substrate resistance element storage unit 23 stores the substrate resistance element calculated by the substrate resistance calculation unit 20.
The noise model synthesis unit 24 creates a power supply noise analysis model by combining the wiring resistance element, the junction capacitance element, and the substrate resistance element.

The power supply noise analysis model storage unit 25 stores the generated power supply noise analysis model.
The simulation execution unit 26 executes a simulation using the power supply noise analysis model.

FIG. 4 is a diagram illustrating an example of a semiconductor integrated circuit to be analyzed. In addition, the up-down direction in the paper surface of FIG. 4 is called column direction, and the left-right direction is called row direction.
The semiconductor integrated circuit 30 includes a substrate 31, a circuit (Aggressor) 32 serving as a noise source provided on the substrate 31, a circuit (Victim) 33 affected by noise from the noise source, the circuit 32, and the circuit 33. And a well 35 provided in the substrate 31. Noise generated from the circuit 32 propagates to the circuit 33 via the semiconductor device 34. Examples of the substrate include a silicon substrate, a Ga / As (gallium / arsenic) substrate, and a glass substrate.

  The substrate 31 is a high-resistance substrate on which a MOSFET having a gate length of about 45 nm or about 60 nm can be mounted, and the substrate resistance per unit length of the substrate 31 is larger than the wiring resistance (for example, about 1000 times).

An example of the circuit 32 is a digital circuit. An example of the circuit 33 is an analog circuit such as a PLL (Phase Locked Loop).
The semiconductor device 34 is disposed on the well 35, and a plurality of metal wires 341, 341,... Extending in the column direction and a plurality of metal wires 342, 342 extending in the row direction substantially orthogonal to the metal wire 341. ... and a plurality of Vias 343, 343, ... used for connection between the Metal wirings 341, 341, ... and the Metal wirings 342, 342, ... in the wiring process.

Some of the metal wirings 342, 342,... Are electrically connected to the circuit 32.
5 is a cross-sectional view taken along line AA of the semiconductor integrated circuit shown in FIG. Note that portions similar to those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 34 includes a plurality of contacts 344, 344, and a plurality of contacts 344, 344 provided between each of the metal wires 342 and the Well 35, in addition to the metal wires 341, 341,... And the metal wires 342, 342,. ···have. Each contact 344 is connected to a plurality of impurity layers 351, 351,.

  FIG. 5 shows noise propagation paths and resistances and capacitances existing in the propagation paths. Noise from the circuit 32 propagates to the circuit 33 through the wiring resistance group, the substrate resistance group, and the junction capacitance group.

  Here, the wiring resistance group includes a wiring resistance R1a between the circuit 32 and the substrate 31, a wiring resistance R1b between the circuit 33 and the substrate 31, and each wiring resistance R1c between the semiconductor device 34 and the substrate 31. , A wiring resistance R1d of the metal wiring 342 between the circuit 32 and the contact 344, and a wiring resistance R1d of the metal wiring 342 between the contacts 344.

  The substrate resistance group includes a substrate resistance R2a of the substrate 31 between the circuit 32 and the semiconductor device 34, each substrate resistance R2b between each contact 344 in the substrate 31, and a substrate 31 between the circuit 33 and the semiconductor device 34. Substrate resistance R2c.

  The junction capacitance group has each junction capacitance C1a existing between the substrate 31 and the Well 35. In FIG. 5, the wiring resistances R1a, R1b, R1c, R1d, the substrate resistances R2a, R2b, R2c and each junction capacitance C1a are schematically shown as parasitic elements, and such resistances and capacitances are actually embedded. It is not necessarily. When the P / N characteristics of the substrate 31 and the Well 35 are the same, the junction capacitance C1a is not applied, so the junction capacitance C1a is not considered and the wiring resistors R1a, R1b, R1c, R1d, the substrate resistors R2a, R2b, Only R2c may be considered.

In order to perform such noise analysis of the semiconductor integrated circuit 30, a contact detected by the contact detection unit 14 will be described.
FIG. 6 is a diagram showing contacts to be detected by the semiconductor integrated circuit shown in FIG.

  The contact detection unit 14 expands the pattern of the circuit 33 at equal intervals in the vertical direction and the horizontal direction on the paper surface, and detects the closest contact 344 from the layout data. More specifically, five contacts 344 that overlap the locus L1 of points that are equidistant from the end of the circuit 33 are detected. By narrowing down the detection target in this way, other contacts are excluded from the calculation targets of the substrate resistance and the wiring resistance.

Such detection is performed because of the characteristic that the combined resistance of the substrate resistance and the wiring resistance hardly changes according to the distance from the circuit 33. Hereinafter, measurement examples of this characteristic will be described.
FIG. 7 is a diagram for explaining measurement conditions.

  When the distance between the perpendicular from the center of the circuit 33 and the perpendicular from the center of the contact 344 closest to the circuit 33 is 1, the wiring resistance and the substrate resistance when the contact 344 further away by the distance α is the detection target. The change in the combined resistance (impedance) will be described.

FIG. 8A is a diagram illustrating a relationship between a circuit affected by noise and a change in the combined resistance.
FIG. 8B is an enlarged view of a part of FIG.
As shown in FIG. 8B, when α> 0, the combined resistance hardly depends on a change in the value of α. As described above, even when only α = 0, that is, only the contact 344 closest to the circuit 33 is detected and the power supply noise analysis model is created, an error hardly occurs.

FIG. 9 is a diagram showing the substrate resistance and the wiring resistance to be calculated on the AA line in FIG.
As a result of narrowing down the contacts to be detected, the calculation target of the wiring resistance calculation unit 19a in FIG. 9 is the wiring resistance R1d of the metal wiring 342 between the contacts 344 and between the rightmost contact 344 and the substrate 31 in FIG. Wiring resistance R1c and wiring resistance R1b between the substrate 31 and the circuit 33. The calculation target of the junction capacitance calculation unit 19b is the junction capacitance C1a between the rightmost contact 344 and the substrate 31. The calculation target of the substrate resistance calculation unit 20 is the substrate resistance R2c between the contact 344 and the circuit 33.

Hereinafter, the wiring resistance calculation method of the wiring resistance calculation unit 19a, the wiring capacitance calculation method of the junction capacitance calculation unit 19b, and the substrate resistance calculation method of the substrate resistance calculation unit 20 will be specifically described.
<Wiring resistance R1d>
The wiring resistance R1d is ρ ₀ given from the process parameter storage unit 21, sheet resistance (Ω / □), row-direction length X defining mesh size, and column-direction length defining mesh size, respectively. It calculates | requires by the following Formula (1) using Y.
R1d = ρ ₀ (Ω / □) × X / Y (1)
<Wiring resistance R1c>
The wiring resistance R1c defines ρ given from the process parameter storage unit 21, the depth D from the surface of the substrate 31, the length X ₀ in the row direction that defines the execution area of the contact 344, and the execution area of the contact 344, respectively. Using the length Y _{0 in the} column direction, the following formula (2) is used.
R1c = ρ × D / X ₀ · Y ₀ (2)
<Junction capacitance C1a>
The junction capacitance C1a is obtained by using the following formula (Junction capacitance C _j per unit area given from the process parameter storage unit 21, the row-direction length X _W defining the Well effective area, and the column-direction length Y _W , respectively. Obtained in 3).
C1a = C _j × X _W · Y _W (3)
<Substrate resistance R2c>
The substrate resistance R2c is ρ given from the process parameter storage unit 21, the effective depth Z related to noise propagation from the surface of the substrate 31, the length X in the row direction defining the mesh size, and the column defining the mesh size. It calculates | requires by the following Formula (4) using the length Y of a direction.
R2c = ρ × X / Y · Z (4)
Then, the noise model synthesis unit 24 creates a network with respect to the obtained wiring resistance element and junction capacitance element. This is performed in the same manner for all the rectangular areas divided into meshes, and a power supply noise analysis model of the parasitic element of the semiconductor integrated circuit 30 is created.

  FIG. 10 is a diagram showing a power supply noise analysis model of the semiconductor device shown in FIG. That is, the power supply noise analysis model links each wiring resistance R1c, R1d, each junction capacitance C1a, and each substrate resistance R2c extracted for each rectangular area obtained by dividing the layout of the semiconductor integrated circuit 30 shown in FIG. Circuit connection information.

  Here, the dotted line portion in FIG. 10 is a portion that can be omitted by the detection of the contact detection unit 14 as compared with the conventional case (when the contact detection unit 14 is not installed). Thus, by reducing the number of contacts to be detected, the calculation amount of the wiring resistance calculation unit 19a, the junction capacitance calculation unit 19b, and the substrate resistance calculation unit 20 is reduced as compared with the conventional case.

FIG. 11 is a diagram (table) showing simulation results of the simulation execution unit.
As shown in FIG. 11, in this embodiment (this time), the number of elements is 48% (−52%) and the analysis time is 7% (−93%), compared to the conventional case where all wiring resistances are detected. became. On the other hand, the measurement error with respect to the prior art remained at 1.0%.

  As described above, according to the simulation device 11 of the present embodiment, the contact detection unit 14 sets only the contact closest to the circuit 33 as a detection target. Thereby, the number of contacts to be extracted can be minimized. Therefore, the number of elements of the power supply noise analysis model can be greatly reduced without impairing accuracy, and as a result, simulation can be performed at high speed.

  In this embodiment, only the contact closest to the circuit 33 is set as a detection target. However, in addition to the contact closest to the circuit 33, a contact that may be particularly involved in noise injection may be set as a detection target. . Thereby, a more accurate simulation result can be obtained.

Next, a case where the simulation apparatus 11 is applied to a semiconductor integrated circuit in which a transistor is installed on a substrate will be described.
FIG. 12 illustrates a semiconductor integrated circuit including a transistor.

  A semiconductor device 44 in the semiconductor integrated circuit 40 is provided on a p-type substrate 41 and includes a transistor 451 and a contact region 452. Note that portions having the same functions as those of the semiconductor device 34 are denoted by the same reference numerals.

  The transistor 451 is provided closer to the circuit 33 than the contact region 452, and includes a gate 451a and a device element region 451b. In the device element region 451b, two (total four) contacts 344 are provided along the column direction with the gate 451a interposed therebetween. A metal wiring 341 is provided on each contact 344.

  A well contact 452a is formed in the contact region 452, and a metal wiring 342 is provided on the well contact 452a. The metal wiring 342 is connected to the circuit 32 (not shown).

13 is a cross-sectional view taken along line BB of the semiconductor integrated circuit shown in FIG.
An n-type Well 411 a is formed on the substrate 41. The well contact 452a is connected to the well 411a through the n ⁺ region 412a. The contact 344 of the device element region 451b is connected to the Well 411a through the p region 413a.

The semiconductor integrated circuit 40 includes a wiring resistance R1e between the well contact 452a and the left contact 344 of the transistor 451, a wiring resistance R1f between the contacts 344, and a wiring between the well contact 452a and the n ⁺ region 412a. There is a resistor R1g. Junction capacitances C1b and C1b exist between each p region 413a and Well 411a, and a junction capacitance C1c exists between Well 411a and the substrate 41. Furthermore, substrate resistances R2d and R2e exist between the semiconductor device 44 and the other circuits 32 and 33, respectively.

  Here, when the wiring resistance R1e, the wiring resistance R1f, and the wiring resistance R1g are compared, the values of the wiring resistance R1e and the wiring resistance R1f are larger than the wiring resistance R1g (the impedance through the transistor is high), and the influence on noise is small. Therefore, the influence of the wiring resistance R1g is large, and noise injection via the well contact 452a becomes dominant. Therefore, there is little trouble even if the wiring resistance R1e and the wiring resistance R1f are omitted in the simulation. Therefore, when performing the power supply noise model analysis in the circuit 33, the contact 344 of the transistor 451 is not a detection target of the contact detection unit 14, and the well contact 452a is detected as the closest contact.

  As mentioned above, although the simulation program and simulation apparatus of this invention were demonstrated based on embodiment of illustration, this invention is not limited to this, The structure of each part is arbitrary structures which have the same function. Can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
Hereinafter, the features of the present invention will be described as additional notes.

(Supplementary note 1) In a simulation program for modeling and analyzing voltage fluctuations generated in a power supply,
An extraction process for extracting a contact pattern from the layout data of the semiconductor integrated circuit;
From the pattern, a contact detection step of detecting only the contact included in a predetermined region for a circuit affected by noise in the semiconductor integrated circuit;
A model creation step for creating a data analysis model except for an element that propagates noise through a substrate between a noise generation source and the contact detected by the contact detection step;
A simulation execution step of performing a simulation using the created model for data analysis;
A simulation program for causing a computer to execute.

(Additional remark 2) The said element contains a wiring resistive element, a junction capacitive element, and a board | substrate resistive element, The simulation program of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 3) The simulation program according to supplementary note 1, wherein the contact detection step further detects a series of the contacts that may be involved in noise injection of the circuit affected by noise.

(Additional remark 4) The said contact detection process detects the said contact installed on Well, The simulation program of Additional remark 1 characterized by the above-mentioned.
(Supplementary Note 5) The simulation program according to Supplementary Note 1, wherein the contact included in the predetermined region is a contact closest to a circuit receiving the noise or a contact group including the closest contact.

(Supplementary Note 6) In a simulation apparatus that models and analyzes voltage fluctuations generated by a power supply,
Extracting means for extracting a contact pattern from the layout data of the semiconductor integrated circuit;
From the pattern, contact detection means for detecting only the contacts included in a predetermined region with respect to a circuit affected by noise in the semiconductor integrated circuit;
Model creation means for creating a data analysis model except for an element that propagates noise through a substrate between a noise generation source and the contact detected by the contact detection means;
Simulation execution means for performing simulation using the created model for data analysis;
A simulation apparatus comprising:

  (Supplementary note 7) The simulation apparatus according to supplementary note 6, wherein the contact included in the predetermined region is a contact closest to a circuit receiving the noise or a contact group including the closest contact.

It is a figure which shows the outline | summary of this invention. It is a figure which shows the hardware structural example of a simulation apparatus. It is a block diagram which shows the function of a simulation apparatus. It is a figure which shows an example of the semiconductor integrated circuit used as analysis object. FIG. 5 is a cross-sectional view taken along line AA of the semiconductor integrated circuit shown in FIG. 4. FIG. 5 is a diagram showing contacts to be detected by the semiconductor integrated circuit shown in FIG. 4. It is a figure explaining measurement conditions. It is the figure which shows the relationship between the circuit which receives the influence of noise, and the change of synthetic | combination resistance, and the figure which expanded a part of the relationship. It is a figure which shows the board | substrate resistance and wiring resistance used as the calculation object in the AA line of FIG. It is a figure which shows the power supply noise analysis model of the semiconductor device shown in FIG. It is a figure (table | surface) which shows the simulation result of a simulation execution part. It is a figure which shows a semiconductor integrated circuit provided with a transistor. It is sectional drawing in the BB line of the semiconductor integrated circuit shown in FIG. It is a figure which shows the model creation flow of the conventional circuit simulation apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Computer 2 Extraction means 3 Contact detection means 4 Model preparation means 5 Simulation execution means 6 Layout data 11 Simulation apparatus 12 Layout data storage part 13 Pattern extraction part 14 Contact detection part 15 Metal wiring storage part 16 Via storage part 17 Contact storage part 18 Well storage unit 19 Wiring calculation unit 19a Wiring resistance calculation unit 19b Junction capacitance calculation unit 20 Substrate resistance calculation unit 21 Process parameter storage unit 22a Wiring resistance element storage unit 22b Junction capacitance element storage unit 23 Substrate resistance element storage unit 24 Noise model synthesis unit 25 Power supply noise analysis model storage unit 26 Simulation execution unit 30, 40 Semiconductor integrated circuit 31, 41 Substrate 32, 33 Circuit 34, 44 Semiconductor device 341, 342 Metal wiring 34 Via
344 contact 351 impurity layer 412a n ⁺ region 413a p region 451 transistor 451a gate 451b device element region 452 contact region 452a well contact C1a, C1b, C1c junction capacitance L1 locus R1a, R1b, R1c, R1f, R1f, R1e, R1f R2a, R2b, R2c, R2d Substrate resistance

Claims (5)

In a simulation program that models and analyzes voltage fluctuations that occur in a power supply,
An extraction process for extracting a contact pattern from the layout data of the semiconductor integrated circuit;
From the pattern, a contact detection step of detecting only the contact included in a predetermined region for a circuit affected by noise in the semiconductor integrated circuit;
A model creation step for creating a data analysis model except for an element that propagates noise through a substrate between a noise generation source and the contact detected by the contact detection step;
A simulation execution step of performing a simulation using the created model for data analysis;
A simulation program for causing a computer to execute.   The simulation program according to claim 1, wherein the element includes a wiring resistance element, a junction capacitance element, and a substrate resistance element.   The simulation program according to claim 1, wherein the contact detection step further detects a series of the contacts that may be involved in noise injection of the circuit affected by noise.   The simulation program according to claim 1, wherein the contact detection step detects the contact installed on a well. In a simulation device that models and analyzes voltage fluctuations that occur in a power supply,
Extracting means for extracting a contact pattern from the layout data of the semiconductor integrated circuit;
From the pattern, contact detection means for detecting only the contacts included in a predetermined region with respect to a circuit affected by noise in the semiconductor integrated circuit;
Model creation means for creating a data analysis model except for an element that propagates noise through a substrate between a noise generation source and the contact detected by the contact detection means;
Simulation execution means for performing simulation using the created model for data analysis;
A simulation apparatus comprising:

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